JP3352084B2 - Semiconductor element mounting substrate and semiconductor package - Google Patents

Semiconductor element mounting substrate and semiconductor package

Info

Publication number
JP3352084B2
JP3352084B2 JP2002137362A JP2002137362A JP3352084B2 JP 3352084 B2 JP3352084 B2 JP 3352084B2 JP 2002137362 A JP2002137362 A JP 2002137362A JP 2002137362 A JP2002137362 A JP 2002137362A JP 3352084 B2 JP3352084 B2 JP 3352084B2
Authority
JP
Japan
Prior art keywords
wiring
semiconductor
semiconductor element
mounting
copper foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002137362A
Other languages
Japanese (ja)
Other versions
JP2002334951A (en
Inventor
直樹 福富
良明 坪松
文男 井上
聡夫 山崎
洋人 大畑
伸介 萩原
矩之 田口
宏 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27518850&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP3352084(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP2002137362A priority Critical patent/JP3352084B2/en
Publication of JP2002334951A publication Critical patent/JP2002334951A/en
Application granted granted Critical
Publication of JP3352084B2 publication Critical patent/JP3352084B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】（技術分野）本発明は、半導体パッケ−ジ
の製造法及び半導体パッケ−ジに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package and a semiconductor package.

【０００２】（背景技術）半導体の集積度が向上するに
従い、入出力端子数が増加している。従って、多くの入
出力端子数を有する半導体パッケージが必要になった。
一般に、入出力端子はパッケージの周辺に一列配置する
タイプと、周辺だけでなく内部まで多列に配置するタイ
プがある。前者は、QFP(Quad Flat Package)が代表的で
ある。これを多端子化する場合は、端子ピッチを縮小す
ることが必要であるが、0.5mmピッチ以下の領域では、
配線板との接続に高度な技術が必要になる。後者のアレ
イタイプは比較的大きなピッチで端子配列が可能なた
め、多ピン化に適している。2. Description of the Related Art As the degree of integration of semiconductors increases, the number of input / output terminals increases. Therefore, a semiconductor package having a large number of input / output terminals is required.
In general, there are a type in which input / output terminals are arranged in one line around the package, and a type in which input / output terminals are arranged in multiple lines not only in the periphery but also inside. The former is typically a QFP (Quad Flat Package). To increase the number of terminals, it is necessary to reduce the terminal pitch, but in the region of 0.5 mm pitch or less,
Advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch.

【０００３】従来、アレイタイプは接続ピンを有するPG
A (Pin Grid Array)が一般的であるが、配線板との接続
は挿入型となり、表面実装には適していない。このた
め、表面実装可能なBGA (Ball Grid Array)と称するパ
ッケージが開発されている。BGAの分類としては、(1)セ
ラミックタイプ、(2)プリント配線板タイプ及び(3)TAB
（tape automated bonding）を使ったテープタイプなど
がある。このうち、セラミックタイプについては、従来
のPGAに比べるとマザーボードとパッケージ間の距離が
短くなるために、マザーボードとパッケージ間の熱応力
差に起因するパッケージ反りが深刻な問題である。ま
た、プリント配線板タイプについても、基板の反り、耐
湿性、信頼性などに加えて基板厚さが厚いなどの問題が
あり、TAB技術を適用したテープBGAが提案されている。Conventionally, the array type is a PG having connection pins.
A (Pin Grid Array) is generally used, but the connection with the wiring board is of an insertion type and is not suitable for surface mounting. For this reason, a package called a surface mountable BGA (Ball Grid Array) has been developed. BGA classifications include (1) ceramic type, (2) printed wiring board type, and (3) TAB
(Tape automated bonding). Among them, in the ceramic type, since the distance between the motherboard and the package is shorter than that of the conventional PGA, package warpage caused by a difference in thermal stress between the motherboard and the package is a serious problem. Also, the printed wiring board type has problems such as a large substrate thickness in addition to the substrate warpage, moisture resistance, reliability, and the like, and a tape BGA to which TAB technology is applied has been proposed.

【０００４】パッケージサイズの更なる小型化に対応す
るものとして、半導体チップとほぼ同等サイズの、いわ
ゆるチップサイズパッケージ（CSP; Chip Size Packag
e）が提案されている。これは、半導体チップの周辺部
でなく、実装領域内に外部配線基板との接続部を有する
パッケージである。In order to cope with further miniaturization of the package size, a so-called chip size package (CSP) having substantially the same size as a semiconductor chip has been proposed.
e) is proposed. This is a package having a connection portion with an external wiring board in a mounting region, not in a peripheral portion of a semiconductor chip.

【０００５】具体例としては、バンプ付きポリイミドフ
ィルムを半導体チップの表面に接着し、チップと金リー
ド線により電気的接続を図った後、エポキシ樹脂などを
ポッティングして封止したもの（NIKKEI MATERIALS & T
ECHNOLOGY 94. 4, No.140, p18-19）や、仮基板上に半
導体チップ及び外部配線基板との接続部に相当する位置
に金属バンプを形成し、半導体チップをフェースダウン
ボンディング後、仮基板上でトランスファーモールドし
たもの（Smallest Flip-Chip-Like Package CSP; The S
econd VLSI Packaging Workshop of Japan, p46-50, 19
94）などである。[0005] As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, and after electrical connection between the chip and a gold lead wire is achieved, sealing is performed by potting an epoxy resin or the like (NIKKEI MATERIALS & T
ECHNOLOGY 94.4, No.140, p18-19) and forming a metal bump on the temporary substrate at a position corresponding to the connection between the semiconductor chip and the external wiring board. Transfer molded above (Smallest Flip-Chip-Like Package CSP; The S
econd VLSI Packaging Workshop of Japan, p46-50, 19
94).

【０００６】一方、前述のように、BGAやCSP分野でポリ
イミドテープをベースフィルムとして利用したパッケー
ジが検討されている。この場合、ポリイミドテープとし
ては、ポリイミドフィルム上に接着材層を介して銅箔を
ラミネートしたものが一般的であるが、耐熱性や耐湿性
などの観点から銅箔上に直接ポリイミド層を形成した、
いわゆる２層フレキ基材が好ましい。２層フレキ基材の
製造方法としては、銅箔上にポリイミドの前駆体であ
るポリアミック酸を塗布し後熱硬化させる方法、硬化
したポリイミドフィルム上に真空成膜法や無電解めっき
法などにより金属薄膜を形成する方法に大別されるが、
例えば、レーザ加工を適用して所望する部分（第２の接
続機能部に相当）のポリイミドを除去して銅箔に達する
凹部を設ける場合には、ポリイミドフィルムはできる限
り薄いことが好ましい。反面、２層フレキ基材をリード
フレーム状に加工してハンドリングする場合、ベースフ
ィルム厚さが薄いとハンドリング性やフレームとしての
剛直性に欠けるなどの問題がある。On the other hand, as described above, packages using a polyimide tape as a base film are being studied in the field of BGA and CSP. In this case, the polyimide tape is generally a laminate of copper foil on a polyimide film via an adhesive layer, but a polyimide layer is formed directly on the copper foil from the viewpoint of heat resistance and moisture resistance. ,
A so-called two-layer flexible substrate is preferred. The two-layer flexible base material can be produced by applying a polyamic acid, which is a precursor of polyimide, to a copper foil and then heat-curing it. Alternatively, a metal film is formed on a cured polyimide film by a vacuum film forming method or an electroless plating method. It is roughly divided into a method of forming a thin film,
For example, in the case where a polyimide is removed from a desired portion (corresponding to the second connection function portion) by applying laser processing to form a concave portion reaching the copper foil, the polyimide film is preferably as thin as possible. On the other hand, when a two-layer flexible base material is processed into a lead frame shape and handled, if the base film is thin, there are problems such as lack of handleability and rigidity as a frame.

【０００７】以上のように小型化高集積度化に対応でき
る半導体パッケージとして、種々の提案がされている
が、性能、特性、生産性等全てにわたって満足するよう
一層の改善が望まれている。As described above, various proposals have been made for a semiconductor package which can cope with miniaturization and high integration. However, further improvement is desired so as to satisfy all of performance, characteristics, productivity and the like.

【０００８】本発明は、小型化、高集積度化に対応でき
る半導体パッケージを、生産性良くかつ安定的に製造す
るを可能とする半導体パッケージの製造法及び半導体パ
ッケージを提供するものである。An object of the present invention is to provide a method of manufacturing a semiconductor package and a semiconductor package capable of stably manufacturing a semiconductor package compatible with miniaturization and high integration with good productivity.

【０００９】（発明の開示）本願の第一の発明は、 １Ａ．導電性仮支持体の片面に配線を形成する工程、 １Ｂ．配線が形成された導電性仮支持体に半導体素子を
搭載し、半導体素子端子と配線を導通する工程、 １Ｃ．半導体素子を樹脂封止する工程、 １Ｄ．導電性仮支持体を除去し配線を露出する工程、 １Ｅ．露出された配線の外部接続端子が形成される箇所
以外に絶縁層を形成する工程、 １Ｆ．配線の絶縁層が形成されていない箇所に外部接続
端子を形成する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。(Disclosure of the Invention) The first invention of the present application is described in 1A. Forming a wiring on one side of the conductive temporary support, 1B. Mounting the semiconductor element on the conductive temporary support having the wiring formed thereon, and electrically connecting the semiconductor element terminal to the wiring, 1C. Resin sealing the semiconductor element, 1D. Removing the conductive temporary support and exposing the wiring, 1E. Forming an insulating layer in a portion other than where the external connection terminal of the exposed wiring is formed; 1F. A method for manufacturing a semiconductor package, comprising a step of forming an external connection terminal in a portion where an insulating layer of a wiring is not formed.

【００１０】本願の第二の発明は、 ２Ａ．導電性仮支持体の片面に配線を形成する工程、 ２Ｂ．配線が形成された導電性仮支持体の配線が形成さ
れた面に絶縁性支持体を形成する工程、 ２Ｃ．導電性仮支持体を除去し配線を絶縁性支持体に転
写する工程、 ２Ｄ．配線の外部接続端子が形成される箇所の絶縁性支
持体を除去し外部接続端子用透孔を設ける工程、 ２Ｅ．配線が転写された絶縁性支持体に半導体素子を搭
載し、半導体素子端子と配線を導通する工程、 ２Ｇ．半導体素子を樹脂封止する工程、 ２Ｈ．外部接続端子用透孔に配線と導通する外部接続端
子を形成する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。[0010] The second invention of the present application is 2A. Forming wiring on one side of the conductive temporary support, 2B. Forming an insulating support on the surface of the conductive temporary support on which the wiring is formed, on which the wiring is formed, 2C. Removing the conductive temporary support and transferring the wiring to the insulating support, 2D. Removing the insulating support at the location where the external connection terminal of the wiring is to be formed and providing a through hole for the external connection terminal; 2E. Mounting the semiconductor element on the insulating support to which the wiring has been transferred, and electrically connecting the semiconductor element terminal to the wiring, 2G. Step of resin-sealing the semiconductor element, 2H. A method for manufacturing a semiconductor package, comprising a step of forming an external connection terminal that is electrically connected to a wiring in a through hole for an external connection terminal.

【００１１】第二の発明に於いて、２Ａ〜２Ｈの順に進
めるのが好ましいが、２Ｄの工程を２Ｂの前に行うよう
にしても良い。例えば２Ｂの工程を外部接続端子用透孔
を予め設けた絶縁フィルム絶縁性支持体を配線が形成さ
れた導電性仮支持体の配線が形成された面に貼り合わす
ことにより行っても良い。In the second invention, it is preferable to proceed in the order of 2A to 2H, but the 2D process may be performed before 2B. For example, the step 2B may be performed by bonding an insulating film insulating support provided with through holes for external connection terminals in advance to the surface of the conductive temporary support on which the wiring is formed, on which the wiring is formed.

【００１２】本願の第三の発明は、 ３Ａ．導電性仮支持体の片面に配線を形成する工程、 ３Ｂ．配線が形成された導電性仮支持体に半導体素子を
搭載し、半導体素子端子と配線を導通する工程、 ３Ｃ．半導体素子を樹脂封止する工程、 ３Ｄ．配線の外部接続端子が形成される箇所以外の導電
性仮支持体を除去し導電性仮支持体よりなる外部接続端
子を形成する工程、 ３Ｅ．外部接続端子の箇所以外に絶縁層を形成する工
程、を含むことを特徴とする半導体パッケージの製造法
である。The third invention of the present application is 3A. Forming wiring on one side of the conductive temporary support, 3B. Mounting the semiconductor element on the conductive temporary support having the wiring formed thereon, and electrically connecting the semiconductor element terminal to the wiring, 3C. Resin sealing the semiconductor element, 3D. Removing the conductive temporary support other than where the external connection terminal of the wiring is formed to form an external connection terminal made of the conductive temporary support; 3E. Forming an insulating layer other than at the location of the external connection terminal.

【００１３】本願の第四の発明は、 ４Ａ．導電性仮支持体の片面に配線を形成する工程、 ４Ｂ．配線が形成された導電性仮支持体に半導体素子を
搭載し、半導体素子端子と配線を導通する工程、 ４Ｃ．半導体素子を樹脂封止する工程、 ４Ｄ．導電性仮支持体の半導体素子搭載面と反対側の配
線の外部接続端子が形成される箇所に、導電性仮支持体
と除去条件が異なる金属パターンを形成する工程、 ４Ｅ．金属パターンが形成された箇所以外の導電性仮支
持体を除去する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。[0013] The fourth invention of the present application is 4A. Forming wiring on one side of the conductive temporary support, 4B. Mounting the semiconductor element on the conductive temporary support on which the wiring is formed, and electrically connecting the semiconductor element terminal to the wiring; 4C. Step of resin sealing the semiconductor element, 4D. Forming a metal pattern having different removal conditions from the conductive temporary support at locations where the external connection terminals of the wiring on the side opposite to the semiconductor element mounting surface of the conductive temporary support are formed; 4E. A method of manufacturing a semiconductor package, comprising a step of removing a conductive temporary support other than a portion where a metal pattern is formed.

【００１４】金属パターンとしてははんだが好ましく、
又ニッケル続いて金の層を積ねたものでも良い。[0014] Solder is preferable as the metal pattern,
Alternatively, nickel and a gold layer may be stacked.

【００１５】本願の第五の発明は、 ５Ａ．絶縁性支持体の片面に複数組の配線を形成する工
程、 ５Ｂ．配線の外部接続端子となる箇所の絶縁性支持体を
除去し外部接続端子用透孔を設ける工程 ５Ｃ．複数組の配線が形成された絶縁性支持体に半導体
素子を搭載し、半導体素子端子と配線を導通する工程、 ５Ｄ．半導体素子を樹脂封止する工程、 ５Ｅ．外部接続端子用透孔に配線と導通する外部接続端
子を形成する工程、 ５Ｆ．個々の半導体パッケ−ジに分離する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。The fifth invention of the present application is directed to 5A. Forming a plurality of sets of wiring on one surface of the insulating support, 5B. Step of removing the insulating support at a portion to be the external connection terminal of the wiring and providing a through hole for the external connection terminal 5C. Mounting the semiconductor element on an insulating support having a plurality of sets of wirings formed thereon, and electrically connecting the semiconductor element terminals to the wirings; 5D. Step of resin sealing the semiconductor element, 5E. Forming an external connection terminal electrically connected to the wiring in the through hole for the external connection terminal, 5F. A method of manufacturing a semiconductor package, comprising a step of separating the semiconductor package into individual semiconductor packages.

【００１６】第五の発明に於いて、製造工程は、５Ａ〜
５Ｆの順に進めるのが好ましいが、５Ａ、５Ｂを逆にし
ても良い。すなわち外部接続端子用透孔を設けた絶縁性
支持体に、複数組の配線を形成するようにしても良い。[0016] In the fifth invention, the manufacturing process includes 5A to 5A.
It is preferable to proceed in the order of 5F, but 5A and 5B may be reversed. That is, a plurality of sets of wirings may be formed on the insulating support provided with the through holes for external connection terminals.

【００１７】本願の第六の発明は、 ６Ａ．導電性仮支持体の片面に複数組の配線を形成する
工程、 ６Ｂ．導電性仮支持体に形成された複数組の配線を所定
の単位個数になるように導電性仮支持体を切断分離し、
配線が形成された分離導電性仮支持体をフレ−ムに固着
する工程、 ６Ｃ．配線が形成された導電性仮支持体に半導体素子を
搭載し、半導体素子端子と配線を導通する工程、 ６Ｄ．半導体素子を樹脂封止する工程、 ６Ｅ．導電性仮支持体を除去し配線を露出する工程、 ６Ｆ．露出された配線の外部接続端子が形成される箇所
以外に絶縁層を形成する工程、 ６Ｇ．配線の絶縁層が形成されていない箇所に外部接続
端子を形成する工程 ６Ｈ．個々の半導体パッケ−ジに分離する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。The sixth invention of the present application is directed to 6A. Forming a plurality of sets of wirings on one surface of the conductive temporary support, 6B. Cutting and separating the conductive temporary support so that a plurality of sets of wiring formed on the conductive temporary support become a predetermined unit number,
Fixing the separated conductive temporary support on which the wiring is formed to a frame; 6C. Mounting the semiconductor element on the conductive temporary support on which the wiring is formed, and electrically connecting the semiconductor element terminal to the wiring; 6D. Resin sealing the semiconductor element, 6E. Removing the conductive temporary support and exposing the wiring, 6F. Forming an insulating layer other than where the external connection terminals of the exposed wiring are formed; 6G. Step of forming an external connection terminal in a place where an insulating layer of a wiring is not formed 6H. A method of manufacturing a semiconductor package, comprising a step of separating the semiconductor package into individual semiconductor packages.

【００１８】６Ｂの所定の単位個数は１個が好ましい
が、生産性を上げるため複数個であっても良い。The predetermined number of units of 6B is preferably one, but may be plural in order to increase productivity.

【００１９】本願の第七の発明は、 ７Ａ．絶縁性支持体の片面に複数組の配線を形成する工
程、 ７Ｂ．配線の外部接続端子となる箇所の絶縁性支持体を
除去し外部接続端子用透孔を設ける工程 ７Ｃ．絶縁性支持体に形成された複数組の配線を所定の
単位個数になるように絶縁性支持体を切断分離し、配線
が形成された分離絶縁性支持体をフレ−ムに固着する工
程、 ７Ｄ．配線が形成された絶縁性支持体に半導体素子を搭
載し、半導体素子端子と配線を導通する工程、 ７Ｅ．半導体素子を樹脂封止する工程、 ７Ｆ．外部接続端子用透孔に配線と導通する外部接続端
子を形成する工程、 ７Ｇ．個々の半導体パッケ−ジに分離する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。The seventh invention of the present application is directed to 7A. Forming a plurality of sets of wiring on one surface of the insulating support, 7B. Step of removing the insulating support at a portion to be the external connection terminal of the wiring and providing a through hole for the external connection terminal 7C. Cutting and separating the plurality of sets of wiring formed on the insulating support into a predetermined unit number, and fixing the separated insulating support on which the wiring is formed to a frame; 7D . Mounting the semiconductor element on the insulating support having the wiring formed thereon, and electrically connecting the semiconductor element terminal to the wiring, 7E. Step of resin sealing the semiconductor element, 7F. Forming an external connection terminal electrically connected to the wiring in the external connection terminal through hole, 7G. A method of manufacturing a semiconductor package, comprising a step of separating the semiconductor package into individual semiconductor packages.

【００２０】製造工程は、７Ａ〜７Ｇの順に進めるのが
好ましいが、第五の発明と同様７Ａ、７Ｂを逆にしても
良い。The manufacturing process is preferably performed in the order of 7A to 7G, but 7A and 7B may be reversed similarly to the fifth invention.

【００２１】本願の第八の発明は、１層の配線において
その配線の片面が半導体素子と接続する第１の接続機能
を持ち、その配線の反対側が外部の配線と接続する第２
の接続機能をもつように構成された配線を備えた半導体
パッケージの製造法であって、下記８Ａ、８Ｂ、８Ｃ、
８Ｄの工程を含むことを特徴とする半導体パッケージの
製造法。 ８Ａ．耐熱性を有する金属箔付き絶縁基材の金属箔を複
数組の配線パターンに加工する工程。 ８Ｂ．後工程で第２の接続機能部となる位置に、絶縁基
材側から配線パターンに達する凹部を設ける工程。 ８Ｃ．配線パターン面及び配線パターンと隣接する絶縁
基材面上の所望する位置に、所定の部分を開孔させたフ
レーム基材を貼り合わせる工程。 ８Ｄ．半導体素子を搭載し半導体素子端子と配線を導通
し半導体素子を樹脂封止する工程。According to an eighth aspect of the present invention, in a single-layer wiring, one side of the wiring has a first connection function of connecting to a semiconductor element, and the other side of the wiring has a second connection function of connecting to an external wiring.
A method for manufacturing a semiconductor package provided with a wiring configured to have the following connection function, comprising the following 8A, 8B, 8C,
A method for manufacturing a semiconductor package, comprising an 8D step. 8A. A step of processing a metal foil of an insulating base material with a metal foil having heat resistance into a plurality of sets of wiring patterns. 8B. A step of providing a concave portion reaching the wiring pattern from the insulating base material side at a position to be the second connection function portion in a later step. 8C. A step of bonding a frame base material having a predetermined portion to a desired position on a wiring pattern surface and a desired position on an insulating base material surface adjacent to the wiring pattern. 8D. A step of mounting a semiconductor element, electrically connecting a semiconductor element terminal to a wiring, and sealing the semiconductor element with resin.

【００２２】第八の発明に於いて、工程は８Ａ〜８Ｄの
順に進めるのが好ましいが、８Ａと８Ｂを逆にしても良
い。すなわち、絶縁基板に金属箔に達する凹を設けた後
金属箔を配線パターンに加工するようにしても良い。In the eighth aspect, the steps are preferably performed in the order of 8A to 8D, but 8A and 8B may be reversed. That is, the metal foil may be processed into a wiring pattern after the recess reaching the metal foil is provided on the insulating substrate.

【００２３】本願の第九の発明は、１層の配線において
その配線の片面が半導体素子と接続する第１の接続機能
を持ち、その配線の反対側が外部の配線と接続する第２
の接続機能をもつように構成された配線を備えた半導体
パッケージの製造法であって、下記９Ａ、９Ｂ、９Ｃ、
９Ｄの工程を含むことを特徴とする半導体パッケージの
製造法。 ９Ａ．耐熱性を有する金属箔付き絶縁基材の金属箔を複
数組の配線パターンに加工する工程。 ９Ｂ．後工程で第２の接続機能部となる位置に、絶縁基
材側から配線パターンに達する凹部を設ける工程。 ９Ｃ．配線パターン面及び配線パターンと隣接する絶縁
基材面上の所望する位置に、所定の部分を開孔させた第
２絶縁基材を貼り合わせ絶縁支持体を構成する工程。 ９Ｄ．絶縁支持体に形成された複数組の配線を所定の単
位個数になるように絶縁支持体を切断分離し、配線が形
成された分離絶縁支持体をフレームに固着する工程。 ９Ｅ．半導体素子を搭載し半導体素子端子と配線を導通
し半導体素子樹脂封止する工程。According to a ninth aspect of the present invention, in a single-layer wiring, one side of the wiring has a first connection function of connecting to a semiconductor element, and the other side of the wiring has a second connection function of connecting to an external wiring.
A method of manufacturing a semiconductor package provided with a wiring configured to have a connection function of the following 9A, 9B, 9C,
A method of manufacturing a semiconductor package, comprising a step of 9D. 9A. A step of processing a metal foil of an insulating base material with a metal foil having heat resistance into a plurality of sets of wiring patterns. 9B. A step of providing a concave portion reaching the wiring pattern from the insulating base material side at a position to be the second connection function portion in a later step. 9C. A step of bonding a second insulating base material having a predetermined portion formed at a desired position on the wiring pattern surface and an insulating base material surface adjacent to the wiring pattern to form an insulating support. 9D. A step of cutting and separating the plurality of sets of wiring formed on the insulating support so as to have a predetermined unit number, and fixing the separated insulating support on which the wiring is formed to a frame; 9E. A step of mounting the semiconductor element, conducting the semiconductor element terminals and wiring, and sealing the resin with the semiconductor element.

【００２４】第九の発明に於いて、工程は９Ａ〜９Ｅの
順に進めるのが好ましいが、第八の発明と同様９Ａと９
Ｂを逆にしても良い。In the ninth invention, the steps preferably proceed in the order of 9A to 9E.
B may be reversed.

【００２５】本願の第十の発明は、 １０Ａ．支持体の片面に複数組の配線を形成する工程、 １０Ｂ．配線が形成された支持体に複数個の半導体素子
を搭載し、半導体素子端子と配線とを導通させる工程、 １０Ｃ．導通された複数組の半導体素子と配線とを一括
して樹脂封止する工程、 １０Ｄ．支持体の所望する部分を除去して配線の所定部
分を露出させ、露出した配線と電気的に接続した外部接
続端子を形成する工程、 １０Ｅ．個々の半導体パッケ−ジに分離する工程 を含むことを特徴とする半導体パッケージの製造法であ
る。The tenth invention of the present application is a 10A. Forming a plurality of sets of wiring on one side of the support, 10B. A step of mounting a plurality of semiconductor elements on the support on which the wiring is formed, and electrically connecting the semiconductor element terminals to the wiring; 10C. A step of collectively encapsulating the plurality of conductive semiconductor elements and wirings with a resin, 10D. Removing a desired portion of the support to expose a predetermined portion of the wiring, and forming an external connection terminal electrically connected to the exposed wiring, 10E. A method of manufacturing a semiconductor package, comprising a step of separating the semiconductor package into individual semiconductor packages.

【００２６】支持体として金属箔を使用し樹脂封止後に
支持体を除去することにより配線パターンを露出させる
ようにしても良い。The wiring pattern may be exposed by using a metal foil as a support and removing the support after resin sealing.

【００２７】又、支持体が絶縁基材で、樹脂封止後に絶
縁基材の所定部分を除去して配線パターンに達する非貫
通凹部を形成するようにすることもできる。Further, the support may be an insulating base material, and a predetermined portion of the insulating base material may be removed after resin sealing to form a non-penetrating recess reaching the wiring pattern.

【００２８】本願の第十一の発明は、複数個の半導体素
子実装基板部を備え、複数個の半導体素子実装基板部を
連結するための連結部を備え、位置合わせマーク部を備
えている半導体素子実装用フレームの製造法であって、
（ａ）導電性仮基板上に半導体素子実装部の配線を作製
する工程、（ｂ）樹脂基材上に配線を転写する工程、
（ｃ）導電性仮基板をエッチング除去する工程、を含
み、（ｃ）の導電性仮基板の除去に際して、導電性仮基
板に一部を残し連結部の一部を構成するようにすること
を特徴とする半導体素子実装用フレームの製造法であ
る。According to an eleventh aspect of the present invention, there is provided a semiconductor device having a plurality of semiconductor element mounting board sections, a connecting section for connecting the plurality of semiconductor element mounting board sections, and an alignment mark section. A method for manufacturing an element mounting frame,
(A) a step of forming wiring of a semiconductor element mounting portion on a conductive temporary substrate, (b) a step of transferring wiring on a resin base material,
(C) a step of etching and removing the conductive temporary substrate, wherein in removing the conductive temporary substrate in (c), a part of the conductive temporary substrate is left to constitute a part of the connecting portion. This is a method for producing a semiconductor element mounting frame, which is a feature.

【００２９】本発明では、半導体素子はＬＳＩチップ、
ＩＣチップ等通常の素子が使用できる。In the present invention, the semiconductor element is an LSI chip,
Ordinary elements such as IC chips can be used.

【００３０】半導体素子端子と配線とを同通する方法に
は、ワイヤボンディングだけでなく、バンプ、異方導電
性フィルム等通常の手段を用いることができる。As a method of connecting the semiconductor element terminal and the wiring, not only wire bonding but also ordinary means such as a bump and an anisotropic conductive film can be used.

【００３１】本発明においては、半導体素子を樹脂封止
した後、封止樹脂硬化物を加熱処理することにより、そ
り、変形のない半導体パッケージを製造することができ
る。In the present invention, a semiconductor package without warping and deformation can be manufactured by heat-treating the cured sealing resin after sealing the semiconductor element with resin.

【００３２】加熱処理は、封止樹脂硬化物のガラス転移
温度±２０℃の温度が好ましい。この理由は、ガラス転
移温度±２０℃の範囲で樹脂硬化物は最も塑性的な性質
が強く、残留歪みを解消し易いためである。加熱処理の
温度が、ガラス転移温度−２０℃未満では樹脂硬化物は
ガラス状態の弾性体となり緩和の効果が少なくなる傾向
があり、ガラス転移温度＋２０℃を超えれば樹脂硬化物
はゴム弾性体となり同様に歪みを解消する効果がすきな
くなる傾向にある。The heat treatment is preferably performed at a temperature of the glass transition temperature of the cured sealing resin ± 20 ° C. The reason for this is that the cured resin has the strongest plasticity in the range of the glass transition temperature ± 20 ° C., and the residual strain is easily eliminated. If the temperature of the heat treatment is lower than the glass transition temperature of −20 ° C., the cured resin material tends to be an elastic body in a glassy state, and the relaxation effect tends to be reduced. Similarly, there is a tendency for the effect of eliminating distortion to be insignificant.

【００３３】封止樹脂硬化物のガラス転移温度±２０℃
の温度で加熱処理をした後、５℃／分以下の降温速度で
室温まで冷却することにより、半導体パッケ−ジのそ
り、変形をより確実に防止することができる。Glass transition temperature of cured sealing resin ± 20 ° C.
After the heat treatment at the above temperature, the semiconductor package is cooled to room temperature at a temperature lowering rate of 5 ° C./min or less, so that the warpage and deformation of the semiconductor package can be more reliably prevented.

【００３４】加熱処理及び／又は冷却の工程は、封止樹
脂硬化物の上下面を剛性平板で、封止樹脂硬化物のそ
り、変形を押さえる力で押圧した状態で行うのが好まし
い。The heat treatment and / or cooling step is preferably performed in a state where the upper and lower surfaces of the cured sealing resin are pressed with a rigid flat plate with a force for suppressing the warpage and deformation of the cured sealing resin.

【００３５】本発明の半導体パッケージにおいては、配
線は１層の配線においてその配線の片面が半導体チップ
と接続する第１の接続機能を持ち、その配線の反対面が
外部の配線と接続する第２の接続機能をもつように構成
されている。In the semiconductor package of the present invention, the wiring has a first connection function in which one side of the wiring is connected to the semiconductor chip in a single-layer wiring, and the second side in which the opposite side of the wiring is connected to an external wiring. It is configured to have the connection function of

【００３６】外部の配線と接続する外部接続端子は、例
えばはんだバンプ、金バンプ等が好的に使用できる。As an external connection terminal connected to an external wiring, for example, a solder bump, a gold bump, or the like can be preferably used.

【００３７】外部接続端子は、半導体素子端子が配線と
ワイヤボンディング等で導通される位置より内側に設け
るようにするのが高密度化の上で好ましい（ファンイン
タイプ）。このように外部接続端子の位置は、半導体素
子が搭載された下面に格子状に配置するのが高密度化の
上で好ましい。The external connection terminal is preferably provided inside a position where the semiconductor element terminal is electrically connected to the wiring by wire bonding or the like in view of higher density (fan-in type). As described above, it is preferable to arrange the external connection terminals in a lattice on the lower surface on which the semiconductor element is mounted, from the viewpoint of increasing the density.

【００３８】（発明を実施するための最良の形態）図１
により、本発明の第一の実施例について説明する。(Best Mode for Carrying Out the Invention) FIG.
The first embodiment of the present invention will be described below.

【００３９】厚さ０．０３５ｍｍの電解銅箔１の片面に
厚さ０．００１ｍｍのニッケル層（図１では省略）をめ
っきする。次に、感光性ドライフィルムレジスト（日立
化成工業（株）製、商品名：フォテックＨＮ３４０）を
ラミネートし、配線パターンを露光、現像し、めっきレ
ジストを形成する。続いて、硫酸銅浴にて電解銅めっき
を行う。さらに、ニッケルめっきを０．００３ｍｍ、純
度９９．９％以上の金めっきを０．０００３ｍｍ以上の
厚さでめっきする。次に、めっきレジストを剥離し、配
線２を形成する（図１ａ）。このようにして、配線２を
形成した銅箔１にＬＳＩチップ３を搭載する（図１
ｂ）。ＬＳＩチップの接着には、半導体用銀ペースト４
を用いた。次にＬＳＩ端子部と配線２とをワイヤボンド
１００により接続する（図１ｃ）。このようにして形成
したものをトランスファモールド金型に装填し、半導体
封止用エポキシ樹脂（日立化成工業（株）製、商品名：
ＣＬ−７７００）を用いて封止５した（図１ｄ）。その
後、銅箔１のみをアルカリエッチャントで溶解除去し、
ニッケルを露出させた。ニッケル層を銅の溶解性の少な
いニッケル剥離液にて除去して、配線部を露出させた
（図１ｅ）。続いて、ソルダレジスト６を塗布し、接続
用端子部を露出するようにパターンを形成した。この配
線露出部に、はんだボール７を配置し溶融させた（図１
ｆ）。このはんだボール７を介して外部の配線と接続す
る。A nickel layer (not shown in FIG. 1) having a thickness of 0.001 mm is plated on one side of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is applied to a thickness of 0.003 mm and gold plating having a purity of 99.9% or more is applied to a thickness of 0.0003 mm or more. Next, the plating resist is peeled off to form the wiring 2 (FIG. 1A). Thus, the LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is formed (FIG. 1).
b). For bonding the LSI chip, use silver paste 4 for semiconductor.
Was used. Next, the LSI terminal portion and the wiring 2 are connected by a wire bond 100 (FIG. 1C). The thus formed product is loaded into a transfer mold, and an epoxy resin for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name:
CL-7700) (see FIG. 1d). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant,
The nickel was exposed. The nickel layer was removed with a nickel stripper having low copper solubility to expose the wiring portion (FIG. 1e). Subsequently, a solder resist 6 was applied to form a pattern so as to expose the connection terminal portion. The solder balls 7 were arranged and melted on the exposed portions of the wiring (FIG. 1).
f). Via this solder ball 7, it is connected to an external wiring.

【００４０】図２により、本発明の第二の実施例につい
て説明する。Referring to FIG. 2, a second embodiment of the present invention will be described.

【００４１】図１の場合と同様の方法で、配線２を有す
る銅箔１を作成した（図２ａ）。ＬＳＩチップ３を搭載
する。ＬＳＩチップには、端子部に金バンプ８を形成
し、この金バンプ８と配線２の端子部とを加熱加圧して
接続する（図２ｂ）。次に、ＬＳＩチップ下部に液状エ
ポキシ樹脂を充填し硬化９させる（図２ｃ）。このよう
にして形成したものをトランスファモールド金型に装填
し、半導体封止用エポキシ樹脂（日立化成工業（株）
製、商品名：ＣＬ−７７００）を用いて封止１０した
（図２ｄ）。その後、銅箔１のみをアルカリエッチャン
トで溶解除去し、ニッケルを露出させた。ニッケル層を
銅の溶解性の少ないニッケル剥離液にて除去して、配線
部を露出させた（図２ｅ）。続いて、ソルダレジスト６
を塗布し、接続用端子部を露出するようにパターンを形
成した。この配線露出部に、はんだボール７を配置し溶
融させた（図２ｆ）。このはんだボール７を介して外部
の配線と接続する。A copper foil 1 having a wiring 2 was prepared in the same manner as in FIG. 1 (FIG. 2A). The LSI chip 3 is mounted. A gold bump 8 is formed on a terminal portion of the LSI chip, and the gold bump 8 and a terminal portion of the wiring 2 are connected by heating and pressing (FIG. 2B). Next, a liquid epoxy resin is filled in the lower part of the LSI chip and cured 9 (FIG. 2C). The thus formed product is loaded into a transfer mold and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industry Co., Ltd.)
(Trade name: CL-7700) (see FIG. 2d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripper having low copper solubility to expose the wiring portion (FIG. 2E). Then, solder resist 6
Was applied to form a pattern so as to expose the connection terminal portion. The solder balls 7 were arranged and melted on the exposed portions of the wiring (FIG. 2F). Via this solder ball 7, it is connected to an external wiring.

【００４２】図３により、本発明の第三の実施例につい
て説明する。Referring to FIG. 3, a third embodiment of the present invention will be described.

【００４３】厚さ０．０３５ｍｍの電解銅箔１の片面に
厚さ０．００１ｍｍのニッケル層（図３では省略）をめ
っきする。次に、感光性ドライフィルムレジスト（日立
化成工業（株）製、商品名：フォテックＨＮ３４０）を
ラミネートし、配線パターンを露光、現像しめっきレジ
ストを形成する。続いて、硫酸銅浴にて電解銅めっきを
行い、第一の配線１３を形成する。次にめっきレジスト
を剥離し、第一の配線１３の表面を酸化処理、還元処理
を行う。新たな銅箔と接着樹脂としてポリイミド系接着
フィルム（日立化成工業（株）製、商品名：ＡＳ２２１
０）１２を用いて配線１３が内側となるように積層接着
する。（銅箔１１に直径０．１ｍｍの穴を通常のフォト
エッチング法により形成する。パネルめっき法により、
穴内と銅箔表面全体を銅めっきする。）銅箔をフォトエ
ッチング法で第二の配線１１を形成する。ＬＳＩ搭載部
の樹脂（ポリイミド系接着フィルム１２）をエキシマレ
ーザにより除去し端子部を露出させる。該端子部に、ニ
ッケルめっきを０．００３ｍｍ、純度９９．９％以上の
金めっきを０．０００３ｍｍ以上の厚さでめっきする
（図３ａ）。このようにして、２層配線を形成した銅箔
１にＬＳＩチップを搭載する。ＬＳＩチップの接着に
は、半導体用銀ペーストを用いた（図３ｂ）。次にＬＳ
Ｉ端子部と配線１３とをワイヤボンド１００により接続
する（図３ｃ）。このようにして形成したものをトラン
スファモールド金型に装填し、半導体封止用エポキシ樹
脂（日立化成工業（株）製、商品名：ＣＬ−７７００）
を用いて封止５した。その後、銅箔１のみをアルカリエ
ッチャントで溶解除去し、ニッケルを露出させた。ニッ
ケル層を銅の溶解性の少ないニッケル剥離液にて除去し
て、配線部を露出させた（図３ｅ）。続いて、ソルダレ
ジスト６を塗布し、接続用端子部を露出するようにパタ
ーンを形成した。該露出部に、はんだボール７を配置し
溶融させた（図３ｆ）。このはんだボール７を介して外
部の配線と接続する。A nickel layer (not shown in FIG. 3) having a thickness of 0.001 mm is plated on one side of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath to form the first wiring 13. Next, the plating resist is peeled off, and the surface of the first wiring 13 is subjected to an oxidation treatment and a reduction treatment. A new copper foil and a polyimide adhesive film as an adhesive resin (manufactured by Hitachi Chemical Co., Ltd., trade name: AS221)
0) Lamination bonding using 12 so that the wiring 13 is on the inside. (A hole having a diameter of 0.1 mm is formed in the copper foil 11 by a normal photo-etching method.
The inside of the hole and the entire copper foil surface are plated with copper. 2) The second wiring 11 is formed by photoetching a copper foil. The resin (polyimide adhesive film 12) on the LSI mounting portion is removed by an excimer laser to expose the terminal portion. The terminal portion is plated with nickel plating with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more with a thickness of 0.0003 mm or more (FIG. 3A). Thus, the LSI chip is mounted on the copper foil 1 on which the two-layer wiring is formed. For bonding the LSI chip, a silver paste for a semiconductor was used (FIG. 3B). Then LS
The I terminal portion and the wiring 13 are connected by a wire bond 100 (FIG. 3C). The thus formed product is loaded into a transfer mold, and an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.)
Was used to seal 5. Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripper having low copper solubility to expose the wiring portion (FIG. 3E). Subsequently, a solder resist 6 was applied to form a pattern so as to expose the connection terminal portion. The solder balls 7 were arranged on the exposed portions and were melted (FIG. 3F). Via this solder ball 7, it is connected to an external wiring.

【００４４】図４により、本発明の第四の実施例につい
て説明する。Referring to FIG. 4, a fourth embodiment of the present invention will be described.

【００４５】厚さ０．１ｍｍのＳＵＳ（ステンレス鋼）
板１４に、感光性ドライフィルムレジスト（日立化成工
業（株）製、商品名：フォテックＨＮ３４０）をラミネ
ートし、配線パターンを露光、現像し、めっきレジスト
を形成する。続いて、硫酸銅浴にて電解銅めっきを行
う。さらに、ニッケルめっきを０．００３ｍｍ、純度９
９．９％以上の金めっきを０．０００３ｍｍ以上の厚さ
でめっきする。次に、めっきレジストを剥離し、配線２
を形成する（図４ａ）。このようにして配線２を形成し
たＳＵＳ板１４に半導体チップ１０３を搭載する（図４
ｂ）。半導体チップの接着には半導体用銀ベースト４を
用いた。次に半導体端子部と配線２とをワイヤボンド１
００により接続する（図４ｃ）。このようにして形成し
たものをトランスファモールド金型に装填し、半導体封
止用エポキシ樹脂（日立化成工業（株）製、商品名：Ｃ
Ｌ−７７００）を用いて封止５した（図４ｄ）。その
後、ＳＵＳ板１４を機械的に剥離除去し、配線部を露出
させた（図４ｅ）。続いてソルダレジスト６を塗布し、
接続用端子部を露出するようにパターンを形成した。こ
の配線露出部にはんだボール７を配置し溶融させた（図
４ｆ）。このはんだボール７を介して外部の配線と接続
する。SUS (stainless steel) having a thickness of 0.1 mm
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated on the plate 14, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Furthermore, nickel plating is 0.003 mm, purity 9
Gold plating of 9.9% or more is plated with a thickness of 0.0003 mm or more. Next, the plating resist is removed, and the wiring 2 is removed.
Is formed (FIG. 4a). The semiconductor chip 103 is mounted on the SUS plate 14 on which the wiring 2 is formed as described above (FIG. 4).
b). Silver base 4 for semiconductors was used for bonding the semiconductor chips. Next, wire bonding 1 is applied to the semiconductor terminal portion and the wiring 2.
00 (FIG. 4c). The thus formed product is loaded into a transfer mold, and an epoxy resin for semiconductor encapsulation (trade name: C, manufactured by Hitachi Chemical Co., Ltd.)
L-7700) (see FIG. 4D). Thereafter, the SUS plate 14 was mechanically peeled and removed to expose the wiring portion (FIG. 4E). Subsequently, a solder resist 6 is applied,
The pattern was formed so as to expose the connection terminal. The solder balls 7 were arranged on the exposed portions of the wiring and were melted (FIG. 4F). Via this solder ball 7, it is connected to an external wiring.

【００４６】図５により、本発明の第五の実施例につい
て説明する。Referring to FIG. 5, a fifth embodiment of the present invention will be described.

【００４７】厚さ０．０３５ｍｍの電解銅箔１に、感光
性ドライフィルムレジスト（日立化成工業（株）製、商
品名：フォテックＨＮ３４０）をラミネートし、配線パ
ターンを露光、現像し、めっきレジストを形成する。続
いてニッケルのパターンめっき１５を行った後、硫酸銅
浴にて電解銅めっきを行う。さらに、ニッケルめっきを
０．００３ｍｍ、純度９９．９％以上の金めっきを０．
０００３ｍｍ以上の厚さでめっきする。次に、めっきレ
ジストを剥離し、配線２を形成する（図５ａ）。このよ
うにして配線２を形成した銅箔１に半導体チップ１０３
を搭載する（図５ｂ）。半導体チップの接着には、半導
体用銀ベースト４を用いた。次に半導体端子部と配線２
とをワイヤボンド１００により接続する（図５ｃ）。こ
のようにして形成したものをトランスファモールド金型
に装填し、半導体封止用エポキシ樹脂（日立化成工業
（株）製、商品名：ＣＬ−７７００）を用いて封止５し
た（図５ｄ）。その後、銅箔１をアルカリエッチャンで
溶解除去し、ニッケルの配線部を露出させた（図５
ｅ）。続いてソルダレジスト６を塗布し、接続用端子部
を露出するようにパターンを形成した。この配線露出部
にはんだボール７を配置し溶融させた（図５ｆ）。この
はんだボール７を介して外部の配線と接続する。A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated on the 0.035 mm-thick electrolytic copper foil 1, the wiring pattern is exposed and developed, and the plating resist is removed. Form. Subsequently, after nickel pattern plating 15 is performed, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is 0.003 mm, and gold plating having a purity of 99.9% or more is 0.1 mm.
Plating with a thickness of 0003 mm or more. Next, the plating resist is peeled off to form the wiring 2 (FIG. 5A). The semiconductor chip 103 is attached to the copper foil 1 on which the wiring 2 is formed in this manner.
Is mounted (FIG. 5b). For bonding of the semiconductor chip, a silver base for semiconductor 4 was used. Next, the semiconductor terminal portion and the wiring 2
Are connected by a wire bond 100 (FIG. 5c). The thus formed product was loaded in a transfer mold, and sealed 5 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 5D). Thereafter, the copper foil 1 was dissolved and removed with an alkaline etcher to expose the nickel wiring portion (FIG. 5).
e). Subsequently, a solder resist 6 was applied to form a pattern so as to expose the connection terminal portion. The solder ball 7 was arranged on the exposed portion of the wiring and was melted (FIG. 5F). Via this solder ball 7, it is connected to an external wiring.

【００４８】図６により、本発明の第六の実施例につい
て説明する。Referring to FIG. 6, a sixth embodiment of the present invention will be described.

【００４９】厚さ０．０３５ｍｍの電解銅箔１に、感光
性ドライフィルムレジスト（日立化成工業（株）製、商
品名：フォテックＨＮ３４０）をラミネートし、配線パ
ターンを露光、現像し、めっきレジストを形成する。続
いて純度９９．９％以上の金めっきを０．０００３ｍ
ｍ、ニッケルめっきを０．００３ｍｍ以上の厚さでめっ
きする。さらに、硫酸銅浴にて電解銅めっきを行い、め
っきレジストを剥離し、配線２を形成する（図６ａ）。
このようにして配線２を形成した銅箔１の配線面にポリ
イミドフィルム１６を接着し、レーザを用いて配線２の
接続用端子部を露出させ（図６ｂ）、銅箔１をエッチン
グで除去する（図６ｃ）。また、ポリイミドの代わり
に、感光性フィルムを用いることで、レーザを使用しな
いで接続用端子部を露出させることができる。続いて、
ポリイミドフィルム１６の配線パターン面にＬＳＩチッ
プ３を搭載する。ＬＳＩチップの接着には半導体用銀ペ
ースト４を用いた。次に半導体端子部と配線２とをワイ
ヤボンド１００により接続する（図６ｄ）。このように
して形成したものをトランスファモールド金型に装填
し、半導体封止用エポキシ樹脂（日立化成工業（株）
製、商品名：ＣＬ−７７００）を用いて封止５する（図
６ｅ）。その後、接続用端子部にはんだボール７を配置
し溶融させる（図６ｆ）。このはんだボール７を介して
外部の配線と接続する。A photosensitive dry film resist (Fotech HN340, trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on a 0.035 mm-thick electrolytic copper foil 1, the wiring pattern is exposed and developed, and the plating resist is removed. Form. Subsequently, gold plating with a purity of 99.9% or more is applied to 0.0003 m.
m, nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, the plating resist is stripped, and wiring 2 is formed (FIG. 6A).
The polyimide film 16 is adhered to the wiring surface of the copper foil 1 on which the wiring 2 is formed as described above, the connection terminal portion of the wiring 2 is exposed using a laser (FIG. 6B), and the copper foil 1 is removed by etching. (FIG. 6c). In addition, by using a photosensitive film instead of polyimide, the connection terminal portion can be exposed without using a laser. continue,
The LSI chip 3 is mounted on the wiring pattern surface of the polyimide film 16. A silver paste for semiconductors 4 was used for bonding the LSI chips. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 6D). The thus formed product is loaded into a transfer mold and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industry Co., Ltd.)
(Trade name: CL-7700) (see FIG. 6E). After that, the solder balls 7 are arranged on the connection terminals and melted (FIG. 6f). Via this solder ball 7, it is connected to an external wiring.

【００５０】図７により、本発明の第七の実施例につい
て説明する。Referring to FIG. 7, a seventh embodiment of the present invention will be described.

【００５１】厚さ０．０３５ｍｍの電解銅箔１の片面に
厚さ０．００１ｍｍのニッケル層（図７では省略）をめ
っきする。次に、感光性ドライフィルムレジスト（日立
化成工業（株）製、商品名：フォテックＨＮ３４０）を
ラミネートし、配線パターンを露光、現像し、めっきレ
ジストを形成する。続いて硫酸銅浴にて電解銅めっきを
行う。さらに、ニッケルめっきを０．００３ｍｍ、純度
９９．９％以上の金めっきを０．０００３ｍｍ以上の厚
さでめっきする。次にめっきレジストを剥離し、配線２
を形成する（図７ａ）。このようにして配線２を形成し
た銅箔１にＬＳＩチップ３を搭載する。ＬＳＩチップの
接着には半導体用銀ペースト４を用いた。次に、半導体
端子部と配線２とをワイヤボンド１００により接続する
（図７ｂ）。このようにして形成したものをトランスフ
ァモールド金型に装填し半導体封止用エポキシ樹脂（日
立化成工業（株）製、商品名：ＣＬ−７７００）を用い
て封止５する（図７ｃ）。その後、銅箔１のみをアルカ
リエッチャントで溶解除去し、ニッケルを露出させる。
ニッケル層を銅の溶解性の少ないニッケル剥離液にて除
去して配線部を露出させる（図７ｄ）。続いて、接続用
端子部を開口させたポリイミドフィルム１６を接着し
（図７ｅ）、この配線露出部にはんだボール７を配置し
溶融させる（図７ｆ）。このはんだボール７を介して外
部の配線と接続する。A nickel layer (not shown in FIG. 7) having a thickness of 0.001 mm is plated on one side of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is applied to a thickness of 0.003 mm and gold plating having a purity of 99.9% or more is applied to a thickness of 0.0003 mm or more. Next, the plating resist is removed, and the wiring 2 is removed.
(FIG. 7a). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is formed as described above. A silver paste for semiconductors 4 was used for bonding the LSI chips. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 7B). The thus formed product is loaded into a transfer mold and sealed 5 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 7C). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant to expose nickel.
The nickel layer is removed with a nickel stripper having low copper solubility to expose the wiring portion (FIG. 7D). Subsequently, the polyimide film 16 having the connection terminal portions opened is bonded (FIG. 7E), and the solder balls 7 are arranged and melted on the exposed portions of the wiring (FIG. 7F). Via this solder ball 7, it is connected to an external wiring.

【００５２】図８により、本発明の第八の実施例につい
て説明する。An eighth embodiment of the present invention will be described with reference to FIG.

【００５３】厚さ０．０３５ｍｍの電解銅箔１に、感光
性ドライフィルムレジスト（日立化成工業（株）製、商
品名：フォテックＨＮ３４０）をラミネートし、配線パ
ターンを露光、現像し、めっきレジストを形成する。続
いて純度９９．９％以上の金めっきを０．０００３ｍ
ｍ、ニッケルめっきを０．００３ｍｍ以上の厚さでめっ
きする。さらに、硫酸銅浴にて電解銅めっきを行い、め
っきレジストを剥離し配線２を形成する（図８ａ）。こ
のようにして配線２を形成した銅箔１の配線面に液状封
止樹脂１７をスクリーン印刷により塗布し、配線２の接
続用端子部を露出させるようにして絶縁層を形成する
（図８ｂ）。液状封止樹脂を硬化させた後、銅箔１をエ
ッチングで除去する（図８ｃ）。続いて、硬化させた液
状封止樹脂３の配線パターン面にＬＳＩチップ３を搭載
する。ＬＳＩチップの接着には半導体用銀ペースト４を
用いた。次に半導体端子部と配線２とをワイヤボンド１
００により接続する（図８ｄ）。このようにして形成し
たものをトランスファモールド金型に装填し、半導体封
止用エポキシ樹脂（日立化成工業（株）製、商品名：Ｃ
Ｌ−７７００）を用いて封止５する（図８ｅ）。その
後、配線２の接続用端子部にはんだボール７を配置し溶
融させる（図８ｆ）。このはんだボール７を介して外部
の配線と接続する。A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated on the 0.035 mm-thick electrolytic copper foil 1, the wiring pattern is exposed and developed, and the plating resist is removed. Form. Subsequently, gold plating with a purity of 99.9% or more is applied to 0.0003 m.
m, nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, and the plating resist is peeled off to form wiring 2 (FIG. 8A). The liquid sealing resin 17 is applied by screen printing to the wiring surface of the copper foil 1 on which the wiring 2 is formed as described above, and an insulating layer is formed so as to expose the connection terminal portion of the wiring 2 (FIG. 8B). . After curing the liquid sealing resin, the copper foil 1 is removed by etching (FIG. 8C). Subsequently, the LSI chip 3 is mounted on the wiring pattern surface of the cured liquid sealing resin 3. A silver paste for semiconductors 4 was used for bonding the LSI chips. Next, wire bonding 1 is applied to the semiconductor terminal portion and the wiring 2.
00 (FIG. 8d). The thus formed product is loaded into a transfer mold, and an epoxy resin for semiconductor encapsulation (trade name: C, manufactured by Hitachi Chemical Co., Ltd.)
L-7700) to seal 5 (FIG. 8E). Thereafter, the solder balls 7 are arranged at the connection terminal portions of the wiring 2 and are melted (FIG. 8F). Via this solder ball 7, it is connected to an external wiring.

【００５４】図９により、本発明の第九の実施例につい
て説明する。A ninth embodiment of the present invention will be described with reference to FIG.

【００５５】厚さ０．０３５ｍｍの電解銅箔１の片面に
厚さ０．００１ｍｍのニッケル層（図９では省略）をめ
っきする。次に、感光性ドライフィルムレジスト（日立
化成工業（株）製、商品名：フォテックＨＮ３４０）を
ラミネートし、配線パターンを露光、現像し、めっきレ
ジストを形成する。続いて硫酸銅浴にて電解銅めっきを
行う。さらに、ニッケルめっきを０．００３ｍｍ、純度
９９．９％以上の金めっきを０．０００３ｍｍ以上の厚
さでめっきする。次にめっきレジストを剥離し、配線２
を形成する（図９ａ）。このようにして配線２を形成し
た銅箔１にＬＳＩチップ３を搭載する。ＬＳＩチップ３
の接着には半導体用銀ペースト４を用いた。次に、半導
体端子部と配線２とをワイヤボンド１００により接続す
る（図９ｂ）。このようにして形成したものをトランス
ファモールド金型に装填し半導体封止用エポキシ樹脂
（日立化成工業（株）製、商品名：ＣＬ−７７００）を
用いて封止５する（図９ｃ）。その後、銅箔１のみをア
ルカリエッチャントで溶解除去し、ニッケルを露出させ
る。ニッケル層を銅の溶解性の少ないニッケル剥離液に
て除去して配線部を露出させる（図９ｄ）。続いて、液
状封止樹脂１７をスクリーン印刷により塗布し、配線２
の接続用端子部を露出させるようにして、液状封止樹脂
１７の絶縁層を形成する（図９ｅ）。この配線２の接続
用端子部にはんだボール７を配置し溶融させる（図９
ｆ）。このはんだボール７を介して外部の配線と接続す
る。A nickel layer (not shown in FIG. 9) having a thickness of 0.001 mm is plated on one side of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is applied to a thickness of 0.003 mm and gold plating having a purity of 99.9% or more is applied to a thickness of 0.0003 mm or more. Next, the plating resist is removed, and the wiring 2 is removed.
Is formed (FIG. 9a). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is formed as described above. LSI chip 3
Silver paste 4 for semiconductors was used for bonding. Next, the semiconductor terminal portion and the wiring 2 are connected by a wire bond 100 (FIG. 9B). The thus formed product is loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 9C). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant to expose nickel. The nickel layer is removed with a nickel stripper having low copper solubility to expose the wiring portion (FIG. 9D). Subsequently, the liquid sealing resin 17 is applied by screen printing, and the wiring 2 is formed.
Then, an insulating layer of the liquid sealing resin 17 is formed so as to expose the connection terminal section (FIG. 9E). The solder balls 7 are arranged on the connection terminals of the wiring 2 and are melted (FIG. 9).
f). Via this solder ball 7, it is connected to an external wiring.

【００５６】図１０により、本発明の第十の実施例につ
いて説明する。Referring to FIG. 10, a tenth embodiment of the present invention will be described.

【００５７】厚さ０．０３５ｍｍの電解銅箔１の片面に
厚さ０．００１ｍｍのニッケル層（図１０では省略）を
めっきする。次に、感光性ドライフィルムレジスト（日
立化成工業（株）製、商品名：フォテックＨＮ３４０）
をラミネートし、配線パターン及び位置合わせマークの
めっきレジストを露光、現像により形成する。続いて、
硫酸銅浴にて電解銅めっきを行う。さらに、ニッケルめ
っきを０．００３ｍｍ、純度９９．９％以上の金めっき
を０．０００３ｍｍ以上の厚さでめっきする。次に、め
っきレジストを剥離し、配線２及び位置合わせマーク１
８を形成した後（図１０ａ）、位置合わせマーク１８の
部分だけをＳＵＳ板で挟みプレスすることで銅箔１の裏
面に位置合わせマークを浮かび上がらせる（図１０
ｂ）。このようにして配線２及び位置合わせマーク１８
を形成した銅箔１にＬＳＩチップ３を搭載する（図１０
ｃ）。ＬＳＩチップ３の接着には半導体用銀ペースト４
を用いた。次に、半導体端子部と配線２とをワイヤボン
ド１００により接続する（図１０ｄ）。このようにして
形成したものをトランスファモールド金型に装填し、半
導体封止用エポキシ樹脂（日立化成工業（株）製、商品
名：ＣＬ−７７００）を用いて封止５した（図１０
ｅ）。銅箔裏側に再び感光性ドライフィルムをラミネー
トし、位置合わせマーク１８を利用してエッチングパタ
ーン形成する。その後、銅箔１及びニッケル層をエッチ
ングして、銅箔１によるバンプ７の形成及び配線部の露
出を行う（図１０ｆ）。続いて、ソルダレジスト８を塗
布し、バンプ７が露出するように絶縁層を形成した（図
１０ｇ）。このバンプ７を介して外部の配線と接続す
る。A nickel layer (not shown in FIG. 10) having a thickness of 0.001 mm is plated on one side of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340)
Are laminated, and the plating resist of the wiring pattern and the alignment mark is formed by exposure and development. continue,
Perform electrolytic copper plating in a copper sulfate bath. Further, nickel plating is applied to a thickness of 0.003 mm and gold plating having a purity of 99.9% or more is applied to a thickness of 0.0003 mm or more. Next, the plating resist is removed, and the wiring 2 and the alignment mark 1 are removed.
8 (FIG. 10a), only the position of the alignment mark 18 is sandwiched between SUS plates and pressed, so that the alignment mark emerges on the back surface of the copper foil 1 (FIG. 10).
b). Thus, the wiring 2 and the alignment mark 18
The LSI chip 3 is mounted on the copper foil 1 on which is formed (FIG. 10)
c). For bonding the LSI chip 3, a silver paste 4 for semiconductor is used.
Was used. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 10D). The thus formed product was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 10).
e). A photosensitive dry film is again laminated on the back side of the copper foil, and an etching pattern is formed using the alignment mark 18. Thereafter, the copper foil 1 and the nickel layer are etched to form the bumps 7 and to expose the wiring portions by the copper foil 1 (FIG. 10F). Subsequently, a solder resist 8 was applied to form an insulating layer such that the bumps 7 were exposed (FIG. 10G). The external wiring is connected through the bumps 7.

【００５８】図１１により、本発明の第十一の実施例に
ついて説明する。An eleventh embodiment of the present invention will be described with reference to FIG.

【００５９】厚さ０．０３５ｍｍの電解銅箔１に、感光
性ドライフィルムレジスト（日立化成工業（株）製、商
品名：フォテックＨＮ３４０）をラミネートし、複数組
の配線パターンを露光、現像し、めっきレジストを形成
する。続いて、純度９９．９％以上の金めっきを０．０
００３ｍｍ、ニッケルめっきを０．００３ｍｍ以上の厚
さでめっきする。さらに、硫酸銅浴にて電解銅めっきを
行い、レジストを剥離し、複数組の配線２を形成する
（図１１ａ）。このようにして、複数組の配線２を形成
した銅箔１の配線面にポリイミドフィルム１９を接着
し、レーザを用いて配線２の接続端子部を露出させ（図
１１ｂ）、銅箔１をエッチングで除去する（図１１
ｃ）。以上のように、１枚のポリイミドフィルム上に複
数組の配線２を形成した後、ＬＳＩチップ３を搭載す
る。ＬＳＩチップの接着には、半導体用ダイボンディン
グテープ４’を用いた。次に半導体端子部と配線２とを
ワイヤボンド１００により接続する（図１１ｄ）。この
ようにして形成したものをトランスファモールド金型に
装填し、半導体封止用エポキシ樹脂（日立化成工業
（株）製、商品名：ＣＬ−７７００）を用いて各々封止
５する（図１１ｅ）。その後、配線２の接続端子部には
んだボール７を配置し溶融させる（図１１ｆ）。このは
んだボール７を介して外部の配線と接続する。最後にポ
リイミドフィルムで連結されたパッケージを、金型で打
ち抜く（図１１ｇ）。A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated on a 0.035 mm-thick electrolytic copper foil 1, and a plurality of sets of wiring patterns are exposed and developed. Form a plating resist. Subsequently, gold plating with a purity of 99.9% or more is applied to 0.0
003 mm, nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, the resist is stripped, and a plurality of sets of wirings 2 are formed (FIG. 11A). In this way, the polyimide film 19 is adhered to the wiring surface of the copper foil 1 on which the plural sets of wirings 2 are formed, the connection terminal portions of the wirings 2 are exposed using a laser (FIG. 11B), and the copper foil 1 is etched. (See FIG. 11)
c). As described above, after forming a plurality of sets of wirings 2 on one polyimide film, the LSI chip 3 is mounted. For bonding the LSI chip, a die bonding tape for semiconductor 4 'was used. Next, the semiconductor terminal portion and the wiring 2 are connected by a wire bond 100 (FIG. 11D). The thus formed product is loaded into a transfer mold and sealed using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 11e). . Thereafter, the solder balls 7 are arranged on the connection terminal portions of the wiring 2 and are melted (FIG. 11F). Via this solder ball 7, it is connected to an external wiring. Finally, the package connected by the polyimide film is punched out with a mold (FIG. 11g).

【００６０】図１２により、本発明の第十二の実施例に
ついて説明する。A twelfth embodiment of the present invention will be described with reference to FIG.

【００６１】厚さ０．０７ｍｍの接着剤付きポリイミド
フィルム２０を、金型で打ち抜き接続端子部となる部分
を開口させる（図１２ａ）。次に、厚さ０．０３５ｍｍ
の銅箔２１を接着後（図１２ｂ）、感光性ドライフィル
ムレジスト（日立化成工業（株）製、商品名：フォテッ
クＨＮ３４０）をラミネートし、複数組の配線パターン
を露光、現像し、エッチングレジストを形成する。続い
て銅箔をエッチングし、レジストを剥離し、複数組の配
線２を形成する（図１２ｃ）。以上のように、１枚のポ
リイミドフィルム上に複数組の配線パターンを形成した
後、ＬＳＩチップ３を搭載する。ＬＳＩチップ３の接着
には、半導体用ダイボンディングテープ４’を用いた。
次に半導体端子部と配線２とをワイヤボンド１００によ
り接続する（図１２ｄ）。このようにして形成したもの
をトランスファモールド金型に装填し、半導体封止用エ
ポキシ樹脂（日立化成工業（株）製、商品名：ＣＬ−７
７００）を用いて各々封止５する（図１２ｅ）。その
後、配線の接続端子部にはんだボール７を配置し溶融さ
せる（図１２ｆ）。このはんだボール７を介して外部の
配線と接続する。最後にポリイミドフィルムで連結され
たパッケージを、金型で打ち抜く（図１２ｇ）。A polyimide film 20 with an adhesive having a thickness of 0.07 mm is punched out with a die to open a portion to be a connection terminal portion (FIG. 12A). Next, thickness 0.035mm
After bonding the copper foil 21 (FIG. 12b), a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, a plurality of sets of wiring patterns are exposed and developed, and the etching resist is removed. Form. Subsequently, the copper foil is etched, the resist is stripped, and a plurality of sets of wirings 2 are formed (FIG. 12C). As described above, after forming a plurality of sets of wiring patterns on one polyimide film, the LSI chip 3 is mounted. For bonding the LSI chip 3, a semiconductor die bonding tape 4 'was used.
Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 12D). The thus formed product is loaded into a transfer mold, and an epoxy resin for semiconductor encapsulation (trade name: CL-7, manufactured by Hitachi Chemical Co., Ltd.)
700) (see FIG. 12E). Thereafter, the solder balls 7 are arranged at the connection terminal portions of the wiring and are melted (FIG. 12F). Via this solder ball 7, it is connected to an external wiring. Finally, the package connected by the polyimide film is punched out with a mold (FIG. 12g).

【００６２】図１３〜１５により、本発明の第十三の実
施例について説明する。A thirteenth embodiment of the present invention will be described with reference to FIGS.

【００６３】厚さ０．０３５ｍｍの電解銅箔１の片面に
厚さ０．００１ｍｍのニッケル層（図１３では省略）を
めっきする。感光性ドライフィルムレジスト（日立化成
工業（株）製、商品名：フォテックＨＮ３４０）をラミ
ネートし、複数組の配線パターンのめっきレジストを露
光、現像により形成する。続いて、硫酸銅浴にて電解銅
めっきを行う。さらに、ニッケルめっきを０．００３ｍ
ｍ、純度９９．９％以上の金めっきを０．０００３ｍｍ
以上の厚さでめっきし、めっきレジストを剥離し、配線
２を形成した（図１３ａ）。次に、配線２を形成した銅
箔１を単位個数に分けた後、ポリイミド接着フィルムを
介して別に用意したステンレス製フレーム２２（厚さ；
０．１３５ｍｍ）にはりつけた（図１３ｂ）。フレーム
としては、りん青銅等の銅合金、銅箔、ニッケル箔、ニ
ッケル合金箔等が使用できる。接着の方法としては他に
金属間の共晶を利用した接合、超音波を利用した接合等
を用いることも可能である。また、図１４に示したよう
に銅箔１上の配線をあらかじめ検査し、配線良品２３だ
けを撰択し、フレーム２２にはりつけると良い。図１４
において、１は電解銅箔、２２はフレ−ム、２４は配線
不良品、２５は位置合わせ用穴である。また、この実施
例では、切り分けた銅箔上には配線１個となるようにし
たが、切り分けた銅箔上に複数組の配線があるようにし
ても良い。フレーム２２と配線付き銅箔との張り合わせ
の位置関係として、例えば図１５（ａ）、（ｂ）に示し
たものなど種々可能である。図１５はフレ−ム２２の平
面図であり、２６はフレ−ム開口部、２７は配線付き銅
箔の搭載位置、２８は箔固定用接着剤である。次に、Ｌ
ＳＩチップ３を搭載し、半導体端子部と配線２とをワイ
ヤボンド１００により接続する（図１３ｃ）。ＬＳＩチ
ップの搭載には半導体用ダイボンディングテープ４’を
用いた。ここで、ボンディングテープ４’の代わりにダ
イボンド用銀ペースト等を用いてもよい。また、半導体
チップの実装には、通常のワイヤーボンディング接続を
用いたが、フィリップチップ等、他の方法を用いてもよ
い。このようにして形成したものをトランスファモール
ド金型に装填し、半導体封止用エポキシ樹脂（日立化成
工業（株）製、商品名：ＣＬ−７７００）を用いて封止
５した（図１３ｄ）。その後、銅箔１のみをアルカリエ
ッチャントで溶解除去し、ニッケルを露出させた。ニッ
ケル層を銅の溶解性の少ないニッケル剥離液にて除去し
て、配線部を露出させた。続いて、ソルダレジスト６を
塗布し、接続用端子部を露出するようにパターンを形成
した。この配線露出部に、はんだボール７を配置し溶融
させた（図１３ｅ）。この後で、切断機を用いて切断
し、フレーム２２の不要な切片１０１を除いて、個々の
半導体パッケージに分割した（図１３ｆ）。このはんだ
ボール７を介して外部の配線と接続する。この例では、
板取りを上げて効率よく半導体パッケ−ジを製造するこ
とができる。A nickel layer (not shown in FIG. 13) having a thickness of 0.001 mm is plated on one side of the electrolytic copper foil 1 having a thickness of 0.035 mm. A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, and a plurality of sets of wiring pattern plating resists are formed by exposure and development. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Furthermore, nickel plating is 0.003m
m, gold plating of purity 99.9% or more is 0.0003 mm
Plating was performed at the above thickness, the plating resist was peeled off, and wiring 2 was formed (FIG. 13A). Next, after dividing the copper foil 1 on which the wiring 2 is formed into a unit number, a stainless steel frame 22 (thickness;
0.135 mm) (FIG. 13b). As the frame, a copper alloy such as phosphor bronze, a copper foil, a nickel foil, a nickel alloy foil, or the like can be used. As a bonding method, it is also possible to use bonding using eutectic between metals, bonding using ultrasonic waves, or the like. Further, as shown in FIG. 14, it is preferable to inspect the wiring on the copper foil 1 in advance, select only good wiring 23, and attach it to the frame 22. FIG.
In the figure, 1 is an electrolytic copper foil, 22 is a frame, 24 is a defective wiring, and 25 is a positioning hole. In this embodiment, one wiring is provided on the cut copper foil, but a plurality of sets of wiring may be provided on the cut copper foil. Various positional relationships such as those shown in FIGS. 15A and 15B are possible as the bonding positional relationship between the frame 22 and the copper foil with wiring. FIG. 15 is a plan view of the frame 22, 26 is a frame opening, 27 is a mounting position of a copper foil with wiring, and 28 is a foil fixing adhesive. Next, L
The SI chip 3 is mounted, and the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 13C). A semiconductor die bonding tape 4 'was used for mounting the LSI chip. Here, a silver paste for die bonding or the like may be used instead of the bonding tape 4 '. In addition, a normal wire bonding connection is used for mounting the semiconductor chip, but another method such as a Philip chip may be used. The thus formed product was charged into a transfer mold, and sealed 5 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 13D). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripper having low copper solubility to expose the wiring portion. Subsequently, a solder resist 6 was applied to form a pattern so as to expose the connection terminal portion. The solder balls 7 were arranged and melted on the exposed portions of the wiring (FIG. 13E). After that, it was cut using a cutting machine, and the semiconductor chip was divided into individual semiconductor packages except for unnecessary sections 101 of the frame 22 (FIG. 13F). Via this solder ball 7, it is connected to an external wiring. In this example,
The semiconductor package can be manufactured efficiently by removing the board.

【００６４】図１６により、本発明の第十四の実施例に
ついて説明する。A fourteenth embodiment of the present invention will be described with reference to FIG.

【００６５】厚さ０．０７ｍｍの接着剤付きポリイミド
フィルム２９を、金型で打ち抜き接続端子部となる部分
を開口させる。次に、厚さ０．０３５ｍｍの銅箔を接着
後、感光性ドライフィルムレジスト（日立化成工業
（株）製、商品名：フォテックＨＮ３４０）をラミネー
トし、複数組の配線パターンを露光、現像し、エッチン
グレジストを形成た。続いて銅箔をエッチングし、レジ
ストを剥離し、複数組の配線２を形成する（図１６
ａ）。ここで、銅箔上にポリイミドを直接コ−ティング
した材料（例えば、日立化成工業（株）製、商品名５０
００１）を用いて、接続端子部および配線２を形成する
ようにしても良い。開口部の形成もドリル加工、エキシ
マレ−ザ等のレ−ザ加工、印刷等の方法を用いたり、ポ
リイミドに感光性を持たせた材料を使用し、露光・現像
により形成しても良い。ポリイミドの代わりに封止樹脂
等他の材料を使用しても良い。A polyimide film 29 with an adhesive having a thickness of 0.07 mm is punched out with a mold to open a portion to be a connection terminal portion. Next, after bonding a copper foil having a thickness of 0.035 mm, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated, and a plurality of sets of wiring patterns are exposed and developed. An etching resist was formed. Subsequently, the copper foil is etched, the resist is stripped, and a plurality of sets of wirings 2 are formed (FIG. 16).
a). Here, a material obtained by directly coating a polyimide on a copper foil (for example, trade name 50 manufactured by Hitachi Chemical Co., Ltd.)
001), the connection terminal portion and the wiring 2 may be formed. The opening may be formed by a method such as drilling, laser processing such as an excimer laser, or printing, or by using a material obtained by imparting photosensitivity to polyimide, and by exposing and developing. Other materials such as sealing resin may be used instead of polyimide.

【００６６】以上のように、１枚のポリイミドフィルム
上に複数組の配線パターンを形成した後、配線付きフィ
ルムを単位個数に分けた、ポリイミド接着接着剤２８を
介して別に用意したステンレス製フレーム２２（厚さ；
０．１３５ｍｍ）にはりつけた（図１６ｂ）。次に、Ｌ
ＳＩチップ３を搭載し、半導体端子部と配線２とをワイ
ヤボンド１００により接続する（図１６ｃ）。ＬＳＩチ
ップの搭載には半導体用ダイボンディングテープ４´を
用いた。このようにして形成したものをトランスファモ
ールド金型に装填し、半導体封止用エポキシ樹脂（日立
化成工業（株）製、商品名：ＣＬ−７７００）を用いて
封止５した（図１６ｄ）。続いて最初に設けた接続端子
部となるべき開口部にはんだボール７を配置し溶融させ
る（図１６ｅ）。このはんだボール７を介して外部の配
線と接続する。最後にフレームで連結されたパッケージ
を金型で打ち抜き、個々のパッケージに分割した（図１
６ｆ）。As described above, after a plurality of sets of wiring patterns are formed on one polyimide film, the film with wiring is divided into unit numbers, and the stainless steel frame 22 separately prepared via the polyimide adhesive 28 is used. (thickness;
0.135 mm) (FIG. 16b). Next, L
The SI chip 3 is mounted, and the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 16C). A semiconductor die bonding tape 4 'was used for mounting the LSI chip. The thus formed product was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 16D). Subsequently, the solder balls 7 are arranged and melted in the openings to be the connection terminals, which are provided first (FIG. 16E). Via this solder ball 7, it is connected to an external wiring. Finally, the packages connected by the frame were punched out with a mold and divided into individual packages (FIG. 1).
6f).

【００６７】図１７により本発明の第十五の実施例につ
いて説明する。The fifteenth embodiment of the present invention will be described with reference to FIG.

【００６８】金属箔３１上に絶縁基材３２を直接形成し
た２層フレキシブル基材（図１７ａ）の金属箔上に所定
のレジスト像を形成し、公知のエッチング法により所望
する複数組の配線パターン３３を形成し、レジスト像を
剥離する（図１７ｂ）。金属箔としては、電解銅箔や圧
延銅箔あるいは銅合金箔などの単一箔の他、後工程で除
去可能なキャリヤ箔上に銅薄層を有する複合金属箔など
も適用可能である。具体的には、厚さ18μｍの電解銅箔
の片面に厚さ0.2μｍ程度のニッケル-リンめっき層を形
成後、続けて厚さ5μｍ程度の銅薄層をめっきしたもの
などが適用できる。この場合、銅薄層上にポリイミド層
を形成した後、銅箔及びニッケル-リン層をエッチング
除去することにより、銅薄層が露出する。すなわち、本
願の発明においては銅薄層全てを露出させた後銅薄層を
配線加工しても良いし、キャリヤ箔（銅箔/ニッケル薄
層）をリードフレーム構造体の一部として利用しても良
い。一方、絶縁基材としては、プロセス耐熱性などの観
点からポリイミド材が一般的である。この場合、ポリイ
ミドと銅箔の熱膨張係数が異なるとはんだリフロー工程
において基材の反りが顕著になるため、ポリイミドとし
ては（化１）の繰り返し単位を有するポリイミドを70モ
ル％以上含んだポリイミドを適用することが好ましい。A predetermined resist image is formed on a metal foil of a two-layer flexible base material (FIG. 17A) in which an insulating base material 32 is directly formed on a metal foil 31, and a desired plurality of wiring patterns are formed by a known etching method. 33 are formed and the resist image is peeled off (FIG. 17b). As the metal foil, not only a single foil such as an electrolytic copper foil, a rolled copper foil, or a copper alloy foil, but also a composite metal foil having a thin copper layer on a carrier foil that can be removed in a later step can be applied. Specifically, a nickel-phosphorus plating layer having a thickness of about 0.2 μm is formed on one surface of an electrolytic copper foil having a thickness of 18 μm, and then a copper thin layer having a thickness of about 5 μm is plated. In this case, after the polyimide layer is formed on the copper thin layer, the copper foil and the nickel-phosphorus layer are etched away to expose the copper thin layer. That is, in the present invention, the copper thin layer may be subjected to wiring processing after exposing the entire copper thin layer, or the carrier foil (copper foil / nickel thin layer) may be used as a part of the lead frame structure. Is also good. On the other hand, as the insulating base material, a polyimide material is generally used from the viewpoint of process heat resistance and the like. In this case, if the polyimide and the copper foil have different coefficients of thermal expansion, the warpage of the base material becomes remarkable in the solder reflow step. Therefore, as the polyimide, a polyimide containing at least 70 mol% of a polyimide having a repeating unit of the formula (1) is used. It is preferred to apply.

【００６９】[0069]

【化１】 次に、後工程で外部基板との接続部となる位置に銅箔に
達する凹部３４を設ける（図１７ｃ）。凹部の加工方法
は特に限定するものではなく、エキシマレーザや炭酸ガ
スレーザ及びYAGレーザなどレーザ加工の他、ウエット
エッチング法などが適用可能である。Embedded image Next, a concave portion 34 reaching the copper foil is provided at a position to be a connection portion with an external substrate in a later step (FIG. 17C). The method of processing the concave portion is not particularly limited, and a wet etching method or the like can be applied in addition to laser processing such as an excimer laser, a carbon dioxide laser, and a YAG laser.

【００７０】次に、所定の部分（開孔部３５）をパンチ
ング加工等で打ち抜いた接着材３６付きフレーム基材３
７を配線パターン面に接着させる（図１７ｄ）。この場
合、フレーム基材は特に限定するものではなく、ポリイ
ミドフィルムや銅箔などの金属箔の適用が可能である。
ここで、仮に２層フレキシブル基材のポリイミド層厚さ
が25μｍで、かつ、接着するフレーム基材がポリイミド
フィルムの場合、フレーム全体としての剛直性を確保す
るためにはフィルム厚さとして50〜70μｍ程度が必要に
なる。なお、フレーム基材層を形成する領域についても
特に限定するものではなく、半導体チップを搭載する部
分にフレーム基材層を設けることも可能である。具体的
には、チップ実装がワイヤボンディング方式の場合に
は、最小限ワイヤボンド用端子部３８が露出していれば
他の領域全てにフレーム基材層を設けても良い。次に、
半導体チップ３９を搭載し、金ワイヤ４０で半導体チッ
プと配線パターン間を電気的に接続させる（図１７
ｅ）。一方、半導体チップ実装方式としてフェースダウ
ン方式を採用する場合には、配線パターンの所定位置
（半導体チップの外部接続用電極位置に対応）に金属パ
ンプ等を設け、金属バンプを介して半導体チップと波線
パターンとを電気的に接続させても良い。次に、トラン
スファーモールド用の金型にセットし、樹脂封止材４１
で封止する（図１７ｆ）。この場合、樹脂封止材は特に
限定するものではなく、例えば、直径10〜20μｍ程度の
シリカを5〜80wt%の範囲で含有したエポキシ系樹脂など
が適用できる。次に、外部基板との接続部４２を形成す
る。接続部４２の形成方法としては、図１７ｃの工程後
にあらかじめ電解めっき法によりポリイミドフィルム厚
さ以上のバンプを形成しておく方法や樹脂封止後にはん
だ印刷法によりはんだバンプを形成する方法などが適用
可能である。最後に、フレームからパッケージ部を切断
して所望するパッケージが得られる（図１７ｇ）。Next, the frame base material 3 with the adhesive 36 is punched out of a predetermined portion (opening portion 35) by punching or the like.
7 is adhered to the wiring pattern surface (FIG. 17d). In this case, the frame base material is not particularly limited, and a metal foil such as a polyimide film or a copper foil can be used.
Here, if the polyimide layer thickness of the two-layer flexible substrate is 25 μm, and the frame substrate to be bonded is a polyimide film, the film thickness is 50 to 70 μm in order to secure the rigidity of the entire frame. Need a degree. The region where the frame base material layer is formed is not particularly limited, and the frame base material layer can be provided in a portion where the semiconductor chip is mounted. Specifically, when the chip mounting is a wire bonding method, the frame base material layer may be provided in all other regions as long as the terminal portions for wire bonding 38 are at least exposed. next,
The semiconductor chip 39 is mounted, and the semiconductor chip and the wiring pattern are electrically connected by the gold wire 40 (FIG. 17).
e). On the other hand, when the face-down method is adopted as the semiconductor chip mounting method, a metal pump or the like is provided at a predetermined position of the wiring pattern (corresponding to the position of the external connection electrode of the semiconductor chip), and the semiconductor chip and the wavy line are connected via the metal bumps. The pattern may be electrically connected. Next, the resin sealing material 41 is set in a transfer mold.
(FIG. 17f). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. Next, the connection part 42 with the external substrate is formed. As a method for forming the connection portion 42, a method in which a bump having a thickness equal to or larger than the thickness of the polyimide film is formed in advance by an electrolytic plating method after the step of FIG. 17C or a method in which a solder bump is formed by a solder printing method after resin sealing is applied. It is possible. Finally, the package is cut from the frame to obtain the desired package (FIG. 17g).

【００７１】図１７の第十五の実施例を更に具体的に説
明する。The fifteenth embodiment of FIG. 17 will be described more specifically.

【００７２】具体例１ 厚さ12μｍの電解銅箔を片面に有する２層フレキシブル
基材（日立化成工業（株）製、商品名：MCF 5000I）の
銅箔面上にドライフィルムレジスト（日立化成工業
（株）製、商品名：フォテックHK815）をラミネート
し、露光、現像により所望するレジストパターンを得
た。次に、塩化第二鉄溶液で銅箔をエッチング加工後、
レジストパターンを水酸化カリウム溶液で剥離すること
により所定の配線パターンを得た。次に、エキシマレー
ザ加工機（住友重機械工業（株）製、装置名：INDEX20
0）を用いて絶縁基材側から配線パターン裏面に達する
凹部（直径300μｍ）を所定の位置に所定の数だけ形成
した。エキシマレーザ加工条件は、エネルギー密度250m
J/cm２、縮小率3.0、発振周波数200Hz、照射パルス数30
0パルスである。次に50μｍ厚さのポリイミドフィルム
（宇部興産製、商品名：UPILEXS）の片面に厚さ10μｍ
のポリイミド系接着材（日立化成工業（株）製、商品
名：AS 2250）を有する接着シートを作製し、後工程で
のワイヤボンド端子部に相当する領域を含む所定領域を
パンチ加工により除去し、接着材を介してポリイミドフ
ィルムと配線パターン付き２層フレキ基材とを加熱圧着
させた。圧着条件は、圧力20kgf/cm2、温度180℃、加熱
加圧時間60分である。次に、無電解ニッケル、金めっき
法によりワイヤボンド用端子部にニッケル/金めっきを
施した。めっき厚さは、それぞれ、3μｍ、0.3μｍであ
る。次に、半導体チップ搭載用ダイボンド材（日立化成
工業（株）製、商品名：HM-1）を用いて半導体チップを
搭載した。搭載条件は、プレス圧力5kgf/cm２、接着温
度380℃及び圧着時間5秒である。次に、ワイヤボンディ
ングにより半導体チップの外部電極部と配線パターンを
電気的に接続した。その後、リードフレーム状に金型加
工し、トランスファーモールド用金型にセットし、半導
体封止用エポキシ樹脂（日立化成工業（株）製、CL-770
0）を用いて185℃、90秒で封止した。続いて、前述の凹
部に所定量のはんだを印刷塗布し、赤外線リフロー炉に
よりはんだを溶融させて外部接続用バンプを形成した。
最後に、パッケージ部を金型で打ち抜き、所望するパッ
ケージを得た。Concrete Example 1 A dry film resist (Hitachi Chemical Industries, Ltd.) was formed on a copper foil surface of a two-layer flexible base material (manufactured by Hitachi Chemical Co., Ltd., trade name: MCF 5000I) having a 12 μm thick electrolytic copper foil on one surface. (Trade name: Photek HK815, manufactured by Co., Ltd.), and a desired resist pattern was obtained by exposure and development. Next, after etching the copper foil with ferric chloride solution,
A predetermined wiring pattern was obtained by stripping the resist pattern with a potassium hydroxide solution. Next, an excimer laser machine (Sumitomo Heavy Industries, Ltd., device name: INDEX20)
Using (0), a predetermined number of concave portions (diameter: 300 μm) reaching the wiring pattern back surface from the insulating base material side were formed at predetermined positions. Excimer laser processing conditions are energy density 250m
J / cm2, reduction ratio 3.0, oscillation frequency 200Hz, irradiation pulse number 30
0 pulses. Next, on one side of a 50 μm thick polyimide film (product name: UPILEXS, manufactured by Ube Industries), a 10 μm thick
An adhesive sheet having a polyimide adhesive (Hitachi Kasei Kogyo Co., Ltd., trade name: AS 2250) is prepared, and a predetermined region including a region corresponding to a wire bond terminal portion in a later process is removed by punching. Then, the polyimide film and the two-layer flexible base material with the wiring pattern were heated and pressed via an adhesive. The pressure bonding conditions are a pressure of 20 kgf / cm2, a temperature of 180 ° C., and a heating and pressing time of 60 minutes. Next, nickel / gold plating was applied to the terminal portion for wire bonding by electroless nickel and gold plating. The plating thicknesses are 3 μm and 0.3 μm, respectively. Next, a semiconductor chip was mounted using a die bond material for mounting a semiconductor chip (trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.). The mounting conditions are a press pressure of 5 kgf / cm 2, an adhesion temperature of 380 ° C., and a pressure bonding time of 5 seconds. Next, the external electrode portion of the semiconductor chip and the wiring pattern were electrically connected by wire bonding. After that, it is molded into a lead frame and set in a mold for transfer molding. Epoxy resin for semiconductor encapsulation (CL-770, manufactured by Hitachi Chemical Co., Ltd.)
Using 0), sealing was performed at 185 ° C. for 90 seconds. Subsequently, a predetermined amount of solder was printed and applied to the above-mentioned concave portions, and the solder was melted by an infrared reflow furnace to form external connection bumps.
Finally, the package was punched out with a mold to obtain a desired package.

【００７３】図１８により本発明の第十六の実施例につ
いて説明する。A sixteenth embodiment of the present invention will be described with reference to FIG.

【００７４】金属箔３１上に絶縁基材３２を直接形成し
た２層フレキシブル基材（図１８ａ）の金属箔上に所定
のレジスト像を形成し、公知のエッチング法により所望
する複数組の配線パターン３を形成し、レジスト像を剥
離する（図１８ｂ）。金属箔としては、電解銅箔や圧延
銅箔あるいは銅合金箔などの単一箔の他、後工程で除去
可能なキャリヤ箔上に銅薄層を有する複合金属箔なども
適用可能である。具体的には、厚さ18μｍの電解銅箔の
片面に厚さ0.2μｍ程度のニッケル-リンめっき層を形成
後、続けて厚さ5μｍ程度の銅薄層をめっきしたものな
どが適用できる。この場合、銅薄層上にポリイミド層を
形成した後、銅箔及びニッケル-リン層をエッチング除
去することにより、銅薄層が露出する。すなわち、本願
の発明においては銅薄層全てを露出させた後銅薄層を配
線加工しても良いし、キャリヤ箔（銅箔/ニッケル薄
層）をリードフレーム構造体の一部として利用しても良
い。一方、絶縁基材としては、プロセス耐熱性などの観
点からポリイミド材が一般的である。この場合、ポリイ
ミドと銅箔の熱膨張係数が異なるとはんだリフロー工程
において基材の反りが顕著になるため、ポリイミドとし
ては（化１）の繰り返し単位を有するポリイミドを70モ
ル％以上含んだポリイミドを適用することが好ましい。A predetermined resist image is formed on a metal foil of a two-layer flexible base material (FIG. 18a) in which an insulating base material 32 is directly formed on a metal foil 31, and a desired plurality of wiring patterns are formed by a known etching method. Then, the resist image is peeled off (FIG. 18b). As the metal foil, not only a single foil such as an electrolytic copper foil, a rolled copper foil, or a copper alloy foil, but also a composite metal foil having a thin copper layer on a carrier foil that can be removed in a later step can be applied. Specifically, a nickel-phosphorus plating layer having a thickness of about 0.2 μm is formed on one surface of an electrolytic copper foil having a thickness of 18 μm, and then a copper thin layer having a thickness of about 5 μm is plated. In this case, after the polyimide layer is formed on the copper thin layer, the copper foil and the nickel-phosphorus layer are etched away to expose the copper thin layer. That is, in the present invention, the copper thin layer may be subjected to wiring processing after exposing the entire copper thin layer, or the carrier foil (copper foil / nickel thin layer) may be used as a part of the lead frame structure. Is also good. On the other hand, as the insulating base material, a polyimide material is generally used from the viewpoint of process heat resistance and the like. In this case, if the polyimide and the copper foil have different coefficients of thermal expansion, the warpage of the base material becomes remarkable in the solder reflow step. Therefore, as the polyimide, a polyimide containing at least 70 mol% of a polyimide having a repeating unit of the formula (1) is used. It is preferred to apply.

【００７５】次に、後工程で外部基板との接続部となる
位置に銅箔に達する凹部３４を設ける（図１８ｃ）。凹
部の加工方法は特に限定するものではなく、エキシマレ
ーザや炭酸ガスレーザ及びYAGレーザなどレーザ加工の
他、ウエットエッチング法などが適用可能である。Next, a concave portion 34 reaching the copper foil is provided at a position to be a connection portion with the external substrate in a later step (FIG. 18c). The method of processing the concave portion is not particularly limited, and a wet etching method or the like can be applied in addition to laser processing such as an excimer laser, a carbon dioxide laser, and a YAG laser.

【００７６】次に、第２絶縁基体として所定の部分（開
孔部５）をパンチング加工等で打ち抜いた接着材３６付
きフレーム基材３７を配線パターン面に接着させる（図
１８ｄ）。ここで、仮に２層フレキシブル基材のポリイ
ミド層厚さが25μｍであれば、後工程でフレームに固着
することを考慮すれば接着するポリイミドフィルムの厚
さとして50〜70μｍ程度が必要になる。なお、ポリイミ
ドを接着する領域についても特に限定するものではな
く、半導体チップを搭載する部分に設けることにより、
ＣＳＰのように半導体チップ下部に外部接続端子を形成
することも可能である。具体的には、チップ実装がワイ
ヤボンディング方式の場合には、最小限ワイヤボンド用
端子部３８が露出していれば他の領域全てにポリイミド
フィルムを接着しても良い。このようにして得られた絶
縁基板を、個々の配線パターンに分離し（図１８ｅ）別
に用意した例えばＳＵＳなどのフレーム４３に固着する
（図１８ｆ）。次に、半導体チップ３９を搭載し、金ワ
イヤ４０で半導体チップと配線パターン間を電気的に接
続させる（図１８ｇ）。一方、半導体チップ実装方式と
してフェースダウン方式を採用する場合には、配線パタ
ーンの所定位置（半導体チップの外部接続用電極位置に
対応）に金属パンプ等を設け、金属バンプを介して半導
体チップと波線パターンとを電気的に接続させても良
い。次に、トランスファーモールド用の金型にセット
し、樹脂封止材４１で封止する（図１８ｈ）。この場
合、樹脂封止材は特に限定するものではなく、例えば、
直径10〜20μｍ程度のシリカを5〜80wt%の範囲で含有し
たエポキシ系樹脂などが適用できる。次に、外部基板と
の接続部１２を形成する。接続部１２の形成方法として
は、図１８ｃの工程後にあらかじめ電解めっき法により
ポリイミドフィルム厚さ以上のバンプを形成しておく方
法や樹脂封止後にはんだ印刷法によりはんだバンプを形
成する方法などが適用可能である。最後に、フレームか
らパッケージ部を切断して所望するパッケージが得られ
る（図１８ｉ）。Next, a frame base material 37 with an adhesive material 36 obtained by punching a predetermined portion (opening portion 5) of the second insulating base material by punching or the like is bonded to the wiring pattern surface (FIG. 18D). Here, if the thickness of the polyimide layer of the two-layer flexible base material is 25 μm, the thickness of the polyimide film to be bonded needs to be about 50 to 70 μm in consideration of the fact that it is fixed to the frame in a later step. In addition, the region to which the polyimide is bonded is not particularly limited, and is provided in a portion where the semiconductor chip is mounted.
It is also possible to form external connection terminals below the semiconductor chip like a CSP. Specifically, when the chip mounting is a wire bonding method, a polyimide film may be bonded to all other regions as long as the wire bonding terminal portion 38 is at least exposed. The insulating substrate thus obtained is separated into individual wiring patterns (FIG. 18e) and fixed to a separately prepared frame 43 of, for example, SUS (FIG. 18f). Next, the semiconductor chip 39 is mounted, and the semiconductor chip and the wiring pattern are electrically connected by the gold wire 40 (FIG. 18g). On the other hand, when the face-down method is adopted as the semiconductor chip mounting method, a metal pump or the like is provided at a predetermined position of the wiring pattern (corresponding to the position of the external connection electrode of the semiconductor chip), and the semiconductor chip and the wavy line are connected via the metal bumps. The pattern may be electrically connected. Next, it is set in a transfer mold and sealed with a resin sealing material 41 (FIG. 18h). In this case, the resin sealing material is not particularly limited, for example,
An epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be used. Next, the connection part 12 with the external substrate is formed. As a method for forming the connection portion 12, a method in which a bump having a thickness equal to or larger than the thickness of the polyimide film is formed in advance by the electrolytic plating method after the step of FIG. 18C, or a method in which a solder bump is formed by a solder printing method after resin sealing is applied. It is possible. Finally, the desired package is obtained by cutting the package from the frame (FIG. 18i).

【００７７】図１８の第十六の実施例を更に具体的に説
明する。The sixteenth embodiment of FIG. 18 will be described more specifically.

【００７８】具体例２ 厚さ12μｍの電解銅箔を片面に有する２層フレキシブル
基材（日立化成工業（株）製、商品名：MCF 5000I）の
銅箔面上にドライフィルムレジスト（日立化成工業
（株）製、商品名：フォテックHK815）をラミネート
し、露光、現像により所望するレジストパターンを得
た。次に、塩化第二鉄溶液で銅箔をエッチング加工後、
レジストパターンを水酸化カリウム溶液で剥離すること
により所定の配線パターンを得た。次に、エキシマレー
ザ加工機（住友重機械工業（株）製、装置名：INDEX20
0）を用いて絶縁基材側から配線パターン裏面に達する
凹部（直径300μｍ）を所定の位置に所定の数だけ形成
した。エキシマレーザ加工条件は、エネルギー密度250m
J/cm２、縮小率3.0、発振周波数200Hz、照射パルス数30
0パルスである。次に50μｍ厚さのポリイミドフィルム
（宇部興産製、商品名：UPILEXS）の片面に厚さ10μｍ
のポリイミド系接着材（日立化成工業（株）製、商品
名：AS 2250）を有する接着シートを作製し、後工程で
のワイヤボンド端子部に相当する領域を含む所定領域を
パンチ加工により除去し、接着材を介してポリイミドフ
ィルムと配線パターン付き２層フレキ基材とを加熱圧着
させた。圧着条件は、圧力20kgf/cm２、温度180℃、加
熱加圧時間60分である。次に、無電解ニッケル、金めっ
き法によりワイヤボンド用端子部にニッケル/金めっき
を施した。めっき厚さは、それぞれ、3μｍ、0.3μｍで
ある。このようにして得られた基板を、個々の配線パタ
ーンに分離し、別に用意したＳＵＳフレ−ムに固着し
た。次に、半導体チップ搭載用ダイボンド材（日立化成
工業（株）製、商品名：HM-1）を用いて半導体チップを
搭載した。搭載条件は、プレス圧力5kgf/cm2、接着温度
380℃及び圧着時間5秒である。次に、ワイヤボンディン
グにより半導体チップの外部電極部と配線パターンを電
気的に接続した。その後、リードフレーム状に金型加工
し、トランスファーモールド用金型にセットし、半導体
封止用エポキシ樹脂（日立化成工業（株）製、CL-770
0）を用いて185℃、90秒で封止した。続いて、前述の凹
部に所定量のはんだを印刷塗布し、赤外線リフロー炉に
よりはんだを溶融させて外部接続用バンプを形成した。
最後に、パッケージ部を金型で打ち抜き、所望するパッ
ケージを得た。Specific Example 2 A dry film resist (Hitachi Chemical Industries, Ltd.) was formed on a copper foil surface of a two-layer flexible base material (manufactured by Hitachi Chemical Co., Ltd., trade name: MCF 5000I) having a 12 μm thick electrolytic copper foil on one surface. (Trade name: Photek HK815, manufactured by Co., Ltd.), and a desired resist pattern was obtained by exposure and development. Next, after etching the copper foil with ferric chloride solution,
A predetermined wiring pattern was obtained by stripping the resist pattern with a potassium hydroxide solution. Next, an excimer laser machine (Sumitomo Heavy Industries, Ltd., device name: INDEX20)
Using (0), a predetermined number of concave portions (diameter: 300 μm) reaching the wiring pattern back surface from the insulating base material side were formed at predetermined positions. Excimer laser processing conditions are energy density 250m
J / cm2, reduction ratio 3.0, oscillation frequency 200Hz, irradiation pulse number 30
0 pulses. Next, on one side of a 50 μm thick polyimide film (product name: UPILEXS, manufactured by Ube Industries), a 10 μm thick
An adhesive sheet having a polyimide adhesive (Hitachi Kasei Kogyo Co., Ltd., trade name: AS 2250) is prepared, and a predetermined region including a region corresponding to a wire bond terminal portion in a later process is removed by punching. Then, the polyimide film and the two-layer flexible base material with the wiring pattern were heated and pressed via an adhesive. The pressure bonding conditions are a pressure of 20 kgf / cm 2, a temperature of 180 ° C., and a heating and pressing time of 60 minutes. Next, nickel / gold plating was applied to the terminal portion for wire bonding by electroless nickel and gold plating. The plating thicknesses are 3 μm and 0.3 μm, respectively. The substrate thus obtained was separated into individual wiring patterns, and fixed to a separately prepared SUS frame. Next, a semiconductor chip was mounted using a die bond material for mounting a semiconductor chip (trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.). Mounting conditions are press pressure 5kgf / cm2, bonding temperature
380 ° C and crimping time 5 seconds. Next, the external electrode portion of the semiconductor chip and the wiring pattern were electrically connected by wire bonding. After that, it is molded into a lead frame and set in a mold for transfer molding. Epoxy resin for semiconductor encapsulation (CL-770, manufactured by Hitachi Chemical Co., Ltd.)
Using 0), sealing was performed at 185 ° C. for 90 seconds. Subsequently, a predetermined amount of solder was printed and applied to the above-mentioned concave portions, and the solder was melted by an infrared reflow furnace to form external connection bumps.
Finally, the package was punched out with a mold to obtain a desired package.

【００７９】図１９、２０、２１により本発明の第十七
の実施例について説明する。A seventeenth embodiment of the present invention will be described with reference to FIGS.

【００８０】支持体５１上に複数組の所定の配線パター
ン５２を形成する（図１９ａ）。支持体としては、電解
銅箔などの金属箔の他にポリイミドフィルムなどの絶縁
基材を適用できる。絶縁基材を適用する場合には２通り
の方法がある。第１の方法は、絶縁基材の所定部分に配
線パターンに達する非貫通凹部を形成し、配線パターン
の露出部に外部接続端子を形成する方法である。非貫通
凹部はエキシマレーザや炭酸ガスレーザなどを適用して
形成できる。第２の方法は、接着材付き絶縁基材にドリ
ル加工したものを予め形成しておき、電解銅箔などと積
層させた後、銅箔をエッチング加工する方法である。A plurality of predetermined wiring patterns 52 are formed on the support 51 (FIG. 19A). As a support, an insulating substrate such as a polyimide film can be applied in addition to a metal foil such as an electrolytic copper foil. When an insulating base material is used, there are two methods. The first method is a method in which a non-penetrating recess reaching a wiring pattern is formed in a predetermined portion of an insulating base material, and an external connection terminal is formed in an exposed portion of the wiring pattern. The non-penetrating recess can be formed by using an excimer laser, a carbon dioxide gas laser, or the like. The second method is a method in which a drilled material is formed in advance on an insulating base material with an adhesive, laminated with an electrolytic copper foil or the like, and then the copper foil is etched.

【００８１】一方、金属箔を適用する場合には、まずフ
ォトレジストなどによりレジストパターンを形成後、金
属箔をカソードとして電気めっき法で配線パターンを形
成する。この場合、通常の電解銅箔や電解銅箔上に銅箔
と化学エッチング条件の異なる金属（ニッケル、金、は
んだ等）の薄層を設けたものなどが適用できる。また、
配線パターンとしては銅が好ましいが、前述のように電
解銅箔を支持体として適用する場合には、銅箔とエッチ
ング条件の異なる金属自体を配線パターンとして適用し
たり、あるいは、銅箔エッチング時のバリヤ層となるパ
ターン薄層をパターン銅めっき前に形成したりする必要
がある。On the other hand, when a metal foil is used, a resist pattern is first formed with a photoresist or the like, and then a wiring pattern is formed by electroplating using the metal foil as a cathode. In this case, a normal electrolytic copper foil or a copper foil having a thin layer of a metal (nickel, gold, solder, etc.) having different chemical etching conditions from the copper foil can be applied. Also,
Copper is preferable as the wiring pattern, but when the electrolytic copper foil is used as the support as described above, the metal itself having different etching conditions from the copper foil may be used as the wiring pattern, or may be used when etching the copper foil. It is necessary to form a thin pattern layer serving as a barrier layer before pattern copper plating.

【００８２】次に、ダイボンド材５３で半導体素子５４
を搭載後、半導体素子端子と配線パターンとを電気的に
接続し（図１９ｂ）、トランスファーモールド法により
複数組の半導体素子と配線パターンとを一括して樹脂封
止材５６で封止する（図１９ｃ）。樹脂封止材は特に限
定するものではなく、例えば、直径10〜20μｍ程度のシ
リカを5〜80wt%の範囲で含有したエポキシ樹脂のが適用
できる。なお、本発明は半導体素子の実装方式がフェー
スアップ方式の場合に限定されるものではなく、例え
ば、フェースダウン方式の場合にも適用可能である。具
体的には、配線パターン５２上の所定位置にフェースダ
ウンボンド用のバンプをめっき法などにより形成した
後、半導体素子の外部接続部とバンプとを電気的に接続
させれば良い。Next, the semiconductor element 54 is formed with the die bonding material 53.
After mounting, the semiconductor element terminals and the wiring patterns are electrically connected (FIG. 19B), and a plurality of sets of the semiconductor elements and the wiring patterns are collectively sealed with a resin sealing material 56 by transfer molding (FIG. 19B). 19c). The resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. Note that the present invention is not limited to the case where the mounting method of the semiconductor element is a face-up method, and is applicable to, for example, a case where the mounting method is a face-down method. Specifically, after a bump for face-down bonding is formed at a predetermined position on the wiring pattern 52 by a plating method or the like, the external connection portion of the semiconductor element and the bump may be electrically connected.

【００８３】更に、図２０や図２１に示したように後工
程でパッケージを分割しやすいようにしておくことは有
効である。このうち、図２０は複数個ある各パッケージ
部分の境界部分に溝５９を形成するものである。溝の幅
や深さ等は、トランスファーモールド用金型の加工寸法
により制御可能である。また、図２１は、あらかじめ各
パッケージ部に対応した部分をくり抜いた格子状中間板
６０を使用してトランスファーモールドを行なうもので
ある。次に、支持体が金属箔の場合、化学エッチング法
などにより支持体を除去し、所定の位置に外部接続用端
子５７を形成する（図１９ｄ）。支持体として絶縁基材
を適用する場合には、前述したようにレーザ等により所
定部分の絶縁基材のみを選択的に除去すれば良い。最後
に、一括封止した基板を単位部分５８に切断分離する。
なお、配線パターン露出面に配線パターンを保護する目
的でソルダーレジスト層を形成しても良い。Further, as shown in FIGS. 20 and 21, it is effective to easily divide the package in a later step. Among them, FIG. 20 shows a case where a groove 59 is formed at a boundary portion between a plurality of package portions. The width and depth of the groove can be controlled by the processing dimensions of the transfer mold. FIG. 21 shows a case where transfer molding is performed using a grid-like intermediate plate 60 in which a portion corresponding to each package portion has been cut out in advance. Next, when the support is a metal foil, the support is removed by a chemical etching method or the like, and external connection terminals 57 are formed at predetermined positions (FIG. 19D). When an insulating base material is used as the support, only a predetermined portion of the insulating base material may be selectively removed by a laser or the like as described above. Finally, the collectively sealed substrate is cut and separated into unit portions 58.
Note that a solder resist layer may be formed on the exposed surface of the wiring pattern for the purpose of protecting the wiring pattern.

【００８４】第十七の実施例を具体的に説明する。The seventeenth embodiment will be specifically described.

【００８５】具体例３ 厚さ35μｍ、外形250ｍｍ角の電解銅箔のシャイニー面
に、感光性ドライフィルムレジスト（日立化成工業
（株）製、商品名：フォテックHN640）をラミネート
し、露光、現像により所望するレジストパターン（最少
ライン/スペース=50μm /50μm ）を形成した。次に、
電気めっき法により、厚さ0.2μｍのニッケル、30μｍ
の銅、5μｍのニッケル及び1μｍのソフト金で構成され
る同一の配線パターンを300個（4ブロック/250mm角、75
個/ブロック）形成した。次に、液温35℃、濃度3wt%の
水酸化カリウム溶液を用いてレジストパターンを剥離
し、85℃で15分間乾燥後、各ブロックに切断後、半導体
素子実装用ダイボンド材（日立化成工業（株）製、商品
名：HM-1）を用いて半導体素子を接着した。接着条件
は、プレス圧力5kg/cm２、温度380℃及び圧着時間5秒で
ある。次に、半導体素子の外部端子と金めっき端子部
（第２の接続部）をワイヤボンドにより電気的に接続し
た後、トランスファーモールド金型にセットし、半導体
封止用エポキシ樹脂（日立化成工業（株）製、商品名：
CL-7700）を用いて185℃、90秒で75個（１ブロックに相
当）の配線パターンを一括封止することにより、各配線
パターンを封止材中に転写した。次に、アルカリエッチ
ャント（メルテックス（株）製、商品名： Aプロセス）
を用いて電解銅箔の所望する部分をエッチング除去し
た。エッチング液の温度は40℃、スプレー圧力は1.2kgf
/ cm２である。次に、印刷法により外部接続端子部には
んだパターンを形成し、赤外線リフロー炉によりはんだ
を溶融させて外部接続用バンプを形成した。最後に、ダ
イヤモンドカッターにより、各パッケージ部に分離して
所望するパッケージを得た。Specific Example 3 A photosensitive dry film resist (product name: PHOTEC HN640, manufactured by Hitachi Chemical Co., Ltd.) was laminated on a shiny surface of an electrolytic copper foil having a thickness of 35 μm and an outer shape of 250 mm, and exposed and developed. A desired resist pattern (minimum line / space = 50 μm / 50 μm) was formed. next,
Nickel with thickness of 0.2μm, 30μm by electroplating method
300 identical wiring patterns composed of copper, 5μm nickel and 1μm soft gold (4 blocks / 250mm square, 75
Pieces / block) formed. Next, the resist pattern is peeled off using a potassium hydroxide solution having a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, cut into blocks, and a die bond material for semiconductor element mounting (Hitachi Chemical Industries, Ltd. The semiconductor element was bonded using HM-1) (trade name, manufactured by Co., Ltd.). The bonding conditions are a pressing pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressing time of 5 seconds. Next, after electrically connecting the external terminal of the semiconductor element and the gold-plated terminal portion (second connection portion) by wire bonding, the semiconductor terminal is set in a transfer mold, and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industries, Ltd. Product name:
75 wiring patterns (corresponding to one block) were collectively sealed at 185 ° C. for 90 seconds using CL-7700) to transfer each wiring pattern into the sealing material. Next, alkaline etchant (Meltex Co., Ltd., trade name: A process)
A desired portion of the electrolytic copper foil was removed by etching using. Etchant temperature 40 ° C, spray pressure 1.2kgf
/ cm2. Next, a solder pattern was formed on the external connection terminal portion by a printing method, and the solder was melted by an infrared reflow furnace to form an external connection bump. Finally, a desired package was obtained by separating the package into parts using a diamond cutter.

【００８６】具体例４ 厚さ35μｍ、外形250ｍｍ角の電解銅箔のシャイニー面
に、感光性ドライフィルムレジスト（日立化成工業
（株）製、商品名：フォテックHN640）をラミネート
し、露光、現像により所望するレジストパターン（最少
ライン/スペース=50μm /50μm ）を形成した。次に、
電気めっき法により、厚さ0.2μｍのニッケル、30μｍ
の銅、5μｍのニッケル及び1μｍのソフト金で構成され
る同一の配線パターンを300個（4ブロック/250mm角、75
個/ブロック）形成した。次に、液温35℃、濃度3wt%の
水酸化カリウム溶液を用いてレジストパターンを剥離
し、85℃で15分間乾燥後、各ブロックに切断後、半導体
素子実装用ダイボンド材（日立化成工業（株）製、商品
名：HM-1）を用いて半導体素子を接着した。接着条件
は、プレス圧力5kg/cm２、温度380℃及び圧着時間5秒で
ある。次に、半導体素子の外部端子と金めっき端子部
（第２の接続部）をワイヤボンドにより電気的に接続し
た。次に、パッケージ領域に相当する部分（15mm角）を
くり抜いた格子状ステンレス板を中間板としてトランス
ファーモールド金型にセットし、半導体封止用エポキシ
樹脂（日立化成工業（株）製、商品名：CL-7700）を用
いて185℃、90秒で75個（１ブロックに相当）の配線パ
ターンを一括封止することにより、各配線パターンを封
止材中に転写した。中間板の格子部分は、各パッケージ
が中間板から分離しやすいように12°のテーパがついて
いる。次に、アルカリエッチャント（メルテックス
（株）製、商品名： A プロセス）を用いて電解銅箔の
所望する部分をエッチング除去した。各パッケージ部
は、格子状中間板で保持されている。エッチング液の温
度は40℃、スプレー圧力は1.2kgf/ cm２である。最後
に、印刷法により外部接続端子部にはんだパターンを形
成し、赤外線リフロー炉によりはんだを溶融させて外部
接続用バンプを形成し、中間板から各パッケージ部に分
離して所望するパッケージを得た。Specific Example 4 A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN640) was laminated on the shiny surface of an electrolytic copper foil having a thickness of 35 μm and an outer shape of 250 mm square, and exposed and developed. A desired resist pattern (minimum line / space = 50 μm / 50 μm) was formed. next,
Nickel with thickness of 0.2μm, 30μm by electroplating method
300 identical wiring patterns composed of copper, 5μm nickel and 1μm soft gold (4 blocks / 250mm square, 75
Pieces / block) formed. Next, the resist pattern is peeled off using a potassium hydroxide solution having a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, cut into blocks, and a die bond material for semiconductor element mounting (Hitachi Chemical Industries, Ltd. The semiconductor element was bonded using HM-1) (trade name, manufactured by Co., Ltd.). The bonding conditions are a pressing pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external terminals of the semiconductor element were electrically connected to the gold-plated terminal portions (second connection portions) by wire bonding. Next, a grid-shaped stainless steel plate having a portion corresponding to the package area (15 mm square) cut out is set as an intermediate plate in a transfer mold, and an epoxy resin for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: 75 wiring patterns (corresponding to one block) were collectively sealed at 185 ° C. for 90 seconds using CL-7700) to transfer each wiring pattern into the sealing material. The grid portion of the intermediate plate is tapered at 12 ° so that each package can be easily separated from the intermediate plate. Next, a desired portion of the electrolytic copper foil was removed by etching using an alkaline etchant (trade name: A process, manufactured by Meltex Co., Ltd.). Each package section is held by a grid-like intermediate plate. The temperature of the etching solution is 40 ° C., and the spray pressure is 1.2 kgf / cm 2. Finally, a solder pattern was formed on the external connection terminal portion by a printing method, the solder was melted by an infrared reflow furnace to form a bump for external connection, and the desired package was obtained by separating the intermediate plate into each package portion. .

【００８７】図２２により本発明の第十八の実施例につ
いて説明する。Referring to FIG. 22, an eighteenth embodiment of the present invention will be described.

【００８８】導電性の仮支持体６１（図２２ａ）上に複
数組の所定のレジストパターン６２（図２２ｂ）を形成
する。次に、電気めっき法により仮支持体の露出部に配
線パターン６３を形成する。この場合、仮支持体は特に
限定されるものではなく、例えば、通常の電解銅箔や電
解銅箔上に銅箔と化学エッチング条件の異なる金属（ニ
ッケル、金、はんだ等）の薄層を設けたものなどが適用
できる。また、配線パターンとしては銅が好ましいが、
前述のように電解銅箔を仮支持体として適用する場合に
は、銅箔とエッチング条件の異なる金属自体を配線パタ
ーンとして適用したり、あるいは、銅箔エッチング時の
バリヤ層となるパターン薄層をパターン銅めっき前に形
成したりする必要がある。仮支持体の厚さは、後工程で
のハンドリング性や半導体素子実装時の寸法安定性など
の点で支障がなければ特に限定されることはない。次
に、仮支持体をカソードとして金ワイヤボンド用のめっ
き（通常は、ニッケル/金）６４を施した後、レジスト
パターンを除去する（図２２ｃ）。なお、本発明は半導
体素子の実装方式がフェースアップ方式の場合に限定さ
れるものではなく、例えば、フェースダウン方式の場合
にも適用可能である。具体的には、配線パターン６３上
の所定位置にフェースダウンボンド用のバンプをめっき
法などにより形成した後、半導体素子の外部接続部とバ
ンプとを電気的に接続させれば良い。A plurality of sets of predetermined resist patterns 62 (FIG. 22B) are formed on the conductive temporary support 61 (FIG. 22A). Next, a wiring pattern 63 is formed on the exposed portion of the temporary support by an electroplating method. In this case, the temporary support is not particularly limited. For example, a thin layer of a metal (nickel, gold, solder, etc.) having different chemical etching conditions from the copper foil is provided on a normal electrolytic copper foil or an electrolytic copper foil. Can be applied. Also, copper is preferable as the wiring pattern,
When the electrolytic copper foil is used as the temporary support as described above, the metal itself having different etching conditions from the copper foil is used as a wiring pattern, or a thin pattern layer serving as a barrier layer during copper foil etching is used. It must be formed before the pattern copper plating. The thickness of the temporary support is not particularly limited as long as there is no problem in handling properties in a later step and dimensional stability in mounting a semiconductor element. Next, after performing plating (usually nickel / gold) 64 for gold wire bonding using the temporary support as a cathode, the resist pattern is removed (FIG. 22c). Note that the present invention is not limited to the case where the mounting method of the semiconductor element is a face-up method, and is applicable to, for example, a case where the mounting method is a face-down method. Specifically, after a bump for face-down bonding is formed at a predetermined position on the wiring pattern 63 by a plating method or the like, the external connection portion of the semiconductor element and the bump may be electrically connected.

【００８９】次に、半導体素子６５をダイボンド材６６
などで接着し、半導体素子の外部接続端子と配線パター
ンとを電気的に接続する（図２２ｄ）。次に、トランス
ファーモールド用金型にセットし、樹脂封止材６８で封
止する（図２２ｅ）。この場合、樹脂封止材は特に限定
するものではなく、例えば、直径10〜20μｍ程度のシリ
カを5〜80wt%の範囲で含有したエポキシ樹脂が適用でき
る。Next, the semiconductor element 65 is replaced with a die bonding material 66.
Then, the external connection terminals of the semiconductor element are electrically connected to the wiring patterns (FIG. 22D). Next, it is set in a transfer mold and sealed with a resin sealing material 68 (FIG. 22E). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied.

【００９０】次に、外部接続端子に相当する箇所に所定
の金属パターン６９を形成する（図２２ｆ）。この場
合、適用する金属としては、導電性仮支持体をエッチン
グ除去する条件下でエッチングされないものであれば良
く、例えば、はんだ、金、ニッケル/金などが適用可能
である。また、金属パターンの形成法としては、公知の
電気めっき法やはんだ印刷法などが適用できる。更に、
金属パターン６９をはんだパターンを印刷法で形成する
場合、リフローすることによりハンダバンプ７０を形成
することができる。この場合、パターン６９の厚さを調
節することにより、リフロー後のはんだバンプ７０の高
さを制御することができる。次に、金属パターンをエッ
チングレジストとして仮支持体の所定部分を除去し、配
線パターンを露出させる。Next, a predetermined metal pattern 69 is formed at a position corresponding to the external connection terminal (FIG. 22F). In this case, the metal to be applied only needs to be one that is not etched under the condition of removing the conductive temporary support by etching, and for example, solder, gold, nickel / gold, etc. can be applied. In addition, as a method of forming a metal pattern, a known electroplating method, a solder printing method, or the like can be applied. Furthermore,
When the metal pattern 69 is formed by printing a solder pattern, the solder bump 70 can be formed by reflow. In this case, by adjusting the thickness of the pattern 69, the height of the solder bump 70 after reflow can be controlled. Next, a predetermined portion of the temporary support is removed using the metal pattern as an etching resist to expose the wiring pattern.

【００９１】最後に、金型加工、あるいは、ダイシング
加工など適用して各パッケージ７１を分割する（図２２
ｇ）。なお、露出した配線パターンがニッケルなどの耐
腐食性金属で保護されていない場合には、外部接続端子
部以外の領域を公知のソルダーレジストなどで被覆して
も良い。また、はんだを金属パターンとして適用する場
合、リフロー工程は特に限定するものではなく、各パッ
ケージに分割する前でも後でも良いし、あるいは、外部
配線基板上に各パッケージを実装する際に行なっても良
い。Finally, each package 71 is divided by applying die processing or dicing processing (FIG. 22).
g). If the exposed wiring pattern is not protected by a corrosion-resistant metal such as nickel, a region other than the external connection terminal may be covered with a known solder resist or the like. When solder is applied as a metal pattern, the reflow step is not particularly limited, and may be performed before or after dividing into each package, or may be performed when each package is mounted on an external wiring board. good.

【００９２】第十八の実施例を具体的に説明する。The eighteenth embodiment will be specifically described.

【００９３】具体例５ 厚さ70μｍの電解銅箔のシャイニー面に、感光性ドライ
フィルムレジスト（日立化成工業（株）製、商品名：フ
ォテックHN640）をラミネートし、露光、現像により所
望するレジストパターン（最少ライン/スペース=50μm
/50μm ）を形成した。次に、電気めっき法により、厚
さ0.2μｍのニッケル、30μｍの銅、5μｍのニッケル及
び1μｍのソフト金で構成される配線パターンを形成し
た。次に、液温35℃、濃度3wt%の水酸化カリウム溶液を
用いてレジストパターンを剥離し、85℃で15分間乾燥
後、半導体素子実装用ダイボンド材（日立化成工業
（株）製、商品名：HM-1）を用いて半導体素子を接着し
た。接着条件は、プレス圧力5kg/cm２、温度380℃及び
圧着時間5秒である。次に、半導体素子の外部端子と金
めっき端子部（第２の接続部）をワイヤボンドにより電
気的に接続した後、トランスファーモールド金型にセッ
トし、半導体封止用エポキシ樹脂（日立化成工業（株）
製、商品名：CL-7700）を用いて185℃、90秒で封止する
ことにより、配線パターンを封止材中に転写した。次
に、電解銅箔上に感光性ドライフィルムレジスト（日立
化成工業（株）製、商品名：フォテックHN340）をラミ
ネートし、露光、現像により所望するレジストパターン
を形成後、電気めっき法により厚さ40μｍのはんだパッ
ド（直径0.3ｍｍφ、配置ピッチ1.0ｍｍ）を形成した。
次に、ドライフィルムレジストを剥離した後、アルカリ
エッチャント（メルテックス（株）製、商品名： A プ
ロセス）を用いて電解銅箔の所望する部分をエッチング
除去した。エッチング液の温度は40℃、スプレー圧力は
1.2kgf/cm２である。最後に、赤外線リフロー炉により
はんだを溶融させて外部接続用バンプを形成した。Specific Example 5 A photosensitive dry film resist (trade name: PHOTEC HN640, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the shiny surface of a 70 μm-thick electrolytic copper foil, and the desired resist pattern was obtained by exposure and development. (Minimum line / space = 50μm
/ 50 µm). Next, a wiring pattern composed of nickel having a thickness of 0.2 μm, copper having a thickness of 30 μm, nickel having a thickness of 5 μm, and soft gold having a thickness of 1 μm was formed by electroplating. Next, the resist pattern is peeled off using a potassium hydroxide solution having a concentration of 3 wt% at a liquid temperature of 35 ° C., and dried at 85 ° C. for 15 minutes. Then, a die bonding material for semiconductor device mounting (trade name, manufactured by Hitachi Chemical Co., Ltd.) : HM-1). The bonding conditions are a pressing pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressing time of 5 seconds. Next, after electrically connecting the external terminal of the semiconductor element and the gold-plated terminal portion (second connection portion) by wire bonding, the semiconductor terminal is set in a transfer mold, and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industries, Ltd. stock)
(Trade name: CL-7700, manufactured at 185 ° C.) for 90 seconds to transfer the wiring pattern into the sealing material. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: PHOTEC HN340) is laminated on the electrolytic copper foil, and a desired resist pattern is formed by exposure and development. A 40 μm solder pad (diameter 0.3 mmφ, arrangement pitch 1.0 mm) was formed.
Next, after removing the dry film resist, a desired portion of the electrolytic copper foil was removed by etching using an alkali etchant (trade name: A process, manufactured by Meltex Co., Ltd.). The temperature of the etchant is 40 ° C and the spray pressure is
It is 1.2 kgf / cm2. Finally, the solder was melted by an infrared reflow furnace to form external connection bumps.

【００９４】図２３、２４、２５により本発明の第十九
の実施例を説明する。A nineteenth embodiment of the present invention will be described with reference to FIGS.

【００９５】半導体実装用フレームの構成について図２
３を用いて説明する。８９は半導体実装用基板であり絶
縁基材と配線によって構成される。基板部と連結部９０
を介して、複数個連結されている。連結部９０には、基
準位置用ピン穴９１が形成される。ピン穴９１の代わり
に画像認識で用いられる認識マーク等でも構わない。後
工程では、これらの基準位置をもとに位置が決められ
る。特に半導体を樹脂でモールドする際はキャビティ内
のピンをピン穴９１にさして位置合わせを行うことなど
が行われる。FIG. 2 shows the structure of the semiconductor mounting frame.
3 will be described. Reference numeral 89 denotes a semiconductor mounting substrate, which is composed of an insulating base and wiring. Board part and connecting part 90
Are connected to each other. A reference position pin hole 91 is formed in the connecting portion 90. Instead of the pin hole 91, a recognition mark or the like used in image recognition may be used. In the post-process, the position is determined based on these reference positions. In particular, when a semiconductor is molded with a resin, a pin in a cavity is inserted into a pin hole 91 to perform positioning.

【００９６】更に図２４及び２５を用いて説明する。導
電性仮基板である厚さ約０．０７０ｍｍの電解銅箔８１
の片面に厚さ０．００１ｍｍのニッケル層（図２４、２
５では省略）を電解めっきで形成した。次に感光性ドラ
イフィルムレジスト（日立化成工業（株）製、商品名：
フォテックＨＮ３４０）をラミネートし、露光、現像に
より複数組の配線パターンのめっきレジストを形成す
る。この時の露光量は70mJ/cm２である。さらに、公知
の硫酸銅浴にて電解銅めっきを行い、レジストを剥離
し、複数組の配線８２を形成する（図２４ａ、図２５
ａ）。ここで、図２５ａに示したように連結部もにめっ
き銅８２’を形成することも考えられ、これにより出来
上がりのフレームの剛性をさらに高めることも可能であ
る。図２４ａ、図２５ａに示した構成は、銅／ニッケル
薄層／銅の３層からなる基材をあらかじめ用意し、片方
の銅箔を通常のエッチング工程で配線形成しても得られ
る。また、ここで得られた銅箔８１／ニッケル薄層（図
示せず）／銅配線８２（及び８２’）の構成を銅箔／ニ
ッケル配線、ニッケル箔／銅配線等、ニッケル薄層のな
い２層構造にしてもよい。すなわち、金属種の撰択は本
実施例の種類に限られることはないが、後の工程で仮基
板の一部をエッチング除去（図２４ｃ、図２５ｃ）した
ときに、配線が撰択的に残るようにできることが好適な
撰択基準となる。また、導電性仮基板はフレームの連結
部の構成材となるため厚いほうが好ましいが、後でその
一部をエッチング除去する工程があるため、適当な厚さ
を撰択する必要がある。導電性仮基板の厚みとしては、
材質にもよるが、例えば銅箔を用いる場合、約０．０３
〜０．３ｍｍ程度が好ましい。次に、複数組の配線８２
を形成した銅箔８１の配線面にポリイミド接着剤８３を
接着した。ここで、ポリイミド接着剤８３は、この材料
に限られることなく、例えば、エポキシ系接着フィル
ム、ポリイミドフィルムに接着剤を塗布したフィルム等
も利用可能である。次に、エキシマレーザを用いて外部
接続端子用穴８４を形成した（図２４ｂ、図２５ｂ）。
後工程における工程簡略化のためには半導体を実装する
前に接続端子を設けておくことが好適である。また、こ
の穴８４の形成法として他に、あらかじめドリルやパン
チ加工でフィルムに外部接続端子用穴８４を形成してお
き、このフィルムを接着する方法を用いてもかまわな
い。さらにここで、この穴８４に接続端子として用いる
半田等の金属（図２４ｆ、図２５ｆの８８に相当）を充
填させておいてもかまわないが、後の半導体実装工程、
樹脂封止工程では、金属突起が障害となることもあり、
後の工程で形成する方が好ましい。半導体素子実装基板
部の外部接続端子用穴（または端子）は半導体素子搭載
反対面にアレイ状に配置されるようにしるのが好まし
い。Further description will be made with reference to FIGS. Electrolytic copper foil 81 having a thickness of about 0.070 mm which is a conductive temporary substrate
A nickel layer having a thickness of 0.001 mm (see FIGS. 24 and 2)
5 is omitted) by electrolytic plating. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name:
POTEK HN340) is laminated, and a plurality of sets of wiring pattern plating resists are formed by exposure and development. The exposure amount at this time is 70 mJ / cm2. Further, electrolytic copper plating is performed in a known copper sulfate bath, the resist is stripped, and a plurality of sets of wirings 82 are formed (FIGS. 24A and 25).
a). Here, as shown in FIG. 25a, it is conceivable to form plated copper 82 'also on the connecting portion, and thereby it is possible to further increase the rigidity of the completed frame. The configuration shown in FIGS. 24a and 25a can also be obtained by preparing a base material composed of three layers of copper / nickel thin layer / copper in advance and forming wiring on one of the copper foils by a normal etching process. The structure of the copper foil 81 / nickel thin layer (not shown) / copper wiring 82 (and 82 ') obtained here was changed to copper foil / nickel wiring, nickel foil / copper wiring, etc. It may have a layered structure. That is, the selection of the metal type is not limited to the type of the present embodiment, but when a part of the temporary substrate is removed by etching (FIGS. 24c and 25c) in a later step, the wiring is selectively selected. Being able to remain is a suitable selection criterion. Further, the conductive temporary substrate is preferably thick because it becomes a constituent material of the connecting portion of the frame, but it is necessary to select an appropriate thickness because there is a step of etching and removing a part thereof later. As the thickness of the conductive temporary substrate,
Depending on the material, for example, when using copper foil, about 0.03
About 0.3 mm is preferable. Next, a plurality of sets of wirings 82
A polyimide adhesive 83 was adhered to the wiring surface of the copper foil 81 on which was formed. Here, the polyimide adhesive 83 is not limited to this material, and for example, an epoxy-based adhesive film, a film in which an adhesive is applied to a polyimide film, or the like can be used. Next, an external connection terminal hole 84 was formed using an excimer laser (FIGS. 24B and 25B).
It is preferable to provide connection terminals before mounting the semiconductor for simplifying the process in a later process. Alternatively, as a method for forming the holes 84, a method may be used in which the holes 84 for external connection terminals are previously formed in the film by drilling or punching, and the film is bonded. Here, the hole 84 may be filled with a metal such as solder (corresponding to 88 in FIGS. 24F and 25F) used as a connection terminal, but it may be filled in a later semiconductor mounting step.
In the resin encapsulation process, metal protrusions may be an obstacle,
It is preferable to form them in a later step. The holes (or terminals) for external connection terminals of the semiconductor element mounting board portion are preferably arranged in an array on the surface opposite to the semiconductor element mounting.

【００９７】次に、配線パターンが形成されている部分
の仮基板である電解銅箔の一部をエッチング除去した。
このエッチング液として、この実施例の構成の場合、ニ
ッケルに比べて銅の溶解速度が著しく高いエッチング
液、エッチング条件を撰択するのがよい。この実施例で
は、エッチング液としてアルカリエッチャント（メルテ
ックス（株）製、商品名： A プロセス）が、エッチン
グ条件としては例えば液温度を40℃、スプレー圧力を1.
2kgf/cm２とした。ここで示した液の種類、条件は一例
にすぎない。この工程によって基板部分のニッケル薄層
が露出される。このニッケル薄層だけをエッチングする
際には、銅よりニッケルの溶解速度が著しく高いエッチ
ング液、エッチング条件を撰択するのがよい。この実施
例では、ニッケルエッチャント（メルテックス（株）
製、商品名：メルストリップ N950）で選択的にエッチ
ング除去した。エッチング液の温度を40℃、スプレー圧
力を1.2kgf/cm２とした。ここで示した液の種類、条件
も一例にすぎない。このような工程を経て、連結部の仮
基板が残され、剛性のある半導体実装用フレームが得れ
れる（図２４ｃ、図２５ｃ）。この実施例ではこのフレ
ームの銅配線端子部分には無電解ニッケル−金めっきが
施される（図では省略）。これは、後工程でチップをワ
イヤーボンディングするために必要であり、このような
表面処理は必要に応じて施せばよい。Next, a part of the electrolytic copper foil as the temporary substrate in the portion where the wiring pattern was formed was removed by etching.
In the case of the structure of this embodiment, it is preferable to select an etching solution having an extremely high dissolution rate of copper as compared with nickel and an etching condition. In this embodiment, an alkaline etchant (manufactured by Meltex Co., Ltd., trade name: A process) is used as an etching solution, and the etching conditions are, for example, a solution temperature of 40 ° C. and a spray pressure of 1.
It was 2 kgf / cm2. The types and conditions of the liquids shown here are only examples. This step exposes the thin nickel layer on the substrate portion. When etching only the nickel thin layer, it is preferable to select an etching solution and etching conditions in which the dissolution rate of nickel is much higher than that of copper. In this embodiment, a nickel etchant (Meltex Co., Ltd.)
(Trade name: Melstrip N950). The temperature of the etching solution was 40 ° C., and the spray pressure was 1.2 kgf / cm 2. The types and conditions of the liquids shown here are only examples. Through these steps, the temporary substrate of the connecting portion is left, and a rigid semiconductor mounting frame is obtained (FIGS. 24c and 25c). In this embodiment, electroless nickel-gold plating is applied to the copper wiring terminal portion of the frame (not shown in the figure). This is necessary in order to wire-bond the chip in a later step, and such a surface treatment may be performed as needed.

【００９８】さらに半導体チップ８５を搭載する。半導
体チップの接着には、半導体用ダイボンディングテープ
８６（例えば、日立化成工業（株）製、商品名：HM-1）
を用いた。ここで、チップの下に配線がない場合には、
ダイボンド用銀ペーストを用いて接着してもよい。次に
半導体端子部と配線とをワイヤボンド１００により接続
する（図２４ｄ、図２５ｄ）。半導体端子との接続は、
他の方法、例えば、フェイスダウンによるフィリップチ
ップ接続や異方導電性背着剤による接着でもよい。この
ようにして形成したものをトランスファモールド金型に
装填し、半導体封止用エポキシ樹脂（日立化成工業
（株）製、商品名：ＣＬ−７７００）を用いて各々封止
８７する（図２４ｅ、図２５ｅ）。その後、配線８２の
接続端子部に設けた接続用穴にはんだボール８８を配置
し溶融させて形成する（図２４ｆ、図２５ｆ）。このは
んだボール８８はいわゆる外部接続端子となる。連結部
１０２によってつながっている複数個の半導体装置を金
型で打ち抜いて個々の半導体装置が得られる（図２４
ｇ、図２５ｇ）。Further, a semiconductor chip 85 is mounted. For bonding of the semiconductor chip, a die bonding tape 86 for semiconductor (for example, HM-1 manufactured by Hitachi Chemical Co., Ltd.)
Was used. Here, if there is no wiring under the chip,
The bonding may be performed using a silver paste for die bonding. Next, the semiconductor terminal portion and the wiring are connected by a wire bond 100 (FIGS. 24D and 25D). The connection with the semiconductor terminal
Other methods, for example, a flip-chip connection by face-down or adhesion by an anisotropic conductive backing agent may be used. The thus formed product is loaded into a transfer mold and sealed 87 using an epoxy resin for semiconductor encapsulation (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 24E, Figure 25e). Thereafter, solder balls 88 are arranged in connection holes provided in connection terminal portions of the wirings 82 and are melted (FIGS. 24f and 25f). The solder balls 88 serve as so-called external connection terminals. Each semiconductor device is obtained by punching out a plurality of semiconductor devices connected by the connecting portion 102 with a mold (FIG. 24).
g, FIG. 25g).

【００９９】この実施例では、半導体実装用フレーム及
び半導体装置製造法により、ポリイミドテープ等フィル
ム基板を用いたBGA、CSP等の半導体装置製造において、
十分な剛性を備えたフレームを得ることができ、これを
利用することによって半導体装置を精度良く効率良く作
製可能になる。In this embodiment, a method for manufacturing a semiconductor device such as a BGA or a CSP using a film substrate such as a polyimide tape by a method for manufacturing a semiconductor mounting frame and a semiconductor device is described.
A frame having sufficient rigidity can be obtained, and by using this, a semiconductor device can be manufactured accurately and efficiently.

【０１００】本発明により、半導体チップの高集積度化
に対応することができる半導体パッケージを生産性良
く、かつ安定的に製造することができる。According to the present invention, a semiconductor package capable of coping with high integration of a semiconductor chip can be stably manufactured with high productivity.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 1 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図２】図２は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 2 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図３】図３は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図４】図４は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 4 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図５】図５は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 5 is a sectional view illustrating an example of a method of manufacturing a semiconductor package according to the present invention.

【図６】図６は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 6 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図７】図７は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 7 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図８】図８は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 8 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図９】図９は、本発明の半導体パッケージの製造法の
一例を説明する断面図である。FIG. 9 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１０】図１０は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 10 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１１】図１１は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 11 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１２】図１２は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 12 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１３】図１３は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 13 is a sectional view illustrating an example of a method of manufacturing a semiconductor package according to the present invention.

【図１４】図１４は、本発明の半導体パッケージの製造
法の一例を説明する平面図である。FIG. 14 is a plan view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１５】図１５は、本発明の半導体パッケージの製造
法の一例を説明する平面図である。FIG. 15 is a plan view illustrating an example of a method for manufacturing a semiconductor package of the present invention.

【図１６】図１６は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 16 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１７】図１７は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 17 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１８】図１８は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 18 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図１９】図１９は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 19 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図２０】図２０は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 20 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図２１】図２１は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 21 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図２２】図２２は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 22 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図２３】図２３は、本発明の半導体パッケージの製造
法の一例を説明する平面図である。FIG. 23 is a plan view illustrating an example of a method for manufacturing a semiconductor package of the present invention.

【図２４】図２４は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 24 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

【図２５】図２５は、本発明の半導体パッケージの製造
法の一例を説明する断面図である。FIG. 25 is a sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention.

───────────────────────────────────────────────────── フロントページの続き (31)優先権主張番号 特願平7−56202 (32)優先日 平成７年３月15日(1995．3．15) (33)優先権主張国 日本（ＪＰ） 早期審査対象出願 (72)発明者 大畑 洋人 茨城県つくば市花畑１−15−18 日立化 成紫峰寮Ｂ204号 (72)発明者 萩原 伸介 茨城県下館市玉戸1278−302 (72)発明者 田口 矩之 茨城県つくば市花畑１−15−18 日立化 成紫峰寮Ａ504号 (72)発明者 野村 宏 栃木県小山市網戸227 (56)参考文献 特開 平４−277636（ＪＰ，Ａ) 特開 平３−94459（ＪＰ，Ａ) 特開 平３−94430（ＪＰ，Ａ) 特開 昭59−208756（ＪＰ，Ａ) 特開 平１−289273（ＪＰ，Ａ) 特開 昭59−43554（ＪＰ，Ａ) 特開 昭60−160624（ＪＰ，Ａ) 特開 昭59−231825（ＪＰ，Ａ) 特開 昭61−222151（ＪＰ，Ａ) 特開 平５−218228（ＪＰ，Ａ) 実開 平４−26545（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 501 ────────────────────────────────────────────────── ─── Continued on the front page (31) Priority claim number Japanese Patent Application Hei 7-56202 (32) Priority date March 15, 1995 (March 15, 1995) (33) Priority claim country Japan (JP) Application for early examination (72) Inventor Hiroto Ohata 1-15-18 Hanahata, Tsukuba City, Ibaraki Prefecture Hitachi Chemical Shiseimine Dormitory B204 (72) Inventor Shinsuke Hagiwara 1278-302 Tamado, Shimodate City, Ibaraki Prefecture (72) Inventor Rin Taguchi No. 1-15-18 Hanahata, Tsukuba-shi, Ibaraki Pref.Hitachi Kasei Shimine Dormitory A504 (72) Inventor Hiroshi Nomura 227 Ado, Koyama-shi, Tochigi Pref. JP-A-3-94459 (JP, A) JP-A-3-94430 (JP, A) JP-A-59-208756 (JP, A) JP-A-1-289273 (JP, A) JP-A-59-43554 (JP, A) A) JP-A-60-160624 (JP, A) JP-A-59-231825 (JP, A) Akira 61-222151 (JP, A) JP flat 5-218228 (JP, A) JitsuHiraku flat 4-26545 (JP, U) (58 ) investigated the field (Int.Cl. 7, DB name) H01L 23 / 12 501

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】絶縁性支持体と、その片面に形成された複
数の配線とを備える半導体素子搭載用基板において、 半導体素子搭載領域と、該半導体素子搭載領域の外側の
樹脂封止用半導体パッケージ領域とを、複数組備え、 上記配線は、 上記半導体パッケージ領域に形成されたワイヤボンディ
ング端子と、上記半導体素子搭載領域に形成された外部
接続端子とをつなぐ配線を含み、 上記外部接続端子の形成された箇所の上記絶縁性支持体
に、上記外部接続端子に達する開口部が設けられている
ことを特徴とする半導体素子搭載用基板。 An insulative support and a plurality of members formed on one side thereof.
A semiconductor element mounting area having a number of wirings and a semiconductor element mounting area, and a semiconductor element mounting area outside the semiconductor element mounting area.
A plurality of pairs of semiconductor package regions for resin encapsulation, wherein the wiring is a wire bonder formed in the semiconductor package region;
Terminals and external parts formed in the semiconductor element mounting area.
Insulating support including a wiring connecting the connection terminal and the portion where the external connection terminal is formed
Has an opening reaching the external connection terminal.
A substrate for mounting a semiconductor element, comprising: 【請求項２】上記外部接続端子は、上記半導体素子搭載
領域ごとに二つ以上設けられることを特徴とする請求項
１記載の半導体素子搭載用基板。 2. The semiconductor device according to claim 2 , wherein the external connection terminal is mounted with the semiconductor element.
Claims wherein at least two are provided for each area.
2. The substrate for mounting a semiconductor element according to 1. 【請求項３】上記配線は、表面にニッケル及び金のめっ
き層を有することを特徴とする請求項１又は２記載の半
導体素子搭載用基板。 3. The wiring according to claim 1 , wherein the surface of the wiring is coated with nickel and gold.
3. A half as claimed in claim 1, wherein said half is provided.
Substrate for mounting conductive elements. 【請求項４】上記絶縁性支持体は、ポリイミドフィルム
であることを特徴とする請求項１〜３のいずれかに記載
の半導体素子搭載用基板。 4. The insulating support is a polyimide film.
4. The method according to claim 1, wherein
Semiconductor element mounting substrate. 【請求項５】上記外部接続端子は、上記半導体素子搭載
領域に格子状に形成されていることを特徴とする請求項
１〜４のいずれかに記載の半導体素子搭載用基板。 5. The semiconductor device according to claim 1 , wherein the external connection terminal is mounted with the semiconductor element.
The region is formed in a lattice shape.
The substrate for mounting a semiconductor element according to any one of claims 1 to 4. 【請求項６】上記開口部は、打ち抜き加工、ドリル加
工、レーザ加工及びウエットエッチング加工の少なくと
もいずれかにより開けられたものであることを特徴とす
る請求項１〜５のいずれかに記載の半導体素子搭載用基
板。 6. The opening is formed by punching, drilling,
Processing, laser processing and wet etching processing
Is also opened by any of
A substrate for mounting a semiconductor element according to claim 1.
Board. 【請求項７】請求項１〜６のいずれかに記載の半導体素
子搭載用基板と、 上記半導体素子搭載用基板の上記半導体素子搭載領域に
ダイボンディング材を介して搭載された半導体素子と、 上記半導体パッケージ領域に設けられた封止樹脂とを備
えることを特徴とする半導体パッケージ。 7. A semiconductor element according to claim 1,
Board for mounting the semiconductor element and the semiconductor element mounting area of the semiconductor element mounting board.
A semiconductor element mounted via a die bonding material and a sealing resin provided in the semiconductor package area are provided.
A semiconductor package characterized by the following characteristics. 【請求項８】上記ダイボンディング材はダイボンディン
グテープであることを特徴とする請求項７記載の半導体
パッケージ。 8. The die bonding material is a die bond.
8. The semiconductor according to claim 7, wherein the semiconductor is a tape.
package.
JP2002137362A 1994-03-18 2002-05-13 Semiconductor element mounting substrate and semiconductor package Expired - Fee Related JP3352084B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002137362A JP3352084B2 (en) 1994-03-18 2002-05-13 Semiconductor element mounting substrate and semiconductor package

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP4876094 1994-03-18
JP6-48760 1994-03-18
JP27346994 1994-11-08
JP6-273469 1994-11-08
JP768395 1995-01-20
JP7-7683 1995-01-20
JP7-56202 1995-03-15
JP5620295 1995-03-15
JP2002137362A JP3352084B2 (en) 1994-03-18 2002-05-13 Semiconductor element mounting substrate and semiconductor package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2001237791A Division JP3337467B2 (en) 1994-03-18 2001-08-06 Semiconductor package manufacturing method and semiconductor package

Publications (2)

Publication Number Publication Date
JP2002334951A JP2002334951A (en) 2002-11-22
JP3352084B2 true JP3352084B2 (en) 2002-12-03

Family

ID=27518850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002137362A Expired - Fee Related JP3352084B2 (en) 1994-03-18 2002-05-13 Semiconductor element mounting substrate and semiconductor package

Country Status (1)

Country Link
JP (1) JP3352084B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7434305B2 (en) 2000-11-28 2008-10-14 Knowles Electronics, Llc. Method of manufacturing a microphone
US8617934B1 (en) 2000-11-28 2013-12-31 Knowles Electronics, Llc Methods of manufacture of top port multi-part surface mount silicon condenser microphone packages
US7326591B2 (en) 2005-08-31 2008-02-05 Micron Technology, Inc. Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
US8375577B2 (en) * 2008-06-04 2013-02-19 National Semiconductor Corporation Method of making foil based semiconductor package
US9374643B2 (en) 2011-11-04 2016-06-21 Knowles Electronics, Llc Embedded dielectric as a barrier in an acoustic device and method of manufacture
US9078063B2 (en) 2012-08-10 2015-07-07 Knowles Electronics, Llc Microphone assembly with barrier to prevent contaminant infiltration
US9794661B2 (en) 2015-08-07 2017-10-17 Knowles Electronics, Llc Ingress protection for reducing particle infiltration into acoustic chamber of a MEMS microphone package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943554A (en) * 1982-09-03 1984-03-10 Toshiba Corp Resin-sealed semiconductor device
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package
JPS59231825A (en) * 1983-06-14 1984-12-26 Toshiba Corp Semiconductor device
JPS60160624A (en) * 1984-01-31 1985-08-22 Sharp Corp Dielectric isolation for semiconductor chip
JPS61222151A (en) * 1985-03-27 1986-10-02 Ibiden Co Ltd Manufacture of printed wiring substrate for mounting semiconductor
JPH01289273A (en) * 1988-05-17 1989-11-21 Matsushita Electric Ind Co Ltd Wiring board
JP2840317B2 (en) * 1989-09-06 1998-12-24 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
JP2840316B2 (en) * 1989-09-06 1998-12-24 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
JPH0426545U (en) * 1990-06-27 1992-03-03
JP2962586B2 (en) * 1991-03-05 1999-10-12 新光電気工業株式会社 Semiconductor device, method of manufacturing the same, and joined body used therefor
JPH05218228A (en) * 1992-02-04 1993-08-27 Ibiden Co Ltd Substrate for electronic component mounting use

Also Published As

Publication number Publication date
JP2002334951A (en) 2002-11-22

Similar Documents

Publication Publication Date Title
JP4862848B2 (en) Manufacturing method of semiconductor package
JP2916915B2 (en) Method of manufacturing ball grid array semiconductor package
JP4029910B2 (en) Manufacturing method of semiconductor package and semiconductor package
JP3352084B2 (en) Semiconductor element mounting substrate and semiconductor package
JP3337467B2 (en) Semiconductor package manufacturing method and semiconductor package
JP4196606B2 (en) Wiring board manufacturing method
JP4140555B2 (en) Manufacturing method of semiconductor package
JP3606275B2 (en) Semiconductor package and manufacturing method thereof
JP3352083B2 (en) Method for manufacturing semiconductor package and substrate for mounting semiconductor element
JP2005328057A (en) Manufacturing method of semiconductor package, and the semiconductor package
JP3685203B2 (en) Semiconductor device mounting substrate
JP3685205B2 (en) Semiconductor package and manufacturing method thereof
JP3413413B2 (en) Semiconductor element mounting substrate and method of manufacturing the same
JP3413191B2 (en) Semiconductor package manufacturing method and semiconductor package
JP3685204B2 (en) Semiconductor device mounting substrate
JP2936540B2 (en) Circuit board, method of manufacturing the same, and method of manufacturing semiconductor package using the same
JP2004247764A (en) Substrate for mounting semiconductor element
JP4115553B2 (en) Manufacturing method of semiconductor package
JP4115556B2 (en) Manufacturing method of semiconductor package

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: R3D04

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070920

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080920

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090920

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090920

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100920

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100920

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100920

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110920

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110920

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120920

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120920

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120920

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120920

Year of fee payment: 10

R157 Certificate of patent or utility model (correction)

Free format text: JAPANESE INTERMEDIATE CODE: R157

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120920

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130920

Year of fee payment: 11

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130920

Year of fee payment: 11

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees