JP3685205B2 - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package substrate that can meet the requirement for large scale integration of semiconductors. <P>SOLUTION: After through holes are formed for external connecting terminals in an insulating substrate by partially removing the substrate at spots forming the external wiring terminals of wiring, a plurality of sets of wiring is formed on one surface of the insulating substrate and semiconductor elements are mounted on the substrate on which the wiring is formed through die-bonding tapes. Then the terminals of the semiconductor elements are electrically connected to the wiring, and the semiconductor elements are sealed with a resin. Thereafter, the external connecting terminals electrically connected to the wiring are formed in the through holes for external connecting terminals, and the obtained product is divided into individual semiconductor packages. <P>COPYRIGHT: (C)2004,JPO&amp;NCIPI

Description

The present invention relates to a semiconductor package and a manufacturing method thereof .

(Background technology)
As the degree of integration of semiconductors has improved, the number of input / output terminals has increased. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, there are a type in which input / output terminals are arranged in a row around the package and a type in which the input / output terminals are arranged in multiple rows not only in the periphery but also in the interior. The former is typically QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in an area of 0.5 mm pitch or less, advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged with a relatively large pitch.

  Conventionally, the array type is generally a PGA (Pin Grid Array) having connection pins, but the connection to the wiring board is an insertion type and is not suitable for surface mounting. Therefore, a package called BGA (Ball Grid Array) that can be mounted on the surface has been developed. The BGA classification includes (1) ceramic type, (2) printed wiring board type, and (3) tape type using TAB (tape automated bonding). Among these, for ceramic types, the distance between the mother board and the package is shorter than that of the conventional PGA, so the package warpage due to the thermal stress difference between the mother board and the package is a serious problem. Also, the printed wiring board type has problems such as substrate warpage, moisture resistance, and reliability, as well as a large substrate thickness, and a tape BGA using TAB technology has been proposed.

  As a countermeasure for further downsizing of the package size, a so-called chip size package (CSP), which is almost the same size as a semiconductor chip, has been proposed. This is a package having a connection portion with an external wiring board in the mounting region, not in the peripheral portion of the semiconductor chip.

  As a specific example, a polyimide film with bumps is bonded to the surface of a semiconductor chip, and after electrical connection is made between the chip and a gold lead wire, epoxy resin is potted and sealed (NIKKEI MATERIALS & TECHNOLOGY 94. 4, No.140, p18-19) or metal bumps are formed on the temporary substrate at positions corresponding to the connections between the semiconductor chip and the external wiring board. After the semiconductor chip is face-down bonded, transfer is performed on the temporary substrate. Molded ones (Smallest Flip-Chip-Like Package CSP; The Second VLSI Packaging Workshop of Japan, p46-50, 1994).

  On the other hand, as described above, packages using polyimide tape as a base film are being studied in the BGA and CSP fields. In this case, the polyimide tape is generally laminated with a copper foil on a polyimide film via an adhesive layer, but a polyimide layer is directly formed on the copper foil from the viewpoint of heat resistance and moisture resistance. A so-called two-layer flexible substrate is preferred. The two-layer flexible substrate manufacturing method includes (1) a method in which a polyamic acid, which is a polyimide precursor, is applied on a copper foil, followed by thermosetting, and (2) a vacuum film-forming method or no method on a cured polyimide film. A method of forming a metal thin film by electrolytic plating or the like is roughly divided. For example, laser processing is applied to remove polyimide at a desired portion (corresponding to the second connection function portion) and reach the copper foil. Is preferably as thin as possible. On the other hand, when the two-layer flexible base material is processed into a lead frame and handled, there are problems such as lack of handling properties and rigidity as a frame if the base film thickness is thin.

  As described above, various proposals have been made as semiconductor packages that can cope with downsizing and high integration, but further improvements are desired to satisfy all of the performance, characteristics, productivity, and the like.

  The present invention provides a method for manufacturing a semiconductor package and a semiconductor package that enable a semiconductor package that can be reduced in size and highly integrated to be manufactured with high productivity and stability.

(Disclosure of the Invention)
In this invention, it is a manufacturing method of the package using the wiring board which has a temporary support body, Comprising: The process of forming a 1st wiring in the said board | substrate, and the process of forming an adhesive resin layer so that the said 1st wiring may be covered A step of forming a second wiring on the adhesive resin layer, a step of mounting a semiconductor element on the substrate on which the first and second wirings are formed, and a step of resin-sealing the semiconductor element And a step of removing the temporary support.

  In the present invention, a normal element such as an LSI chip or an IC chip can be used as the semiconductor element.

  As a method for allowing the semiconductor element terminal and the wiring to communicate with each other, not only wire bonding but also normal means such as a bump and an anisotropic conductive film can be used.

  In the present invention, a semiconductor package free from warpage and deformation can be produced by heat-treating the cured resin product after resin-sealing the semiconductor element.

  The heat treatment is preferably performed at a glass transition temperature ± 20 ° C. of the cured encapsulated resin. This is because the cured resin has the strongest plastic property within the range of the glass transition temperature ± 20 ° C., and it is easy to eliminate the residual strain. When the temperature of the heat treatment is less than the glass transition temperature of −20 ° C., the cured resin tends to be an elastic body in a glass state, and the effect of relaxation tends to be reduced. Similarly, the effect of eliminating distortion tends to be lost.

  Heat treatment at a glass transition temperature of ± 20 ° C of the cured encapsulated resin and then cooling to room temperature at a rate of 5 ° C / min or less can prevent the semiconductor package from warping and deformation more reliably. can do.

  The heat treatment and / or cooling step is preferably carried out in a state where the upper and lower surfaces of the cured encapsulated resin are pressed by a rigid flat plate with a force that suppresses warpage and deformation of the encapsulated cured resin.

  In the semiconductor package of the present invention, the wiring has a first connection function in which one side of the wiring is connected to the semiconductor chip in a single layer wiring, and the second connection function is connected to the external wiring on the opposite side of the wiring. It is comprised so that it may have.

  For example, solder bumps and gold bumps can be preferably used as the external connection terminals connected to the external wiring.

  It is preferable to provide the external connection terminals on the inner side from the position where the semiconductor element terminals are electrically connected to the wiring by wire bonding or the like (fan-in type). As described above, the external connection terminals are preferably arranged in a grid pattern on the lower surface on which the semiconductor element is mounted in terms of increasing the density.

(Best Mode for Carrying Out the Invention)
A first reference example of the present invention will be described with reference to FIG.

  A nickel layer (not shown in FIG. 1) having a thickness of 0.001 mm is plated on one surface of an electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 1a). In this way, the LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is formed (FIG. 1b). For bonding the LSI chip, a silver paste 4 for semiconductor was used. Next, the LSI terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 1c). What was formed in this way was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 1d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having low copper solubility to expose the wiring portion (FIG. 1e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed and melted in the wiring exposed portions (FIG. 1f). The solder balls 7 are connected to external wiring.

A second reference example of the present invention will be described with reference to FIG.

  A copper foil 1 having wirings 2 was created in the same manner as in FIG. 1 (FIG. 2a). The LSI chip 3 is mounted. In the LSI chip, gold bumps 8 are formed on the terminal portions, and the gold bumps 8 and the terminal portions of the wiring 2 are connected by heating and pressing (FIG. 2b). Next, the lower part of the LSI chip is filled with a liquid epoxy resin and cured 9 (FIG. 2c). What was formed in this way was loaded into a transfer mold, and sealed 10 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 2d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having a low copper solubility to expose the wiring portion (FIG. 2e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed wiring portions and melted (FIG. 2f). The solder balls 7 are connected to external wiring.

The Figure 3, a description will be given of an embodiment 1 of the present invention.

  A nickel layer (not shown in FIG. 3) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath to form the first wiring 13. Next, the plating resist is peeled off, and the surface of the first wiring 13 is subjected to oxidation treatment and reduction treatment. Using a polyimide adhesive film (manufactured by Hitachi Chemical Co., Ltd., trade name: AS2210) 12 as a new copper foil and adhesive resin, lamination bonding is performed so that the wiring 13 is on the inside. (A hole having a diameter of 0.1 mm is formed in the copper foil 11 by a normal photoetching method. The inside of the hole and the entire surface of the copper foil are copper-plated by a panel plating method.) Form. The resin (polyimide adhesive film 12) on the LSI mounting portion is removed by an excimer laser to expose the terminal portion. The terminal part is plated with 0.003 mm of nickel plating and gold plating with a purity of 99.9% or more with a thickness of 0.0003 mm or more (FIG. 3a). In this manner, the LSI chip is mounted on the copper foil 1 on which the two-layer wiring is formed. For bonding the LSI chip, a silver paste for semiconductor was used (FIG. 3b). Next, the LSI terminal portion and the wiring 13 are connected by a wire bond 100 (FIG. 3c). What was formed in this way was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having low copper solubility to expose the wiring portion (FIG. 3e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed portions and melted (FIG. 3f). The solder balls 7 are connected to external wiring.

A third reference example of the present invention will be described with reference to FIG.

  A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on a SUS (stainless steel) plate 14 having a thickness of 0.1 mm, and the wiring pattern is exposed and developed, and the plating resist is applied. Form. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 4a). The semiconductor chip 103 is mounted on the SUS plate 14 on which the wiring 2 is formed in this way (FIG. 4b). A semiconductor-based silver base 4 was used for bonding the semiconductor chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 4c). What was formed in this way was loaded into a transfer mold, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 4d). Thereafter, the SUS plate 14 was mechanically peeled and removed to expose the wiring portion (FIG. 4e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed wiring portion and melted (FIG. 4f). The solder balls 7 are connected to external wiring.

A fourth reference example of the present invention will be described with reference to FIG.

  A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, after nickel pattern plating 15 is performed, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 5a). The semiconductor chip 103 is mounted on the copper foil 1 on which the wiring 2 is thus formed (FIG. 5b). For bonding the semiconductor chip, a silver base 4 for semiconductor was used. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 5c). What was formed in this way was loaded into a transfer mold die, and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 5d). Thereafter, the copper foil 1 was dissolved and removed with an alkaline etchant to expose the nickel wiring portion (FIG. 5e). Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the exposed wiring portions and melted (FIG. 5f). The solder balls 7 are connected to external wiring.

A fifth reference example of the present invention will be described with reference to FIG.

  A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, gold plating with a purity of 99.9% or more is plated with a thickness of 0.0003 mm and nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, the plating resist is peeled off, and the wiring 2 is formed (FIG. 6a). The polyimide film 16 is bonded to the wiring surface of the copper foil 1 on which the wiring 2 is formed in this way, the connection terminal portion of the wiring 2 is exposed using a laser (FIG. 6b), and the copper foil 1 is removed by etching. (Figure 6c). Further, by using a photosensitive film instead of polyimide, the connection terminal portion can be exposed without using a laser. Subsequently, the LSI chip 3 is mounted on the wiring pattern surface of the polyimide film 16. A semiconductor silver paste 4 was used for bonding the LSI chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 6d). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 6e). Thereafter, the solder balls 7 are placed on the connecting terminal portions and melted (FIG. 6f). The solder balls 7 are connected to external wiring.

A sixth reference example of the present invention will be described with reference to FIG.

  A nickel layer (not shown in FIG. 7) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 7a). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is thus formed. A semiconductor silver paste 4 was used for bonding the LSI chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 7b). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 7c). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant to expose nickel. The wiring layer is exposed by removing the nickel layer with a nickel stripping solution having low copper solubility (FIG. 7d). Subsequently, the polyimide film 16 having the connection terminal portion opened is adhered (FIG. 7e), and the solder balls 7 are disposed on the wiring exposed portion and melted (FIG. 7f). The solder balls 7 are connected to external wiring.

A seventh reference example of the present invention will be described with reference to FIG.

  A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, gold plating with a purity of 99.9% or more is plated with a thickness of 0.0003 mm and nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, and the plating resist is peeled off to form the wiring 2 (FIG. 8a). The liquid sealing resin 17 is applied by screen printing to the wiring surface of the copper foil 1 on which the wiring 2 is formed in this way, and an insulating layer is formed so as to expose the connection terminal portion of the wiring 2 (FIG. 8b). . After the liquid sealing resin is cured, the copper foil 1 is removed by etching (FIG. 8c). Subsequently, the LSI chip 3 is mounted on the wiring pattern surface of the cured liquid sealing resin 3. A semiconductor silver paste 4 was used for bonding the LSI chip. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 8d). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 8e). Thereafter, solder balls 7 are disposed on the connection terminal portions of the wiring 2 and melted (FIG. 8f). The solder balls 7 are connected to external wiring.

The eighth reference example of the present invention will be described with reference to FIG.

  A nickel layer (not shown in FIG. 9) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and the wiring pattern is exposed and developed to form a plating resist. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, the plating resist is removed to form the wiring 2 (FIG. 9a). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 is thus formed. A semiconductor silver paste 4 was used for bonding the LSI chip 3. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 9b). The product thus formed is loaded into a transfer mold and sealed 5 using a semiconductor sealing epoxy resin (trade name: CL-7700, manufactured by Hitachi Chemical Co., Ltd.) (FIG. 9c). Thereafter, only the copper foil 1 is dissolved and removed with an alkali etchant to expose nickel. The nickel layer is removed with a nickel stripping solution with low copper solubility to expose the wiring portion (FIG. 9d). Subsequently, the liquid sealing resin 17 is applied by screen printing, and an insulating layer of the liquid sealing resin 17 is formed so as to expose the connection terminal portion of the wiring 2 (FIG. 9e). Solder balls 7 are placed on the connection terminals of the wires 2 and melted (FIG. 9f). The solder balls 7 are connected to external wiring.

The ninth reference example of the present invention will be described with reference to FIG.

  A nickel layer (not shown in FIG. 10) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plating resist for wiring patterns and alignment marks is formed by exposure and development. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Further, nickel plating is plated with a thickness of 0.003 mm and gold plating with a purity of 99.9% or more is 0.0003 mm or more. Next, after the plating resist is peeled off and the wiring 2 and the alignment mark 18 are formed (FIG. 10a), only the position of the alignment mark 18 is sandwiched between the SUS plates and pressed, so that the alignment mark is formed on the back surface of the copper foil 1. Is raised (FIG. 10b). The LSI chip 3 is mounted on the copper foil 1 on which the wiring 2 and the alignment mark 18 are thus formed (FIG. 10c). A semiconductor silver paste 4 was used for bonding the LSI chip 3. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 10d). What was formed in this way was loaded into a transfer mold die, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 10e). A photosensitive dry film is again laminated on the back side of the copper foil, and an etching pattern is formed using the alignment mark 18. Thereafter, the copper foil 1 and the nickel layer are etched to form the bumps 7 by the copper foil 1 and expose the wiring portion (FIG. 10f). Subsequently, a solder resist 8 was applied, and an insulating layer was formed so that the bumps 7 were exposed (FIG. 10g). The bumps 7 are connected to external wiring.

A tenth reference example of the present invention will be described with reference to FIG.

  A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil 1 having a thickness of 0.035 mm, and a plurality of sets of wiring patterns are exposed and developed to form a plating resist. Form. Subsequently, gold plating with a purity of 99.9% or more is plated with a thickness of 0.0003 mm and nickel plating with a thickness of 0.003 mm or more. Further, electrolytic copper plating is performed in a copper sulfate bath, the resist is peeled off, and a plurality of sets of wirings 2 are formed (FIG. 11a). In this way, the polyimide film 19 is adhered to the wiring surface of the copper foil 1 on which a plurality of sets of wirings 2 are formed, the connection terminal portions of the wirings 2 are exposed using a laser (FIG. 11b), and the copper foil 1 is etched. (Fig. 11c). As described above, after a plurality of sets of wirings 2 are formed on one polyimide film, the LSI chip 3 is mounted. For bonding the LSI chip, a semiconductor die bonding tape 4 'was used. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 11d). What was formed in this way was loaded into a transfer mold die, and each was sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 11e). . Thereafter, solder balls 7 are disposed on the connection terminal portions of the wiring 2 and melted (FIG. 11f). The solder balls 7 are connected to external wiring. Finally, the package connected with the polyimide film is punched out with a mold (FIG. 11g).

The Figure 12, will be described an eleventh exemplary embodiment of the present invention.

  A polyimide film 20 with an adhesive having a thickness of 0.07 mm is punched out with a mold and a portion to be a connection terminal portion is opened (FIG. 12a). Next, after bonding a copper foil 21 having a thickness of 0.035 mm (FIG. 12b), a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of sets of wiring patterns are formed. Exposure and development are performed to form an etching resist. Subsequently, the copper foil is etched, the resist is peeled off, and a plurality of sets of wirings 2 are formed (FIG. 12c). As described above, after a plurality of sets of wiring patterns are formed on one polyimide film, the LSI chip 3 is mounted. A semiconductor die bonding tape 4 ′ was used for bonding the LSI chip 3. Next, the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 12d). What was formed in this way was loaded into a transfer mold die, and each was sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 12e). . Thereafter, solder balls 7 are disposed on the connection terminal portions of the wiring and melted (FIG. 12f). The solder balls 7 are connected to external wiring. Finally, the package connected with the polyimide film is punched out with a mold (FIG. 12g).

By 13-15, there will be described a twelfth exemplary embodiment of the present invention.

A nickel layer (not shown in FIG. 13) having a thickness of 0.001 mm is plated on one surface of the electrolytic copper foil 1 having a thickness of 0.035 mm. A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of sets of wiring pattern plating resists are formed by exposure and development. Subsequently, electrolytic copper plating is performed in a copper sulfate bath. Furthermore, nickel plating was plated at a thickness of 0.003 mm and a purity of 99.9% or more at a thickness of 0.0003 mm or more, the plating resist was peeled off, and wiring 2 was formed (FIG. 13a). Next, the copper foil 1 on which the wiring 2 was formed was divided into unit numbers, and then attached to a separately prepared stainless steel frame 22 (thickness: 0.135 mm) via a polyimide adhesive film (FIG. 13b). As the frame, a copper alloy such as phosphor bronze, copper foil, nickel foil, nickel alloy foil or the like can be used. As other bonding methods, bonding using a eutectic between metals, bonding using ultrasonic waves, or the like can be used. Further, as shown in FIG. 14, the wiring on the copper foil 1 may be inspected in advance, and only the non-defective wiring 23 may be selected and attached to the frame 22. In FIG. 14, 1 is an electrolytic copper foil, 22 is a frame, 24 is a defective wiring product, and 25 is an alignment hole. In this reference example, one wire is provided on the cut copper foil, but a plurality of sets of wires may be provided on the cut copper foil. As the positional relationship of bonding between the frame 22 and the copper foil with wiring, various ones such as those shown in FIGS. 15A and 15B are possible. FIG. 15 is a plan view of the frame 22, wherein 26 is a frame opening, 27 is a mounting position of a copper foil with wiring, and 28 is an adhesive for fixing the foil. Next, the LSI chip 3 is mounted, and the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 13c). A semiconductor die bonding tape 4 'was used for mounting the LSI chip. Here, a silver paste for die bonding or the like may be used instead of the bonding tape 4 ′. Moreover, although the normal wire bonding connection was used for mounting the semiconductor chip, other methods such as a Philip chip may be used. What was formed in this way was loaded into a transfer mold die, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 13d). Thereafter, only the copper foil 1 was dissolved and removed with an alkali etchant to expose nickel. The nickel layer was removed with a nickel stripping solution having a low copper solubility to expose the wiring portion. Subsequently, a solder resist 6 was applied, and a pattern was formed so as to expose the connection terminal portion. Solder balls 7 were placed on the wiring exposed portions and melted (FIG. 13e). After that, it was cut using a cutting machine, and unnecessary sections 101 of the frame 22 were removed and divided into individual semiconductor packages (FIG. 13f). The solder balls 7 are connected to external wiring. In this example, the semiconductor package can be efficiently manufactured by raising the plate.

The Figure 16, will be described thirteenth exemplary embodiment of the present invention.

  A polyimide film 29 with an adhesive having a thickness of 0.07 mm is punched out with a mold and a portion to be a connection terminal portion is opened. Next, after bonding a copper foil having a thickness of 0.035 mm, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of wiring patterns are exposed and developed. An etching resist was formed. Subsequently, the copper foil is etched, the resist is peeled off, and a plurality of sets of wirings 2 are formed (FIG. 16a). Here, the connection terminal portion and the wiring 2 may be formed using a material obtained by directly coating polyimide on the copper foil (for example, Hitachi Chemical Co., Ltd., trade name: 50001). The opening may also be formed by exposure / development using a method such as drilling, laser processing such as excimer laser, printing, etc., or using a material having a photosensitive property on polyimide. Other materials such as a sealing resin may be used instead of polyimide.

  As described above, after forming a plurality of sets of wiring patterns on a single polyimide film, the stainless steel frame 22 (thickness) prepared separately via the polyimide adhesive adhesive 28 is obtained by dividing the film with wiring into unit numbers. ; 0.135 mm) (Fig. 16b). Next, the LSI chip 3 is mounted, and the semiconductor terminal portion and the wiring 2 are connected by the wire bond 100 (FIG. 16c). A semiconductor die bonding tape 4 'was used for mounting the LSI chip. What was formed in this way was loaded into a transfer mold die, and sealed 5 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 16d). Subsequently, the solder ball 7 is disposed and melted in the opening portion to be the connection terminal portion provided first (FIG. 16e). The solder balls 7 are connected to external wiring. Finally, the packages connected by the frame were punched out with a mold and divided into individual packages (FIG. 16f).

A fourteenth reference example of the present invention will be described with reference to FIG.

  A predetermined resist image is formed on the metal foil of a two-layer flexible base material (FIG. 17a) in which the insulating base material 32 is directly formed on the metal foil 31, and a plurality of desired wiring patterns 33 are formed by a known etching method. Then, the resist image is peeled off (FIG. 17b). As the metal foil, in addition to a single foil such as an electrolytic copper foil, a rolled copper foil, or a copper alloy foil, a composite metal foil having a thin copper layer on a carrier foil that can be removed in a later step can be applied. Specifically, a nickel-phosphorous plating layer having a thickness of about 0.2 μm is formed on one surface of an electrolytic copper foil having a thickness of 18 μm, and then a copper thin layer having a thickness of about 5 μm is subsequently applied. In this case, after the polyimide layer is formed on the copper thin layer, the copper thin layer is exposed by etching away the copper foil and the nickel-phosphorus layer. That is, in the present invention, the copper thin layer may be processed after exposing the entire copper thin layer, or the carrier foil (copper foil / nickel thin layer) is used as a part of the lead frame structure. Also good. On the other hand, a polyimide material is generally used as an insulating base material from the viewpoint of process heat resistance. In this case, if the thermal expansion coefficients of the polyimide and the copper foil are different, the warpage of the base material becomes remarkable in the solder reflow process. Therefore, as the polyimide, a polyimide containing 70 mol% or more of a polyimide having a repeating unit of (Chemical Formula 1) is used. It is preferable to apply.

  Next, a recess 34 reaching the copper foil is provided at a position to be a connection portion with the external substrate in a later process (FIG. 17c). The method for processing the recess is not particularly limited, and wet etching or the like can be applied in addition to laser processing such as excimer laser, carbon dioxide laser, and YAG laser.

  Next, a frame base material 37 with an adhesive 36 obtained by punching a predetermined portion (opening portion 35) by punching or the like is adhered to the wiring pattern surface (FIG. 17d). In this case, the frame base material is not particularly limited, and a metal foil such as a polyimide film or a copper foil can be applied. Here, if the polyimide layer thickness of the two-layer flexible base material is 25 μm and the frame base material to be bonded is a polyimide film, the film thickness is 50 to 70 μm to ensure the rigidity of the entire frame. A degree is required. The region for forming the frame base material layer is not particularly limited, and the frame base material layer can be provided in a portion where the semiconductor chip is mounted. Specifically, when the chip mounting is a wire bonding method, the frame base material layer may be provided in all other regions as long as the wire bonding terminal portions 38 are exposed. Next, the semiconductor chip 39 is mounted, and the semiconductor chip and the wiring pattern are electrically connected by the gold wire 40 (FIG. 17e). On the other hand, when the face-down method is adopted as the semiconductor chip mounting method, a metal bump or the like is provided at a predetermined position of the wiring pattern (corresponding to the position of the external connection electrode of the semiconductor chip), and the semiconductor chip and the wavy line through the metal bump. The pattern may be electrically connected. Next, it sets to the metal mold | die for transfer molding, and seals with the resin sealing material 41 (FIG. 17f). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. Next, the connection part 42 with the external substrate is formed. As a method of forming the connecting portion 42, a method of forming a bump having a thickness of a polyimide film or more in advance by an electrolytic plating method after the step of FIG. 17c, a method of forming a solder bump by a solder printing method after resin sealing, or the like is applied. Is possible. Finally, the package is cut from the frame to obtain the desired package (FIG. 17g).

Further illustrate the fourteenth reference example of FIG. 17.

Example 1
Dry film resist (manufactured by Hitachi Chemical Co., Ltd.) on the copper foil surface of a two-layer flexible substrate (manufactured by Hitachi Chemical Co., Ltd., trade name: MCF 5000I) having a 12 μm thick electrolytic copper foil on one side Name: Photec HK815) was laminated, and a desired resist pattern was obtained by exposure and development. Next, after etching the copper foil with a ferric chloride solution, a predetermined wiring pattern was obtained by peeling the resist pattern with a potassium hydroxide solution. Next, using an excimer laser processing machine (manufactured by Sumitomo Heavy Industries, Ltd., device name: INDEX200), a predetermined number of recesses (diameter 300 μm) reaching the back of the wiring pattern from the insulating substrate side are formed at a predetermined position. did. Excimer laser processing conditions are an energy density of 250 mJ / cm 2, a reduction ratio of 3.0, an oscillation frequency of 200 Hz, and an irradiation pulse number of 300 pulses. Next, an adhesive sheet having a polyimide adhesive material (product name: AS 2250, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 10 μm on one side of a polyimide film (product name: UPILEX S) having a thickness of 50 μm is provided. The predetermined region including the region corresponding to the wire bond terminal portion in the subsequent process was removed by punching, and the polyimide film and the two-layer flexible substrate with a wiring pattern were heat-pressed through an adhesive. The pressure bonding conditions are a pressure of 20 kgf / cm 2, a temperature of 180 ° C., and a heating and pressing time of 60 minutes. Next, nickel / gold plating was applied to the terminal portion for wire bonding by electroless nickel and gold plating. The plating thickness is 3 μm and 0.3 μm, respectively. Next, a semiconductor chip was mounted using a die bond material for mounting a semiconductor chip (trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.). The mounting conditions are a press pressure of 5 kgf / cm2, an adhesive temperature of 380 ° C., and a press bonding time of 5 seconds. Next, the external electrode portion of the semiconductor chip and the wiring pattern were electrically connected by wire bonding. After that, the die is processed into a lead frame shape, set in a transfer mold, and sealed with epoxy resin for semiconductor encapsulation (CL-7700, manufactured by Hitachi Chemical Co., Ltd.) at 185 ° C for 90 seconds. did. Subsequently, a predetermined amount of solder was printed and applied to the recesses described above, and the solder was melted in an infrared reflow furnace to form external connection bumps. Finally, the package part was punched with a mold to obtain a desired package.

A fifteenth reference example of the present invention will be described with reference to FIG.

  A predetermined resist image is formed on the metal foil of a two-layer flexible substrate (FIG. 18a) in which an insulating substrate 32 is directly formed on the metal foil 31, and a desired plurality of sets of wiring patterns 3 are formed by a known etching method. Then, the resist image is peeled off (FIG. 18b). As the metal foil, in addition to a single foil such as an electrolytic copper foil, a rolled copper foil, or a copper alloy foil, a composite metal foil having a thin copper layer on a carrier foil that can be removed in a later step can be applied. Specifically, a nickel-phosphorous plating layer having a thickness of about 0.2 μm is formed on one surface of an electrolytic copper foil having a thickness of 18 μm, and then a copper thin layer having a thickness of about 5 μm is subsequently applied. In this case, after the polyimide layer is formed on the copper thin layer, the copper thin layer is exposed by etching away the copper foil and the nickel-phosphorus layer. That is, in the present invention, the copper thin layer may be processed after exposing the entire copper thin layer, or the carrier foil (copper foil / nickel thin layer) is used as a part of the lead frame structure. Also good. On the other hand, a polyimide material is generally used as an insulating base material from the viewpoint of process heat resistance. In this case, if the thermal expansion coefficients of the polyimide and the copper foil are different, the warpage of the base material becomes remarkable in the solder reflow process. Therefore, as the polyimide, a polyimide containing 70 mol% or more of a polyimide having a repeating unit of (Chemical Formula 1) is used. It is preferable to apply.

  Next, a recess 34 reaching the copper foil is provided at a position to be a connection portion with the external substrate in a later process (FIG. 18c). The method for processing the recess is not particularly limited, and wet etching or the like can be applied in addition to laser processing such as excimer laser, carbon dioxide laser, and YAG laser.

  Next, a frame base material 37 with an adhesive 36 obtained by punching a predetermined portion (opening portion 5) as a second insulating base by punching or the like is bonded to the wiring pattern surface (FIG. 18d). Here, if the thickness of the polyimide layer of the two-layer flexible base material is 25 μm, the thickness of the polyimide film to be bonded needs to be about 50 to 70 μm in consideration of fixing to the frame in a later step. Note that the region to which the polyimide is bonded is not particularly limited, and an external connection terminal can be formed below the semiconductor chip like a CSP by providing the region where the semiconductor chip is mounted. Specifically, when the chip mounting is a wire bonding method, a polyimide film may be bonded to all other regions as long as the wire bonding terminal portion 38 is exposed. The insulating substrate thus obtained is separated into individual wiring patterns (FIG. 18e) and fixed to a separately prepared frame 43 such as SUS (FIG. 18f). Next, the semiconductor chip 39 is mounted, and the semiconductor chip and the wiring pattern are electrically connected by the gold wire 40 (FIG. 18g). On the other hand, when the face-down method is adopted as the semiconductor chip mounting method, a metal bump or the like is provided at a predetermined position of the wiring pattern (corresponding to the position of the external connection electrode of the semiconductor chip), and the semiconductor chip and the wavy line through the metal bump. The pattern may be electrically connected. Next, it is set in a mold for transfer molding and sealed with a resin sealing material 41 (FIG. 18h). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. Next, the connection part 12 with an external substrate is formed. As a method for forming the connection portion 12, a method of forming a bump larger than the thickness of the polyimide film by electrolytic plating in advance after the step of FIG. Is possible. Finally, the package is cut from the frame to obtain the desired package (FIG. 18i).

The fifteenth reference example of FIG. 18 will be described more specifically.

Example 2
Dry film resist (manufactured by Hitachi Chemical Co., Ltd.) on the copper foil surface of a two-layer flexible substrate (manufactured by Hitachi Chemical Co., Ltd., trade name: MCF 5000I) having a 12 μm thick electrolytic copper foil on one side Name: Photec HK815) was laminated, and a desired resist pattern was obtained by exposure and development. Next, after etching the copper foil with a ferric chloride solution, a predetermined wiring pattern was obtained by peeling the resist pattern with a potassium hydroxide solution. Next, using an excimer laser processing machine (manufactured by Sumitomo Heavy Industries, Ltd., device name: INDEX200), a predetermined number of recesses (diameter 300 μm) reaching the back of the wiring pattern from the insulating substrate side are formed at a predetermined position. did. Excimer laser processing conditions are an energy density of 250 mJ / cm 2, a reduction ratio of 3.0, an oscillation frequency of 200 Hz, and an irradiation pulse number of 300 pulses. Next, an adhesive sheet having a polyimide adhesive material (product name: AS 2250, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 10 μm on one side of a polyimide film (product name: UPILEX S) having a thickness of 50 μm is provided. The predetermined region including the region corresponding to the wire bond terminal portion in the subsequent process was removed by punching, and the polyimide film and the two-layer flexible substrate with a wiring pattern were heat-pressed through an adhesive. The pressure bonding conditions are a pressure of 20 kgf / cm 2, a temperature of 180 ° C., and a heating and pressing time of 60 minutes. Next, nickel / gold plating was applied to the terminal portion for wire bonding by electroless nickel and gold plating. The plating thickness is 3 μm and 0.3 μm, respectively. The substrate thus obtained was separated into individual wiring patterns and fixed to a separately prepared SUS frame. Next, a semiconductor chip was mounted using a die bond material for mounting a semiconductor chip (trade name: HM-1 manufactured by Hitachi Chemical Co., Ltd.). The mounting conditions are a press pressure of 5 kgf / cm 2, an adhesive temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external electrode portion of the semiconductor chip and the wiring pattern were electrically connected by wire bonding. After that, the die is processed into a lead frame shape, set in a transfer mold, and sealed with epoxy resin for semiconductor encapsulation (CL-7700, manufactured by Hitachi Chemical Co., Ltd.) at 185 ° C for 90 seconds. did. Subsequently, a predetermined amount of solder was printed and applied to the recesses described above, and the solder was melted in an infrared reflow furnace to form external connection bumps. Finally, the package part was punched with a mold to obtain a desired package.

A sixteenth reference example of the present invention will be described with reference to FIGS.

  A plurality of sets of predetermined wiring patterns 52 are formed on the support 51 (FIG. 19a). As the support, in addition to a metal foil such as an electrolytic copper foil, an insulating substrate such as a polyimide film can be applied. There are two methods for applying an insulating substrate. The first method is a method in which a non-penetrating recess reaching the wiring pattern is formed in a predetermined portion of the insulating substrate, and an external connection terminal is formed in an exposed portion of the wiring pattern. The non-penetrating recess can be formed by applying an excimer laser, a carbon dioxide gas laser, or the like. The second method is a method in which a drilled material is formed in advance on an insulating base material with an adhesive, and after being laminated with an electrolytic copper foil or the like, the copper foil is etched.

  On the other hand, when applying a metal foil, a resist pattern is first formed using a photoresist or the like, and then a wiring pattern is formed by electroplating using the metal foil as a cathode. In this case, a normal electrolytic copper foil or a thin layer of metal (nickel, gold, solder, etc.) having different chemical etching conditions from the copper foil can be applied. Also, copper is preferable as the wiring pattern. However, when the electrolytic copper foil is applied as a support as described above, a metal itself having a different etching condition from the copper foil can be applied as the wiring pattern, or copper foil etching can be performed. It is necessary to form a pattern thin layer to be a barrier layer at the time before pattern copper plating.

  Next, after mounting the semiconductor element 54 with the die bond material 53, the semiconductor element terminal and the wiring pattern are electrically connected (FIG. 19b), and a plurality of sets of semiconductor elements and the wiring pattern are collectively collected by a transfer molding method. It seals with the sealing material 56 (FIG. 19c). The resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied. The present invention is not limited to the case where the semiconductor element mounting method is the face-up method, and can be applied to, for example, the face-down method. Specifically, after forming a bump for face down bonding at a predetermined position on the wiring pattern 52 by plating or the like, the external connection portion of the semiconductor element and the bump may be electrically connected.

  Furthermore, it is effective to make it easy to divide the package in a later process as shown in FIGS. Of these, FIG. 20 shows a case in which a groove 59 is formed at a boundary portion between a plurality of package portions. The width and depth of the grooves can be controlled by the processing dimensions of the transfer mold. In FIG. 21, transfer molding is performed using a lattice-shaped intermediate plate 60 in which portions corresponding to the respective package portions are cut out in advance. Next, when the support is a metal foil, the support is removed by a chemical etching method or the like, and external connection terminals 57 are formed at predetermined positions (FIG. 19d). When an insulating base material is applied as the support, only a predetermined portion of the insulating base material may be selectively removed with a laser or the like as described above. Finally, the collectively sealed substrate is cut and separated into unit portions 58. A solder resist layer may be formed on the exposed surface of the wiring pattern for the purpose of protecting the wiring pattern.

The sixteenth reference example will be specifically described.

Example 3
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN640) is laminated on the shiny surface of an electrolytic copper foil with a thickness of 35 μm and an outer shape of 250 mm square, and the desired resist pattern (minimum) by exposure and development. Line / space = 50 μm / 50 μm). Next, 300 identical wiring patterns (4 blocks / 250 mm square, 75 blocks / block) composed of 0.2 μm thick nickel, 30 μm copper, 5 μm nickel and 1 μm soft gold by electroplating Formed. Next, the resist pattern is peeled off using a potassium hydroxide solution with a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, cut into blocks, and die bond material for mounting semiconductor elements (Hitachi Chemical Industry ( A semiconductor element was bonded using a product name: HM-1). The bonding conditions are a press pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external terminal of the semiconductor element and the gold plating terminal portion (second connection portion) are electrically connected by wire bonding, and then set in a transfer mold, and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industry ( Co., Ltd., trade name: CL-7700), 75 wiring patterns (corresponding to 1 block) were collectively sealed at 185 ° C for 90 seconds to transfer each wiring pattern into the sealing material. . Next, a desired portion of the electrolytic copper foil was removed by etching using an alkaline etchant (Meltex Co., Ltd., trade name: A process). The temperature of the etching solution is 40 ° C. and the spray pressure is 1.2 kgf / cm 2. Next, a solder pattern was formed on the external connection terminal portion by a printing method, and the solder was melted by an infrared reflow furnace to form an external connection bump. Finally, the desired package was obtained by separating into each package part with a diamond cutter.

Example 4
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN640) is laminated on the shiny surface of an electrolytic copper foil with a thickness of 35 μm and an outer shape of 250 mm square, and the desired resist pattern (minimum) by exposure and development. Line / space = 50 μm / 50 μm). Next, 300 identical wiring patterns (4 blocks / 250 mm square, 75 blocks / block) composed of 0.2 μm thick nickel, 30 μm copper, 5 μm nickel and 1 μm soft gold by electroplating Formed. Next, the resist pattern is peeled off using a potassium hydroxide solution with a liquid temperature of 35 ° C. and a concentration of 3 wt%, dried at 85 ° C. for 15 minutes, cut into blocks, and die bond material for mounting semiconductor elements (Hitachi Chemical Industry ( A semiconductor element was bonded using a product name: HM-1). The bonding conditions are a press pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external terminal of the semiconductor element and the gold plating terminal part (second connection part) were electrically connected by wire bonding. Next, a lattice-shaped stainless steel plate cut out of the part corresponding to the package area (15mm square) is set as an intermediate plate in a transfer mold, and an epoxy resin for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) was used to collectively seal 75 wiring patterns (corresponding to one block) at 185 ° C. for 90 seconds, thereby transferring each wiring pattern into the sealing material. The lattice portion of the intermediate plate has a 12 ° taper so that each package can be easily separated from the intermediate plate. Next, a desired portion of the electrolytic copper foil was removed by etching using an alkaline etchant (Meltex Co., Ltd., trade name: A process). Each package part is held by a grid-like intermediate plate. The temperature of the etching solution is 40 ° C. and the spray pressure is 1.2 kgf / cm 2. Finally, a solder pattern is formed on the external connection terminal portion by a printing method, solder is melted by an infrared reflow furnace to form external connection bumps, and the desired package is obtained by separating the intermediate plate into each package portion. .

A seventeenth reference example of the present invention will be described with reference to FIG.

  A plurality of sets of predetermined resist patterns 62 (FIG. 22b) are formed on the conductive temporary support 61 (FIG. 22a). Next, a wiring pattern 63 is formed on the exposed portion of the temporary support by electroplating. In this case, the temporary support is not particularly limited. For example, a thin layer of a metal (nickel, gold, solder, etc.) having different chemical etching conditions from a copper foil is provided on a normal electrolytic copper foil or electrolytic copper foil. Can be applied. Moreover, although copper is preferable as the wiring pattern, when the electrolytic copper foil is applied as a temporary support as described above, a metal itself having a different etching condition from the copper foil may be applied as the wiring pattern, or the copper foil. It is necessary to form a pattern thin layer to be a barrier layer during etching before pattern copper plating. The thickness of the temporary support is not particularly limited as long as there is no problem in terms of handling properties in a later process and dimensional stability when mounting a semiconductor element. Next, after plating with gold wire bonding (usually nickel / gold) 64 using the temporary support as a cathode, the resist pattern is removed (FIG. 22c). The present invention is not limited to the case where the semiconductor element mounting method is the face-up method, and can be applied to, for example, the face-down method. Specifically, after forming a bump for face down bonding at a predetermined position on the wiring pattern 63 by plating or the like, the external connection portion of the semiconductor element and the bump may be electrically connected.

  Next, the semiconductor element 65 is bonded with a die bond material 66 or the like, and the external connection terminal of the semiconductor element and the wiring pattern are electrically connected (FIG. 22d). Next, it is set in a transfer mold and sealed with a resin sealing material 68 (FIG. 22e). In this case, the resin sealing material is not particularly limited, and for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% can be applied.

  Next, a predetermined metal pattern 69 is formed at a location corresponding to the external connection terminal (FIG. 22f). In this case, the metal to be applied may be any metal that is not etched under the conditions for removing the conductive temporary support by etching. For example, solder, gold, nickel / gold, or the like is applicable. Moreover, as a formation method of a metal pattern, a well-known electroplating method, a solder printing method, etc. are applicable. Furthermore, when the metal pattern 69 is formed by a solder pattern, the solder bump 70 can be formed by reflowing. In this case, the height of the solder bump 70 after reflow can be controlled by adjusting the thickness of the pattern 69. Next, a predetermined portion of the temporary support is removed using the metal pattern as an etching resist to expose the wiring pattern.

  Finally, each package 71 is divided by applying die processing or dicing processing (FIG. 22g). If the exposed wiring pattern is not protected by a corrosion-resistant metal such as nickel, the region other than the external connection terminal portion may be covered with a known solder resist or the like. In addition, when solder is applied as a metal pattern, the reflow process is not particularly limited, and may be performed before or after being divided into packages, or may be performed when each package is mounted on an external wiring board. good.

The seventeenth reference example will be specifically described.

Example 5
A photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN640) is laminated on the shiny surface of an electrolytic copper foil with a thickness of 70 μm, and the desired resist pattern (minimum line / space = 50 μm / 50 μm). Next, a wiring pattern composed of nickel having a thickness of 0.2 μm, copper having a thickness of 30 μm, nickel having a thickness of 5 μm, and soft gold having a thickness of 1 μm was formed by electroplating. Next, the resist pattern is peeled off using a potassium hydroxide solution with a liquid temperature of 35 ° C and a concentration of 3wt%, dried at 85 ° C for 15 minutes, and then a die bond material for mounting semiconductor elements (manufactured by Hitachi Chemical Co., Ltd., trade name) : HM-1) was used to bond the semiconductor elements. The bonding conditions are a press pressure of 5 kg / cm 2, a temperature of 380 ° C., and a pressing time of 5 seconds. Next, the external terminal of the semiconductor element and the gold plating terminal portion (second connection portion) are electrically connected by wire bonding, and then set in a transfer mold, and an epoxy resin for semiconductor encapsulation (Hitachi Chemical Industry ( The wiring pattern was transferred into the encapsulant by sealing at 185 ° C. for 90 seconds using a product name, CL-7700, manufactured by Co., Ltd. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated on the electrolytic copper foil, and after forming a desired resist pattern by exposure and development, the thickness is obtained by electroplating. A 40 μm solder pad (diameter 0.3 mmφ, arrangement pitch 1.0 mm) was formed. Next, after peeling off the dry film resist, a desired portion of the electrolytic copper foil was removed by etching using an alkali etchant (Meltex Co., Ltd., trade name: A process). The temperature of the etching solution is 40 ° C. and the spray pressure is 1.2 kgf / cm 2. Finally, solder was melted in an infrared reflow furnace to form external connection bumps.

The eighteenth reference example of the present invention will be described with reference to FIGS.

  The configuration of the semiconductor mounting frame will be described with reference to FIG. Reference numeral 89 denotes a semiconductor mounting substrate, which is composed of an insulating base material and wiring. A plurality of substrates are connected via the substrate portion and the connecting portion 90. A reference position pin hole 91 is formed in the connecting portion 90. Instead of the pin hole 91, a recognition mark or the like used for image recognition may be used. In the post-process, the position is determined based on these reference positions. In particular, when a semiconductor is molded with a resin, alignment is performed by placing a pin in the cavity into the pin hole 91.

Further description will be made with reference to FIGS. A nickel layer (not shown in FIGS. 24 and 25) having a thickness of 0.001 mm was formed by electrolytic plating on one surface of an electrolytic copper foil 81 having a thickness of about 0.070 mm, which was a conductive temporary substrate. Next, a photosensitive dry film resist (manufactured by Hitachi Chemical Co., Ltd., trade name: Photec HN340) is laminated, and a plurality of sets of wiring pattern plating resists are formed by exposure and development. The exposure amount at this time is 70 mJ / cm2. Further, electrolytic copper plating is performed in a known copper sulfate bath, the resist is peeled off, and a plurality of sets of wirings 82 are formed (FIGS. 24a and 25a). Here, it is also conceivable to form the plated copper 82 'at the junction as shown in Fig. 25a, it is possible to further increase the rigidity of the frame thereby finished. The configurations shown in FIGS. 24a and 25a can also be obtained by preparing a base material composed of three layers of copper / nickel thin layer / copper in advance and forming a wiring on one copper foil by a normal etching process. The copper foil 81 / nickel thin layer (not shown) / copper wiring 82 (and 82 ') obtained here is composed of a copper foil / nickel wiring, nickel foil / copper wiring, etc., which has no nickel thin layer. A layer structure may be used. That is, the selection of the metal type is not limited to the type of this reference example, but when the part of the temporary substrate is removed by etching (FIGS. 24c and 25c) in the subsequent process, the wiring is selectively selected. Being able to remain is a suitable selection criterion. Further, the conductive temporary substrate is preferably a thick material because it becomes a constituent material of the connecting portion of the frame. However, since there is a step of removing a part of the conductive temporary substrate later, it is necessary to select an appropriate thickness. Although the thickness of the conductive temporary substrate depends on the material, for example, when using copper foil, about 0.03 to 0.3 mm is preferable. Next, a polyimide adhesive 83 was bonded to the wiring surface of the copper foil 81 on which a plurality of sets of wirings 82 were formed. Here, the polyimide adhesive 83 is not limited to this material. For example, an epoxy adhesive film, a film obtained by applying an adhesive to a polyimide film, or the like can be used. Next, an external connection terminal hole 84 was formed using an excimer laser (FIGS. 24b and 25b). In order to simplify the process in the subsequent process, it is preferable to provide the connection terminal before mounting the semiconductor. As another method for forming the hole 84, a method may be used in which the external connection terminal hole 84 is formed in the film in advance by drilling or punching, and the film is adhered. Further, the hole 84 may be filled with a metal such as solder (corresponding to 88 in FIGS. 24f and 25f) used as a connection terminal. However, in the subsequent semiconductor mounting process and resin sealing process, The metal protrusion may become an obstacle, and it is preferable to form in a later step. The external connection terminal holes (or terminals) of the semiconductor element mounting substrate are preferably arranged in an array on the opposite side of the semiconductor element mounting.

Next, a part of the electrolytic copper foil, which is a temporary substrate where the wiring pattern is formed, was removed by etching. As the etching solution, in the case of the configuration of this reference example, it is preferable to select an etching solution and an etching condition in which the dissolution rate of copper is significantly higher than that of nickel. In this reference example, an alkali etchant (manufactured by Meltex Co., Ltd., trade name: A process) was used as the etching solution, and the etching conditions were, for example, a liquid temperature of 40 ° C. and a spray pressure of 1.2 kgf / cm 2. The types and conditions of the liquids shown here are only examples. This step exposes the nickel thin layer of the substrate portion. When etching only this thin nickel layer, it is preferable to select an etching solution and etching conditions in which the dissolution rate of nickel is significantly higher than that of copper. In this reference example, nickel etchant (Meltex Co., Ltd., trade name: Melstrip N950) was selectively etched away. The temperature of the etching solution was 40 ° C., and the spray pressure was 1.2 kgf / cm 2. The types and conditions of the liquid shown here are only examples. Through these steps, remain temporary substrate of the connecting portion, the semiconductor mounting frame having rigidity is obtained, et al. (FIG. 24c, FIG. 25c). In this reference example, the copper wiring terminal portion of this frame is subjected to electroless nickel-gold plating (not shown in the figure). This is necessary for wire bonding of the chip in a later process, and such surface treatment may be performed as necessary.

  Further, a semiconductor chip 85 is mounted. For bonding the semiconductor chip, a semiconductor die bonding tape 86 (for example, Hitachi Chemical Co., Ltd., trade name: HM-1) was used. Here, when there is no wiring under the chip, it may be bonded using a silver paste for die bonding. Next, the semiconductor terminal portion and the wiring are connected by a wire bond 100 (FIGS. 24d and 25d). The connection with the semiconductor terminal may be another method, for example, a Philip chip connection by face-down or an adhesion with an anisotropic conductive back agent. What was formed in this way was loaded into a transfer mold die, and sealed 87 using an epoxy resin for semiconductor sealing (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) (FIG. 24e, FIG. 25e). Thereafter, solder balls 88 are disposed in the connection holes provided in the connection terminal portions of the wiring 82 and melted (FIGS. 24f and 25f). The solder balls 88 serve as so-called external connection terminals. A plurality of semiconductor devices connected by the connecting portion 102 are punched out with a mold to obtain individual semiconductor devices (FIGS. 24g and 25g).

In this reference example, a frame with sufficient rigidity can be obtained by manufacturing a semiconductor device such as BGA and CSP using a film substrate such as a polyimide tape by using a semiconductor mounting frame and a semiconductor device manufacturing method. This makes it possible to manufacture a semiconductor device with high accuracy and efficiency.

  According to the present invention, it is possible to stably and stably manufacture a semiconductor package that can cope with high integration of semiconductor chips.

FIG. 1 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 2 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to the present invention. FIG. 4 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 5 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 6 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 7 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 8 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 9 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 10 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 11 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 12 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 13 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 14 is a plan view for explaining a reference example of a method for manufacturing a semiconductor package. FIG. 15 is a plan view for explaining a reference example of a method for manufacturing a semiconductor package. FIG. 16 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 17 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 18 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 19 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 20 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 21 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 22 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 23 is a plan view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 24 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package. FIG. 25 is a cross-sectional view illustrating a reference example of a method for manufacturing a semiconductor package.

Claims (3)

In a manufacturing method of a package using a wiring board having a temporary support,
Forming a first wiring on the substrate;
Forming an adhesive resin layer so as to cover the first wiring;
Forming a second wiring on the adhesive resin layer;
Mounting a semiconductor element on the substrate on which the first and second wirings are formed;
A step of resin-sealing the semiconductor element;
And a step of removing the temporary support. The temporary support is conductive,
2. The method of manufacturing a semiconductor package according to claim 1 , wherein the temporary support is removed by etching. The semiconductor package manufactured by the manufacturing method according to claim 1 or 2, wherein.

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