JPS60160624A - Dielectric isolation for semiconductor chip - Google Patents

Dielectric isolation for semiconductor chip

Info

Publication number
JPS60160624A
JPS60160624A JP1739984A JP1739984A JPS60160624A JP S60160624 A JPS60160624 A JP S60160624A JP 1739984 A JP1739984 A JP 1739984A JP 1739984 A JP1739984 A JP 1739984A JP S60160624 A JPS60160624 A JP S60160624A
Authority
JP
Japan
Prior art keywords
semiconductor chip
conductor
heat sink
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1739984A
Other languages
Japanese (ja)
Inventor
Hiroshi Ito
弘 伊藤
Masahiro Fukuzumi
福角　正裕
Hidekazu Awaji
淡路　英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1739984A priority Critical patent/JPS60160624A/en
Publication of JPS60160624A publication Critical patent/JPS60160624A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To realize stability to heat and impulse, and reduction in cost through easy assembling by loading a film piece to a substrate such as a heat sink and mounting a semiconductor chip to such film piece. CONSTITUTION:After forming a conductor 12 on a tape film 1 such as a polyimide by the method such as plating, vacuum deposition, sputtering or attachment of conductor, unwanted conductor part is removed by etching the conductor 12. The lower surface of tape film 1 is coated with a bonding agent 2. The bonding agent to be used must be selected from those which are aclyric or epoxy system, semi-hardened, and remelted and hardened when heated for actual use. The tape film is wound into a coil. A tape film 1 is punched and bonded on the heated lead frame and substrate 15 and then the connecting leads 17 such as die bonding and wire bonding, etc. are assembled.

Description

【発明の詳細な説明】 く技術分野〉 本発明は、半導体チップの絶縁分離方法に係り、特に半
導体チップとリードフレーム、ヒートシンク等の基板と
を電気的に絶縁分離する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method for electrically insulating and separating a semiconductor chip, and more particularly to a method for electrically insulating and separating a semiconductor chip from a substrate such as a lead frame or a heat sink.

〈従来技術〉 従来、パワートランジスタ、トライアック等の半導体素
子をシートンンクに取付ける場合、第８図に示すように
半導体素子３０をヒートシンク３１に直接はんだ付けし
ている。しかし、この場合ヒートシンク３１には電圧が
印加されることになり、放熱板へ取付けると感電の危険
性があることから、第９図のようにマイカやテフロン等
の絶縁ソート３３をヒートシンク３１と放熱板３４との
間に挾み込み、ブラヌチックねじ３５でヒートシンクを
放熱板へ取付は絶縁する必要があった。また、このよう
な方法が採用できない場合は、第１０図のように電極を
形成したセラミンク基板３６をヒートシンク３１にはん
だ付けし、更にセラミック基板３６に半導体素子３０を
ダイボンデ、ｆングあるいはワイヤポンディングするこ
とによって、ヒートシンク３１と半導体素子３１間をセ
ラミック基板３６を用いて電気的に絶縁分離していた。<Prior Art> Conventionally, when attaching a semiconductor element such as a power transistor or a triac to a seat tank, the semiconductor element 30 is directly soldered to a heat sink 31 as shown in FIG. However, in this case, a voltage will be applied to the heat sink 31, and there is a risk of electric shock if it is attached to a heat sink. Therefore, as shown in Figure 9, an insulating material 33 such as mica or Teflon is used to connect the heat sink 31 with the heat sink. It was necessary to insulate the heat sink by inserting it between the heat sink and the plate 34 and attaching it to the heat dissipation plate using the Branutik screws 35. In addition, if such a method cannot be adopted, the ceramic substrate 36 on which electrodes are formed is soldered to the heat sink 31 as shown in FIG. By doing so, the heat sink 31 and the semiconductor element 31 are electrically insulated and separated using the ceramic substrate 36.

しかしながら、上述の方法はいずれも取付は組立てが煩
雑であり、かつコスト高となる欠点を有していた。However, all of the above-mentioned methods have the disadvantage that the assembly is complicated and the cost is high.

〈目　的〉 本発明は従来の欠点を除去するために々されたものであ
り、熱的にも衝撃にも安定であり取付は組立てが容易で
コストの低減が図れる半導体チップの絶縁分離方法を提
供することを目的とする。<Purpose> The present invention has been made in order to eliminate the drawbacks of the conventional method, and to provide a semiconductor chip insulation isolation method that is thermally and shock-resistant, easy to assemble, and reduces costs. The purpose is to provide.

〈実施例〉 第１図に示すように、ポリイミド、ポリアミド、テフロ
ン、エポキシ等の樹脂からなるフィルム片ＩＫ接着剤２
を塗布し、これをテープ状に定形化してヒートシンク上
に接着できるように構成する。<Example> As shown in FIG. 1, a film piece IK adhesive 2 made of resin such as polyimide, polyamide, Teflon, epoxy, etc.
This is formed into a tape shape so that it can be adhered onto a heat sink.

上記接着剤２は加熱によりヒートシンクに容易に接着し
、上記フィルム片１に半導体チップをダイボンデ、ボン
デするものである。この絶縁層であるフィルム片１は第
２図に示す如く自動化が容易であり、作業性の良好な形
成操作が可能である。図において、フィルム片を構成す
るテープ３は巻取ＩＪ　−／ｌ／　４及び供給リール５
に巻回され、裏面よりヒータ７により加熱されたヒート
シンク６に打ち抜きポンチ９を備えるプレス８を用いて
上記テープ３をヒートシンク６に加熱によシ圧着接続さ
せる。このようにして、第３図に示すようにヒートシン
ク６上にフィルム片１を介して半導体チップ１０がペー
ストを介して実装され、フィルム片１は半導体チップ１
０とヒートシンク６とを電気的に絶縁分離する。また、
パワートランジスタやトライアックに於ては、半導体チ
ップの底面から導通をとる必要があるため、ポリイミド
等のフィルム片１の上面に予め蒸着、スパッタリング、
メッキなどのメタライズ処理や金属箔の貼付などによっ
て電極１２を形成し、この電極上へペーストで半導体チ
ップ１０をダイボンディングする。パワーＩＣなどに於
ては、一般に、チップ底面からの導通は不要であるが、
従来、第１１図のようにパワーＩＣチップ３７とヒート
シンク３１との絶縁を絶縁ペーストでダイボンディング
していたが、絶縁性が不確実であるという欠点があった
。しかし、第３図の如く、フィルム片ｌを介在すること
によって絶縁性を確実なものとすることができる。The adhesive 2 easily adheres to the heat sink by heating, and is used to die-bond the semiconductor chip to the film piece 1. The film piece 1, which is an insulating layer, can be easily automated as shown in FIG. 2, and can be formed with good workability. In the figure, the tape 3 constituting the film piece is connected to a take-up IJ-/l/4 and a supply reel 5.
The tape 3 is heated and crimped onto the heat sink 6 using a press 8 equipped with a punch 9, which is wound around the heat sink 6 and heated from the back side by a heater 7. In this way, as shown in FIG. 3, the semiconductor chip 10 is mounted on the heat sink 6 through the film piece 1 and the paste, and the film piece 1 is attached to the semiconductor chip 10.
0 and the heat sink 6 are electrically insulated and separated. Also,
In power transistors and triacs, it is necessary to establish conduction from the bottom of the semiconductor chip, so the top surface of the film piece 1 made of polyimide or the like is preliminarily coated with evaporation, sputtering, etc.
The electrode 12 is formed by metallization processing such as plating or pasting of metal foil, and the semiconductor chip 10 is die-bonded onto this electrode using paste. In power ICs, conduction from the bottom of the chip is generally not necessary, but
Conventionally, as shown in FIG. 11, the insulation between the power IC chip 37 and the heat sink 31 has been die-bonded using an insulation paste, but this has the disadvantage that the insulation is uncertain. However, as shown in FIG. 3, insulation can be ensured by interposing a film piece l.

また、パワーデバイスに於て、動作時や加熱時、熱歪が
かなり発生し、半導体チップに悪影響を及ぼす。従来、
半導体チップ１０は樹脂モールド３９され、ヒートシン
ク６にはんだ３２で固着されており、かなりのストレス
を受ける（１２図）が、第５図のようにポリイミド等の
フィルム片１があると、このフィルム片１が緩衝作用を
有するため、ストレスを柔らげる。又フィルム片は熱的
に安定である。このほか、ハイブリッドＩＣ等に於て、
パワーチップとＩＣチップとの電気的分離にも有効であ
る。第６図は電極体のポリイミド層を貼付けた半導体装
置の断面図である。図において、１５は銅、Ｎｉメッキ
等の基板、１６はチップ抵抗、１７はワイヤポンド、１
８はパワーチップ、１９ははんだである。Further, in power devices, considerable thermal strain occurs during operation or heating, which adversely affects semiconductor chips. Conventionally,
The semiconductor chip 10 is resin-molded 39 and fixed to the heat sink 6 with solder 32, and is subjected to considerable stress (Fig. 12). However, if there is a film piece 1 made of polyimide or the like as shown in Fig. 5, this film piece Since 1 has a buffering effect, it relieves stress. The film pieces are also thermally stable. In addition, in hybrid IC, etc.
It is also effective for electrically separating a power chip and an IC chip. FIG. 6 is a sectional view of a semiconductor device to which a polyimide layer of an electrode body is attached. In the figure, 15 is a substrate made of copper or Ni plating, 16 is a chip resistor, 17 is a wire pounder, 1
8 is a power chip, and 19 is a solder.

次に製造方法を第７図に基づいて説明する。Next, the manufacturing method will be explained based on FIG. 7.

（１３ポリイミド等のテープフィルム１上にメッキ、蒸
着、スパッタリング、導体貼付等の既知の方法で導体１
２を形成する。(13) A conductor 1 is formed on a tape film 1 made of polyimide or the like by a known method such as plating, vapor deposition, sputtering, conductor pasting, etc.
form 2.

（２１導体１２をエツチングして不要な導体部分を除去
する。(21 Conductor 12 is etched to remove unnecessary conductor parts.

（３）　テープフィルム１の下面に接着剤２を塗布する
。接着剤はアクリル系、エポキシ系等のもので、半硬化
状態とし、使用に際して加熱することによシ、再溶融し
、硬化するものを選択する。(3) Apply adhesive 2 to the lower surface of tape film 1. The adhesive should be acrylic, epoxy, or the like, and should be in a semi-cured state and remelt and harden when heated during use.

上記テープフ−（／レムを巻取９コイル上にする。Wind the above tape roll onto the 9th coil.

（４）加熱したリードフレーム、基板１５上でテープフ
イｌｖ１を打ち抜き、接着させる。(4) Punch out the tape film lv1 on the heated lead frame and substrate 15 and adhere it.

（５）ダイボンディング、ワイヤボンデ、Ｃング等の接
続リード１７のアセンブリを行ない、完成品とする。(5) Assembly of the connection leads 17 by die bonding, wire bonding, C-ring, etc. is performed to produce a finished product.

〈効　果〉 以上説明した様に本発明によれば、ヒートシンク等の基
板にフィルム片を取着し、このフィルム片に半導体チッ
プを実装することにより、半導体チップと基板間の電気
的絶縁分離を行うようにしたから、熱的にも衝撃に対し
ても安定であり、取付け、組立てが容易で作業性が良好
で、かつコストの低減化を図ることができる。<Effects> As explained above, according to the present invention, a film piece is attached to a substrate such as a heat sink, and a semiconductor chip is mounted on this film piece, thereby achieving electrical insulation separation between the semiconductor chip and the substrate. By doing so, it is stable against heat and impact, easy to attach and assemble, and has good workability, and it is possible to reduce costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ないし第７図は本発明の半導体チップの絶縁分離
方法に係り、第１図はフィルム片構成の平面図、第２図
はフィルム片形成の工程を示す図、第３図は半導体チッ
プを載せたフィルム片をヒートシンクに取着する断面図
、第４図は他の実施例を示す図、第５図はパワーデバイ
スの説明に係る断面図、第６図は完成図、第７図は製造
工程を示す図であシ、また第８図ないし第１２図は従来
の方法に係り、第８図、第１０図、第１１図、第１２図
は一例を示す断面図、第９図はヒートシンク取付状態を
示す斜視図である。 符号の説明 １：フィルム片、　６，１５：基板、　１０：半導体チ
ップ 代理人　弁理士　福　士　愛　彦（他２名）第３　已 朶６図　１５1 to 7 relate to the insulating separation method for semiconductor chips of the present invention, in which FIG. 1 is a plan view of the structure of a film piece, FIG. 2 is a diagram showing the process of forming a film piece, and FIG. 3 is a semiconductor chip. FIG. 4 is a diagram showing another embodiment, FIG. 5 is a cross-sectional diagram for explaining the power device, FIG. 6 is a completed diagram, and FIG. 8 to 12 relate to the conventional method, FIGS. 8, 10, 11, and 12 are cross-sectional views showing an example, and FIG. 9 is a diagram showing the manufacturing process. FIG. 3 is a perspective view showing a state in which the heat sink is attached. Explanation of symbols 1: Film piece, 6, 15: Substrate, 10: Semiconductor chip agent, patent attorney Aihiko Fukushi (and 2 others) No. 3, Figure 6, 15

Claims (1)

【特許請求の範囲】 １、　接着層を有するポリイミド樹脂等の絶縁フィルム
片ヲリードフレーム、ヒートシンク等の基板に取着し、
上記絶縁フィルム片に半導体チップを実装することによ
り、上記半導体チップとと８ 上記基板間＠電気的に分離し絶縁を行うようにしたこと
を特徴とする半導体チップの絶縁分離゛　方法。 ２　絶縁フィルム片が電極取出し用の導体をもつ特許請
求の範囲第１項記載の半導体チップの絶縁分離方法。[Claims] 1. A piece of insulating film made of polyimide resin or the like having an adhesive layer is attached to a substrate such as a lead frame or a heat sink,
A method for insulating and separating a semiconductor chip, characterized in that the semiconductor chip and the substrate are electrically separated and insulated by mounting the semiconductor chip on the insulating film piece. 2. The method for insulating and separating semiconductor chips according to claim 1, wherein the insulating film piece has a conductor for taking out an electrode.
JP1739984A 1984-01-31 1984-01-31 Dielectric isolation for semiconductor chip Pending JPS60160624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1739984A JPS60160624A (en) 1984-01-31 1984-01-31 Dielectric isolation for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1739984A JPS60160624A (en) 1984-01-31 1984-01-31 Dielectric isolation for semiconductor chip

Publications (1)

Publication Number Publication Date
JPS60160624A true JPS60160624A (en) 1985-08-22

Family

ID=11942913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1739984A Pending JPS60160624A (en) 1984-01-31 1984-01-31 Dielectric isolation for semiconductor chip

Country Status (1)

Country Link
JP (1) JPS60160624A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110858A (en) * 1994-03-18 2002-04-12 Hitachi Chem Co Ltd Semiconductor package and its manufacturing method
JP2002334948A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package, substrate for semiconductor element mounting and method of manufacturing them
JP2002334951A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Substrate for semiconductor element mounting and semiconductor package
JP2002334950A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Method of manufacturing semiconductor package and semiconductor package
JP2002334949A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package and method of manufacturing substrate for semiconductor element mounting
US6746897B2 (en) 1994-03-18 2004-06-08 Naoki Fukutomi Fabrication process of semiconductor package and semiconductor package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110858A (en) * 1994-03-18 2002-04-12 Hitachi Chem Co Ltd Semiconductor package and its manufacturing method
JP2002334948A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package, substrate for semiconductor element mounting and method of manufacturing them
JP2002334951A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Substrate for semiconductor element mounting and semiconductor package
JP2002334950A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Method of manufacturing semiconductor package and semiconductor package
JP2002334949A (en) * 1994-03-18 2002-11-22 Hitachi Chem Co Ltd Semiconductor package and method of manufacturing substrate for semiconductor element mounting
US6746897B2 (en) 1994-03-18 2004-06-08 Naoki Fukutomi Fabrication process of semiconductor package and semiconductor package
US7187072B2 (en) 1994-03-18 2007-03-06 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package

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