JPS63284831A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS63284831A
JPS63284831A JP62120378A JP12037887A JPS63284831A JP S63284831 A JPS63284831 A JP S63284831A JP 62120378 A JP62120378 A JP 62120378A JP 12037887 A JP12037887 A JP 12037887A JP S63284831 A JPS63284831 A JP S63284831A
Authority
JP
Japan
Prior art keywords
conductor pattern
component mounting
paste
bonding
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62120378A
Other languages
Japanese (ja)
Inventor
Akira Honda
晃 本多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Inter Electronics Corp
Original Assignee
Nihon Inter Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Inter Electronics Corp filed Critical Nihon Inter Electronics Corp
Priority to JP62120378A priority Critical patent/JPS63284831A/en
Publication of JPS63284831A publication Critical patent/JPS63284831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To employ an economical Cu foil as an outermost layer of a conductor pattern of a component mounting substrate by reinforcing a position where a wire is directly bonded to a conductor pattern with Ag paste. CONSTITUTION:An insulating layer 1b is formed on a metal board 1a and a wiring conductor pattern 2 for forming a required circuit is formed on the insulating layer 1b. The material of the conductor pattern 2 is a Cu foil. A semiconductor chip 3 is mounted on a component mounting substrate 1 with a heat spreader 5 in between and fixed with solder. One end of a metal fine wire 6 made of Al is bonded to an electrode metal 4 on the upper surface of the semiconductor chip 3 by ultrasonic welding and the other end of the metal fine wire 6 is directly bonded to the conductor pattern 2 of the component mounting substrate 1 at a predetermined position by ultrasonic welding to form a bonding position 7. Then Ag paste 8 is applied so as to surround the bonding position 7. The Ag paste 8 applied to the bonding position 7 serves as the reinforcing material of the bonding position 7.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は混成集積回路（以下、ＨＩＣと略記する。）
の製造方法に関し、特に基板上に搭載する半導体チップ
と導体パターン間の金属細線によるワイヤボンディング
部を補強し、断線事故等の発生率を低下さることにより
信頼性を向上させたＨＩＣの製造方法に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a hybrid integrated circuit (hereinafter abbreviated as HIC).
In particular, this invention relates to a method for manufacturing an HIC that improves reliability by reinforcing the wire bonding part using thin metal wires between a semiconductor chip mounted on a board and a conductor pattern, and reducing the incidence of disconnection accidents. It is something.

［従来の技術］ 従来のこの種のＨＩＣの製造方法を第２図を参照して説
明する。[Prior Art] A conventional method for manufacturing this type of HIC will be described with reference to FIG.

第２図において、部品搭載用基板１は絶縁物、例えば樹
脂系若しくはセラミック系の材料で形成しても良く、ま
た放熱性を考慮して基板自体をアルミニューム（ＡＩ）
、銅（Ｃｕ）等の金属板で形成し、その表面に絶縁層を
介して所定の導体パターン２を形成したものでも良い。In FIG. 2, the component mounting board 1 may be formed of an insulator, such as a resin or ceramic material, or the board itself may be made of aluminum (AI) in consideration of heat dissipation.
It may be formed of a metal plate such as copper (Cu), and a predetermined conductor pattern 2 may be formed on the surface thereof with an insulating layer interposed therebetween.

上記のように構成された部品搭載用基板ｌの導体パター
ン２は、上には表面実装部品が適当なソルダにより固着
され、所定の回路が形成される。On the conductor pattern 2 of the component mounting board 1 constructed as described above, surface mount components are fixed with a suitable solder to form a predetermined circuit.

ところで、通常の表面実装部品であれば、導体パターン
２の所定の位置に直接ソルダ付けすることにより接続が
なされるが、第２図に示すような半導体チップ３の場合
には、ヒートスプレッダ５を介して導体パターン２上に
固着された後、導体パターン２と当該半導体チップ３の
上表面の電極金属４とをＡＩ製の金属細線６でワイヤボ
ンディングする。Incidentally, in the case of ordinary surface mount components, connection is made by directly soldering to a predetermined position of the conductor pattern 2, but in the case of a semiconductor chip 3 as shown in FIG. After the conductor pattern 2 is fixed onto the conductor pattern 2, the conductor pattern 2 and the electrode metal 4 on the upper surface of the semiconductor chip 3 are wire-bonded using a thin metal wire 6 made of AI.

なお、上記のヒートスプレッダ５は半導体チップ３から
の発熱を効率良く外部へ放散させるために介在させるも
のである。また、上記の導体パターン２は、ＡＩ製の金
属細線６との溶接強度を向上させるため、その表面には
Ａ１層若しくはＮｉ層が形成されている。The heat spreader 5 described above is provided to efficiently dissipate heat generated from the semiconductor chip 3 to the outside. Moreover, in order to improve the welding strength with the thin metal wire 6 made of AI, the conductor pattern 2 has an A1 layer or a Ni layer formed on its surface.

上記のＡ１層若しくはＮｉ層の下側は、一般に銅（Ｃｕ
）層が形成されている。The underside of the above A1 layer or Ni layer is generally copper (Cu).
) layers are formed.

また、上記第２図では半導体チップ３以外の搭載部品に
ついては図示を省略しである。Further, in FIG. 2, mounting components other than the semiconductor chip 3 are not shown.

［発明が解決しようとする問題点］ 従来のＨＩＣの製造方法は、導体パターンの最外層とな
る部分に表面がＡ１層若しくはＮｉ層を形成しであるた
めに、部品搭載用基板１自体が高価なものとなり、ＨＩ
Ｃ自体の製造原価を高騰させるという問題点があった。[Problems to be Solved by the Invention] In the conventional HIC manufacturing method, the A1 layer or Ni layer is formed on the surface of the outermost layer of the conductor pattern, so the component mounting board 1 itself is expensive. Become something, HI
There was a problem in that the manufacturing cost of C itself rose.

また、導体パターン２の表面は、一般に半導体チップ３
の表面に比較して表面平坦度等、その表面状態が悪く、
そのため超音波溶接による強度にばらつきが生じ、信頼
性に欠けるという問題点があフた。Further, the surface of the conductor pattern 2 is generally covered with a semiconductor chip 3.
The surface condition, such as surface flatness, is poor compared to the surface of
As a result, the problem that ultrasonic welding caused variations in strength and lacked reliability was resolved.

［発明の目的］ この発明は上記のような問題点を解消するためになされ
たもので、部品搭載用基板自体を安価に製作し得るとと
もに、金属細線と導体パターンとのボンディング箇所の
接続強度を高く、かつ、その強度にばらつきを生じるこ
とも少なくなくし、信頼性の高いＨＩＣが得られるよう
にしたＨＩＣの製造方法を提供することを目的とする。[Purpose of the Invention] This invention was made to solve the above-mentioned problems, and it is possible to manufacture the component mounting board itself at low cost, and to improve the connection strength at the bonding point between the thin metal wire and the conductor pattern. It is an object of the present invention to provide a method for manufacturing an HIC that is high in strength, does not infrequently cause variations in strength, and is capable of obtaining a highly reliable HIC.

［問題点を解決するための手段］ この発明のＨＩＣの製造方法は、部品搭載用基板上の導
体パターン自体は、銅箔により形成し、金属細線と導体
パターンとを超音波ボンディングした後に、そのボンデ
ィング箇所を包囲するように銀ペーストを塗布して硬化
させる。[Means for Solving the Problems] In the HIC manufacturing method of the present invention, the conductor pattern itself on the component mounting board is formed of copper foil, and after ultrasonic bonding of the thin metal wire and the conductor pattern, Apply silver paste to surround the bonding area and harden.

［作用］ この発明のＨＩＣの製造方法においては、金属細線と導
体パターンとのボンディング箇所を導電性の銀ペースト
で包囲し、その銀ペーストを硬化させて固着することに
より金属細線の導体パターンに対するワイヤボンディン
グ箇所の溶接強度が補強される。[Function] In the HIC manufacturing method of the present invention, the bonding location between the thin metal wire and the conductor pattern is surrounded by a conductive silver paste, and the silver paste is hardened and fixed, thereby bonding the wire to the conductor pattern of the thin metal wire. The welding strength at the bonding point is reinforced.

一方、部品搭載用基板の導電パターンの最外層は、Ａ１
層若しくはＮｉ層である必要はなく、より安価なＣｕ箔
を使用することができる。On the other hand, the outermost layer of the conductive pattern on the component mounting board is A1
layer or Ni layer, a cheaper Cu foil can be used.

Ｃｕ箔は上記のＡ１層若しくはＮｉ層に比べて溶接強度
の信頼性が若干力るが、金属細線のボンディング箇所に
銀ペーストを塗布して硬化させることによりその強度を
十分補強することができる。Cu foil has a slightly less reliable welding strength than the above-mentioned A1 layer or Ni layer, but its strength can be sufficiently reinforced by applying silver paste to the bonding location of the thin metal wire and curing it.

［実施例］ 以下に、この発明の一実施例を第１図に基づいて説明す
る。[Example] An example of the present invention will be described below based on FIG. 1.

図において、１は部品搭載用基板であり、この部品搭載
用基板１０基体となる部分は、この実施例では放熱性を
良くするためにＡＩ若しくはＣｕ製の金属板１ａとした
が、全体を絶縁物としても良い。In the figure, 1 is a component mounting board, and the part that becomes the base of this component mounting board 10 is a metal plate 1a made of AI or Cu in order to improve heat dissipation in this embodiment, but the whole is insulated. It can also be used as an object.

この実施例では金属板ｌａ上に、絶縁層１ｂを形成する
。そして絶縁層ｌｂ上、所定回路を構成するための配線
用の導体パターン２が形成される。In this embodiment, an insulating layer 1b is formed on a metal plate la. Then, on the insulating layer lb, a conductive pattern 2 for wiring to constitute a predetermined circuit is formed.

この導体パターン２の材質はＣｕ箔であり、従来のよう
に、その表面にＡ１層若しくはＮｉ層を形成する必要が
なく、そのため、部品搭載用基板１を極めて安価に製作
することが可能となる。The material of the conductive pattern 2 is Cu foil, and there is no need to form an A1 layer or a Ni layer on the surface as in the conventional case, and therefore the component mounting board 1 can be manufactured at an extremely low cost. .

上記の部品搭載用基板１上に半導体チップ３が、ヒート
スプレッダ５を介して搭載され、適当なソルダを介して
固着される。上記半導体チップ３の上面の電極金属４に
は、ＡＩ製の金属細線６の一端を超音波溶接により固着
する。上記金属細線６の他端は部品搭載用基板ｌの導体
パターン２の所定の位置に直接、超音波溶接し、ボンデ
ィング部箇所７が形成される。A semiconductor chip 3 is mounted on the above component mounting substrate 1 via a heat spreader 5 and fixed via a suitable solder. One end of a thin metal wire 6 made of AI is fixed to the electrode metal 4 on the upper surface of the semiconductor chip 3 by ultrasonic welding. The other end of the thin metal wire 6 is directly ultrasonically welded to a predetermined position of the conductor pattern 2 of the component mounting board 1 to form a bonding portion 7.

次いで、上記ボンディング箇所７を包囲するようにＡｇ
ペースト８を塗布する。Next, Ag is applied so as to surround the bonding location 7.
Apply paste 8.

上記のＡｇペースト８は、例えば、アミコン株式会社製
；商品名「アミコン」を使用し、これは熱硬化型の一液
性エボキシ樹脂の中に、Ａｇの微粒子を混合させて導電
性を持たせたもので、接着材としての役割を持つもので
ある。The above-mentioned Ag paste 8 is manufactured by Amicon Co., Ltd.; trade name "Amicon" is used, and this is made by mixing Ag fine particles into a thermosetting one-component epoxy resin to give it conductivity. It has a role as an adhesive.

上記のようにボンディング箇所に塗布したＡｇペースト
８は、例えば１５０℃で約３０分間加熱することにより
硬化し、ボンディング箇所７の補強材としての役割を果
たすこととなる。The Ag paste 8 applied to the bonding location as described above is cured by heating, for example, at 150° C. for about 30 minutes, and serves as a reinforcing material for the bonding location 7.

［発明の効果］ 以上のように、この発明によれば上記のように構成した
ので、概略以下のような効果を奏する。[Effects of the Invention] As described above, according to the present invention, the above configuration provides the following effects.

（１）部品搭載用基板上に形成する導体パターンを、従
来のようにＡ１層若しくはＮｉ層とすることなくＣｕ箔
にて形成することができるので、極めて安価な部品搭載
用基板となり、この種のＨＩＣの製造原価を低減するこ
とができる。(1) Since the conductor pattern formed on the component mounting board can be formed with Cu foil instead of using the A1 layer or Ni layer as in the conventional case, it becomes an extremely inexpensive component mounting board, and this type of The manufacturing cost of HIC can be reduced.

（２）導体パターン上に直接ワイヤボンディングした箇
所を、そのボンディング箇所を包囲するように塗布して
硬化させたＡｇペーストにより補強するようにしたので
、金属細線の剥離、断線、等の発生確率が極端に減少し
、そのため製作されたＨＩＣの信頼性を著しく向上させ
ることができる。(2) The area where wire bonding is performed directly on the conductor pattern is reinforced with Ag paste that is applied and hardened to surround the bonding area, reducing the probability of peeling off, disconnection, etc. of the thin metal wire. can be significantly reduced, thereby significantly improving the reliability of the fabricated HIC.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明のＨＩＣの製造方法を説明するための
斜視図、第２図は従来のＨＩＣの製造方法を説明するた
めの斜視図である。 １・・・部品搭載用基板 １ａ・・・金属板 ｌｂ・・・絶縁層 ２・・・導体パターン ３・・・半導体チップ ４・・・電極金属 ５・・・ヒートスプレッダ ６・・・金属細線 ７・・・ボンディング箇所 ８・・・ＡｇペーストFIG. 1 is a perspective view for explaining the HIC manufacturing method of the present invention, and FIG. 2 is a perspective view for explaining the conventional HIC manufacturing method. 1... Component mounting board 1a... Metal plate lb... Insulating layer 2... Conductor pattern 3... Semiconductor chip 4... Electrode metal 5... Heat spreader 6... Metal thin wire 7 ...Bonding point 8...Ag paste

Claims (1)

【特許請求の範囲】 １、電子部品搭載用基板上に形成された所定の導体パタ
ーンを有し、この導体パターンの表面に金属細線を超音
波ボンディングした後に、そのボンディングした部分を
包囲するように固着材で補強したことを特徴とする混成
集積回路の製造方法。 ２、前記固着材が銀ペーストであることを特徴とする特
許請求の範囲第１項に記載の混成集積回路の製造方法。[Claims] 1. It has a predetermined conductor pattern formed on a substrate for mounting electronic components, and after ultrasonically bonding a thin metal wire to the surface of this conductor pattern, it surrounds the bonded part. A method for manufacturing a hybrid integrated circuit, characterized in that it is reinforced with a bonding material. 2. The method of manufacturing a hybrid integrated circuit according to claim 1, wherein the fixing material is silver paste.
JP62120378A 1987-05-18 1987-05-18 Manufacture of hybrid integrated circuit Pending JPS63284831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62120378A JPS63284831A (en) 1987-05-18 1987-05-18 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62120378A JPS63284831A (en) 1987-05-18 1987-05-18 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS63284831A true JPS63284831A (en) 1988-11-22

Family

ID=14784725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62120378A Pending JPS63284831A (en) 1987-05-18 1987-05-18 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS63284831A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100547A (en) * 2004-09-29 2006-04-13 Fujitsu Ltd Superconducting device
DE102007019795A1 (en) * 2007-04-26 2008-11-06 Infineon Technologies Ag Chip module and method for manufacturing this chip module
WO2014153405A1 (en) * 2013-03-20 2014-09-25 Texas Instruments Incorporated Semiconductor device having reinforced wire bond to metal terminal
EP2779232A3 (en) * 2013-03-15 2014-12-03 Renesas Electronics Corporation Semiconductor device with a chip bonded to a lead frame with a sintered Ag layer, wherein a resin fillet covers the sintered Ag layer and a part of a side surface of the chip and wherein chip electrodes are bonded to leads, as well as method of manufacturing the same
JP2018511175A (en) * 2015-03-16 2018-04-19 パック テック−パッケージング テクノロジーズ ゲーエムベーハー Chip arrangement and method for forming contact connections

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100547A (en) * 2004-09-29 2006-04-13 Fujitsu Ltd Superconducting device
DE102007019795A1 (en) * 2007-04-26 2008-11-06 Infineon Technologies Ag Chip module and method for manufacturing this chip module
DE102007019795B4 (en) * 2007-04-26 2012-10-04 Infineon Technologies Ag Chip module and method for manufacturing this chip module
EP2779232A3 (en) * 2013-03-15 2014-12-03 Renesas Electronics Corporation Semiconductor device with a chip bonded to a lead frame with a sintered Ag layer, wherein a resin fillet covers the sintered Ag layer and a part of a side surface of the chip and wherein chip electrodes are bonded to leads, as well as method of manufacturing the same
WO2014153405A1 (en) * 2013-03-20 2014-09-25 Texas Instruments Incorporated Semiconductor device having reinforced wire bond to metal terminal
JP2018511175A (en) * 2015-03-16 2018-04-19 パック テック−パッケージング テクノロジーズ ゲーエムベーハー Chip arrangement and method for forming contact connections

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