JP3048707B2 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JP3048707B2
JP3048707B2 JP27264691A JP27264691A JP3048707B2 JP 3048707 B2 JP3048707 B2 JP 3048707B2 JP 27264691 A JP27264691 A JP 27264691A JP 27264691 A JP27264691 A JP 27264691A JP 3048707 B2 JP3048707 B2 JP 3048707B2
Authority
JP
Japan
Prior art keywords
power
heat sink
semiconductor element
conductive path
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27264691A
Other languages
Japanese (ja)
Other versions
JPH05109940A (en
Inventor
伸一 豊岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP27264691A priority Critical patent/JP3048707B2/en
Publication of JPH05109940A publication Critical patent/JPH05109940A/en
Application granted granted Critical
Publication of JP3048707B2 publication Critical patent/JP3048707B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20754—Diameter ranges larger or equal to 40 microns less than 50 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/2076—Diameter ranges equal to or larger than 100 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To mount a power mono-type semiconductor element wherein a power circuit and a small signal circuit are formed on one chip on a substrate through a heat sink. CONSTITUTION:A heat sink 4 is fixed onto a conductive path 3 formed on a substrate 1, a junction substrate 6 is provided on the heat sink 4 and a thin Al wire line 7B for a small signal circuit of a semiconductor element 5 is connected to the conductive path 3 through the junction substrate 6.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は混成集積回路、特にパワ
ー部と小信号部とを集積化したパワーモノＩＣを搭載し
た混成集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit having a power mono IC in which a power section and a small signal section are integrated.

【０００２】[0002]

【従来の技術】従来、パワー系の半導体素子を搭載した
混成集積回路は図３に示す如く、セラミックスあるいは
表面を陽極酸化したアルミニウム等の絶縁基板（１１）
と、前記基板（１１）上に任意の形状に設けられた導電
路（１２）と、前記導電路（１２）上に半田付けされた
ヒートシンク（１３）とそのヒートシンク（１３）上に
固着されたパワートランジスタ等のパワー系の素子（１
４）と、そのパワー素子（１４）と周辺の導電路（１
２）とを接続するボンディングワイヤ線（１５）とで構
成され、所望出力の混成集積回路が実現されている。2. Description of the Related Art Conventionally, as shown in FIG. 3, a hybrid integrated circuit on which a power semiconductor element is mounted is an insulating substrate (11) made of ceramics or aluminum whose surface is anodized.
A conductive path (12) provided in an arbitrary shape on the substrate (11), a heat sink (13) soldered on the conductive path (12), and fixed on the heat sink (13). Power devices such as power transistors (1
4) and its power element (14) and its surrounding conductive path (1).
2) and a bonding wire line (15) for connection, and a hybrid integrated circuit having a desired output is realized.

【０００３】このような混成集積回路のヒートシンク上
に搭載されるパワー素子は、パワー段のみを構成する回
路が集積化されており、そのパワー素子を駆動させるド
ライバー用の小信号系の駆動用の回路素子は図３では示
されてないがパワー素子の近傍の導電路上に接続され両
者が接続される。In a power element mounted on a heat sink of such a hybrid integrated circuit, a circuit constituting only a power stage is integrated, and a small signal system for driving a driver for driving the power element is used. Although not shown in FIG. 3, the circuit elements are connected on a conductive path near the power element, and both are connected.

【０００４】[0004]

【発明が解決しようとする課題】従って、従来の混成集
積回路ではパワー素子とそのパワー素子を駆動させる小
信号素子とが夫々別に搭載されているため約１０Ａ以上
の大出力を有するパワー用の混成集積回路が実現でき
る。最近、パワー部とそのパワー部を駆動させる小信号
部とが１チップ化された（例えば高耐圧用のＭＯＳＦＥ
Ｔ等）ＬＳＩ素子が出現している。かかる素子のパワー
出力は前述した従来の混成集積回路の如き、大出力では
なく約１〜１０Ａ位の大きさの出力である。Therefore, in a conventional hybrid integrated circuit, a power element and a small signal element for driving the power element are separately mounted, so that a power hybrid having a large output of about 10 A or more is used. An integrated circuit can be realized. Recently, a power section and a small signal section for driving the power section have been integrated into one chip (for example, a MOSFE for high breakdown voltage).
T etc.) LSI elements have appeared. The power output of such a device is not a large output as in the conventional hybrid integrated circuit described above, but an output of about 1 to 10 A.

【０００５】しかしながら、放熱性を考慮するとヒート
シンクの厚みは最低でも２．５〜３ｍｍ位の厚みが必要
であり、パワー部の電極と導電路とを接続する約２００
μ径の太いＡｌワイヤ線はボンディング接続できるもの
の、小信号部の電極と導電路とを接続する約４０μ径の
細いＡｌワイヤ線はボンディング接続が行えず、パワー
部と小信号部とを備えた、いわゆるパワーモノＩＣを従
来の混成集積回路では実装することができなかった。However, in consideration of heat radiation, the thickness of the heat sink needs to be at least about 2.5 to 3 mm, and the thickness of the heat sink is about 200 to connect the electrode of the power section and the conductive path.
Although a thick Al wire having a diameter of μ can be connected by bonding, a thin Al wire having a diameter of about 40 μ connecting an electrode of a small signal portion and a conductive path cannot be connected by bonding, and has a power portion and a small signal portion. That is, a so-called power mono IC cannot be mounted on a conventional hybrid integrated circuit.

【０００６】[0006]

【課題を解決するための手段】本発明は上述した課題に
鑑みて為されたものであり、この発明に係わる混成集積
回路は、良熱伝導性の良好な混成集積回路基板と、前記
基板上に形成された導電路の所定位置に固着されたヒー
トシンクと、前記ヒートシンク上に固着され近傍の導電
路とワイヤ線に接続されたパワー半導体素子とを具備
し、前記パワー半導体素子と前記導電路とを接続する所
定のワイヤ線を前記ヒートシンク上に設けられた中継基
板を介して接続したことを特徴とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a hybrid integrated circuit according to the present invention includes a hybrid integrated circuit board having good thermal conductivity and A heat sink fixed to a predetermined position of a conductive path formed on the heat sink, and a power semiconductor element connected to a nearby conductive path and a wire wire fixed on the heat sink, wherein the power semiconductor element and the conductive path Are connected via a relay board provided on the heat sink.

【０００７】また、この発明に係わる混成集積回路は、
良熱伝導性の良好な混成集積回路基板と、前記基板上に
形成された導電路の所定位置に固着されたヒートシンク
と、前記ヒートシンク上に固着され且つ近傍の導電路と
ワイヤ線に接続されたパワー回路部とそのパワー回路部
を駆動させる小信号系回路部とが１チップ化されたパワ
ー半導体素子とを具備し、前記パワー半導体素子の小信
号回路用の比較的細いワイヤ線のみが、前記ヒートシン
ク上に設けられた中継基板を介して導電路と接続され、
パワー回路部用の比較的太いワイヤ線が直接導電路に接
続されたことを特徴とする。Further, a hybrid integrated circuit according to the present invention comprises:
A hybrid integrated circuit board having good thermal conductivity, a heat sink fixed to a predetermined position of a conductive path formed on the substrate, and a conductive path fixed to the heat sink and connected to a nearby conductive path and a wire line A power semiconductor element in which a power circuit section and a small signal system circuit section for driving the power circuit section are integrated into one chip, and only a relatively thin wire line for the small signal circuit of the power semiconductor element is provided; Connected to the conductive path via a relay board provided on the heat sink,
A relatively thick wire for the power circuit portion is directly connected to the conductive path.

【０００８】[0008]

【作用】以上のように構成される混成集積回路において
は、ヒートシンク上に中継基板を設けているために、従
来の構造では実装不可能であった、パワー回路部とその
パワー回路部を駆動させる小信号系回路とが１チップ化
されたパワーモノ型のパワー半導体素子を固着実装する
ことができる。即ち、細線（約３０μ〜４０μ）と太線
（約２００μ〜３００μ）とのボンディングワイヤ接続
を必要とするパワー半導体素子をヒートシンク上に固着
実装することができる。In the hybrid integrated circuit constructed as described above, since the relay board is provided on the heat sink, the power circuit section and the power circuit section are driven which cannot be mounted by the conventional structure. A power mono-type power semiconductor element in which a small signal system circuit and a single chip are integrated can be fixedly mounted. That is, a power semiconductor element that requires bonding wire connection between a thin wire (about 30 μm to 40 μm) and a thick wire (about 200 μm to 300 μm) can be fixedly mounted on a heat sink.

【０００９】[0009]

【実施例】以下に図１及び図２に示した実施例に基づい
て本発明を説明する。図１は本発明の混成集積回路の要
部拡大断面図であり、（１）は混成集積回路基板、
（２）は絶縁樹脂層、（３）は導電路、（４）はヒート
シンク、（５）はパワー半導体素子、（６）は中継基
板、（７）はワイヤ線である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the embodiments shown in FIGS. FIG. 1 is an enlarged sectional view of a main part of a hybrid integrated circuit according to the present invention.
(2) is an insulating resin layer, (3) is a conductive path, (4) is a heat sink, (5) is a power semiconductor element, (6) is a relay board, and (7) is a wire.

【００１０】混成集積回路基板（１）は良熱伝導性に優
れたアルミニウム基板が用いられ、その表面は周知技術
である陽極酸化法により、酸化アルミニウム膜が形成さ
れている。基板（１）上にはエポキシ樹脂等の絶縁樹脂
層（２）を介して、銅箔あるいは金属メッキ等の手段に
より所望形状の導電路（３）が形成されている。導電路
（３）上の所定位置には、図示されないがトランジス
タ、チップ抵抗、チップコンデンサー等の複数の回路素
子が固着実装されている。一方、パワー系の回路素子は
ヒートシンク（４）を介して実装される。As the hybrid integrated circuit substrate (1), an aluminum substrate having excellent heat conductivity is used, and an aluminum oxide film is formed on the surface of the substrate by an anodic oxidation method which is a well-known technique. A conductive path (3) having a desired shape is formed on the substrate (1) by means such as copper foil or metal plating via an insulating resin layer (2) such as an epoxy resin. At a predetermined position on the conductive path (3), a plurality of circuit elements such as transistors, chip resistors, and chip capacitors are fixedly mounted, though not shown. On the other hand, power circuit elements are mounted via a heat sink (4).

【００１１】本実施例で使用されるパワー半導体素子
（５）はパワートランジスタの如き、パワー回路のみが
形成されるものではなく、パワー回路部とそのパワー回
路部を駆動させる小信号系回路とが１チップ化された、
例えば高耐圧用ＭＯＳＦＥＴ等のパワーモノＩＣが使用
される。かかる、素子（５）を基板（１）上の導電路
（３）と接続する場合二種類のワイヤ線（７）を必要と
する。即ち、パワー回路部領域に形成された電極は約２
００μ〜５００μ径の比較的太いＡｌワイヤ線（７Ａ）
が用いられて接続され、小信号回路領域に形成された電
極は約２０〜５０μ径の比較的細いＡｌ等のワイヤ線
（７Ｂ）が用いられて接続される。The power semiconductor element (5) used in the present embodiment is not one in which only a power circuit is formed, such as a power transistor, but includes a power circuit section and a small signal circuit for driving the power circuit section. One chip,
For example, a power mono IC such as a high breakdown voltage MOSFET is used. When connecting the element (5) to the conductive path (3) on the substrate (1), two types of wire lines (7) are required. That is, about 2 electrodes are formed in the power circuit area.
A relatively thick Al wire with a diameter of 00μ to 500μ (7A)
The electrodes formed in the small signal circuit area are connected using a relatively thin wire (7B) of Al or the like having a diameter of about 20 to 50 μm.

【００１２】一方、ヒートシンク（４）は銅等の材質が
用いられ、パワー半導体素子（５）の熱放散を考慮する
とヒートシンク（４）の肉厚は約２．５ｍｍ〜３．５ｍ
ｍ位必要である。ヒートシンク（４）はパワー半導体素
子（５）よりも大きめに形成され、ヒートシンク（４）
の略中央部に素子（５）が半田等のろう材により固着さ
れる。On the other hand, the heat sink (4) is made of a material such as copper, and the thickness of the heat sink (4) is about 2.5 mm to 3.5 m in consideration of heat dissipation of the power semiconductor element (5).
m is required. The heat sink (4) is formed larger than the power semiconductor element (5), and the heat sink (4)
The element (5) is fixed to a substantially central portion of the device by a brazing material such as solder.

【００１３】本発明の特徴とするところは、パワー半導
体素子（５）が固着されたヒートシンク（４）上に中継
基板（６）を配置し、小信号系回路用の細いＡｌワイヤ
線（７Ｂ）を中継基板（６）を介して導電路（３）に接
続するところにある。中継基板（６）はガラエポ、セラ
ミックス等の絶縁基板が用いられ、その主面上には導体
パターン（６Ａ）が形成されている。中継基板（６）は
図２に示す如く、パワー半導体素子（５）を囲むように
枠状に形成され、内側周端部には細いワイヤ線（７Ｂ）
が接続される固着パッド（６Ｂ）が形成され、外側周端
部には中継基板（６）と導電路（３）とを接続する固着
パッド（６Ｃ）が形成される。前述したように中継基板
（６）上には固着パッド（６Ｂ）（６Ｃ）が形成され、
夫々のパッドは導電パターンにより接続されている。中
継基板（６）の肉厚は細いＡｌ等のワイヤ線（７Ｂ）を
ボンディング可能にするために約０．４ｍｍ〜１．４ｍ
ｍ厚に形成されている。即ち、パワー半導体素子（５）
と中継基板（６）との段差が約１ｍｍ位までがＡｌ等の
細線を用いてボンディングできる範囲であるためチップ
の厚みが変化すれば中継基板の厚みも変化する。A feature of the present invention is that a relay board (6) is arranged on a heat sink (4) to which a power semiconductor element (5) is fixed, and a thin Al wire line (7B) for a small signal system circuit is provided. Is connected to the conductive path (3) via the relay board (6). As the relay substrate (6), an insulating substrate such as glass epoxy or ceramic is used, and a conductor pattern (6A) is formed on the main surface thereof. As shown in FIG. 2, the relay board (6) is formed in a frame shape so as to surround the power semiconductor element (5), and a thin wire (7B) is formed on the inner peripheral end.
Is formed, and a fixing pad (6C) for connecting the relay board (6) and the conductive path (3) is formed on the outer peripheral end. As described above, the fixing pads (6B) and (6C) are formed on the relay board (6).
Each pad is connected by a conductive pattern. The thickness of the relay board (6) is about 0.4 mm to 1.4 m in order to enable bonding of a thin wire (7B) of Al or the like.
m thickness. That is, the power semiconductor element (5)
Since the step between the substrate and the relay board (6) is within a range that can be bonded using a thin wire of Al or the like up to about 1 mm, if the thickness of the chip changes, the thickness of the relay board also changes.

【００１４】ヒートシンク（４）上にパワー半導体素子
（５）及び中継基板（６）を接着剤等を用いて仮接着し
た後、ヒートシンク（４）は導電路（３）上に半田固着
される。パワー半導体素子（５）の小信号系回路領域に
形成された電極と中継基板（６）の一方の固着パッド
（６Ｂ）とが細いＡｌワイヤ線（７Ｂ）により接続さ
れ、次に中継基板（６）の他の固着パッド（６Ａ）と導
電路（３）が太いＡｌワイヤ線（７Ａ）により接続され
る。この際、パワー半導体素子（５）のパワー回路領域
に形成された例えばベース、エミッタ電極と基板（１）
上の導電路（３）が太いＡｌワイヤ線（７Ａ）により接
続される。After temporarily bonding the power semiconductor element (5) and the relay board (6) on the heat sink (4) using an adhesive or the like, the heat sink (4) is fixed by soldering on the conductive path (3). The electrode formed in the small signal system circuit area of the power semiconductor element (5) and one of the fixing pads (6B) of the relay board (6) are connected by a thin Al wire (7B). The other fixing pad (6A) and the conductive path (3) are connected by a thick Al wire (7A). At this time, for example, the base and emitter electrodes formed in the power circuit region of the power semiconductor element (5) and the substrate (1)
The upper conductive path (3) is connected by a thick Al wire (7A).

【００１５】パワー半導体素子（５）と周辺の導電路
（３）とを接続した後、パワー半導体素子（５）及びワ
イヤ線（７）は図示されないがエポキシ樹脂等の封止樹
脂層によって封止される。ところで、本実施例で用いら
れた中継基板（６）はヒートシンク（４）と略同一の大
きさであるが、中継基板（６）の大きさは、これに限ら
れるものではなく、例えば若干大きめに形成することも
可能である。After connecting the power semiconductor element (5) and the peripheral conductive path (3), the power semiconductor element (5) and the wire (7) are sealed with a sealing resin layer such as epoxy resin (not shown). Is done. By the way, the size of the relay board (6) used in the present embodiment is substantially the same as that of the heat sink (4), but the size of the relay board (6) is not limited to this, and is, for example, slightly larger. It is also possible to form it.

【００１６】更に、中継基板（６）を大きめに形成し、
中継基板（６）上にチップコンデンサー等の回路素子を
搭載し、中継基板（６）と基板（１）とをリード端子で
接続すれば多層化された混成集積回路を実現することが
できる。Further, the relay board (6) is formed relatively large,
If a circuit element such as a chip capacitor is mounted on the relay board (6), and the relay board (6) and the board (1) are connected by lead terminals, a multi-layered hybrid integrated circuit can be realized.

【００１７】[0017]

【発明の効果】以上に詳述した如く、本発明に依れば、
ヒートシンク上に中継基板を配置することにより、パワ
ー回路部とそのパワー回路部を駆動させる小信号回路と
が１チップ化された、いわゆるパワーモノ型のパワー半
導体素子の実装が可能となる。As described in detail above, according to the present invention,
By arranging the relay board on the heat sink, it is possible to mount a so-called power mono type power semiconductor element in which the power circuit section and the small signal circuit for driving the power circuit section are integrated into one chip.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１は本発明の実施例を示す要部拡大断面図で
ある。FIG. 1 is an enlarged sectional view of a main part showing an embodiment of the present invention.

【図２】図２は図１の平面図である。FIG. 2 is a plan view of FIG. 1;

【図３】図３は従来の混成集積回路を示す断面図であ
る。FIG. 3 is a sectional view showing a conventional hybrid integrated circuit.

【符号の説明】[Explanation of symbols]

（１） 混成集積回路基板 （２） 絶縁樹脂層 （３） 導電路 （４） ヒートシンク （５） パワー半導体素子 （６） 中継基板 （７） ワイヤ線 (1) Hybrid integrated circuit board (2) Insulating resin layer (3) Conductive path (4) Heat sink (5) Power semiconductor element (6) Relay board (7) Wire wire

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 混成集積回路基板上に形成された導電路
の所定位置に固着されたヒートシンクと、 前記ヒートシンク上に固着されたパワー半導体素子と、 前記ヒートシンク上に固着され、前記パワー半導体素子
の表面と１ｍｍ以内で表面が形成され、且つ前記パワー
半導体素子の周辺に設けられた絶縁材料から成る中継基
板と、 前記中継基板表面に形成され、前記パワー半導体素子に
近接した一方の端子と、前記中継基板の周辺に位置する
他方の端子とを有する導電パターンと、 前記パワー半導体素子と前記一方の端子を接続する細い
ワイヤー線と、 前記他方の端子と前記導電路を接続する太いワイヤー線
とを有することを特徴とした混成集積回路。 1. A conductive path formed on a hybrid integrated circuit substrate.
And a power semiconductor element fixed on the heat sink, and the power semiconductor element fixed on the heat sink.
The surface is formed within 1 mm from the surface of
Relay base made of insulating material provided around semiconductor element
Plate , formed on the relay substrate surface, and
One of the terminals close to the relay substrate
A conductive pattern having the other terminal; and a thin conductive pattern connecting the power semiconductor element and the one terminal.
A wire, and a thick wire connecting the other terminal and the conductive path.
A hybrid integrated circuit comprising: 【請求項２】 前記パワー半導体素子は、小信号系回路
部を有し、この小信号回路部が前記細いワイヤー線と接
続されることを特徴とした請求項１に記載の混成集積回
路。 2. The power semiconductor device according to claim 1, wherein the power semiconductor device is a small signal circuit.
And the small signal circuit section is connected to the thin wire.
2. The hybrid accumulating circuit according to claim 1, further comprising:
Road.
JP27264691A 1991-10-21 1991-10-21 Hybrid integrated circuit Expired - Fee Related JP3048707B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27264691A JP3048707B2 (en) 1991-10-21 1991-10-21 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27264691A JP3048707B2 (en) 1991-10-21 1991-10-21 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH05109940A JPH05109940A (en) 1993-04-30
JP3048707B2 true JP3048707B2 (en) 2000-06-05

Family

ID=17516827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27264691A Expired - Fee Related JP3048707B2 (en) 1991-10-21 1991-10-21 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP3048707B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000228491A (en) * 1999-02-09 2000-08-15 Toshiba Corp Semiconductor module and power converter
JP2007335782A (en) * 2006-06-19 2007-12-27 Fuji Electric Fa Components & Systems Co Ltd Semiconductor device module and manufacturing method thereof
WO2014013705A1 (en) * 2012-07-17 2014-01-23 富士電機株式会社 Semiconductor module

Also Published As

Publication number Publication date
JPH05109940A (en) 1993-04-30

Similar Documents

Publication Publication Date Title
US6482674B1 (en) Semiconductor package having metal foil die mounting plate
JPS59141249A (en) Power chip package
JPH03225854A (en) Semiconductor device and manufacture thereof
JP2735912B2 (en) Inverter device
JP3048707B2 (en) Hybrid integrated circuit
JP2919674B2 (en) Hybrid integrated circuit
JPH02201949A (en) Package of semiconductor device
JPH0645504A (en) Semiconductor device
JP2691352B2 (en) Electronic component mounting device
JPH0382060A (en) Semiconductor device
JPH08148647A (en) Semiconductor device
JP3011502B2 (en) Hybrid integrated circuit
JP3296626B2 (en) Hybrid integrated circuit device
KR100244826B1 (en) A semiconductor device and method for manufacturing the same
JP2736161B2 (en) Semiconductor device
JP2007157801A (en) Semiconductor module and its manufacturing method
JP2735920B2 (en) Inverter device
JP3172393B2 (en) Hybrid integrated circuit device
JPH05144985A (en) Hybrid integrated circuit device
KR20040075683A (en) Power semiconductor mudule package and method for fabricating the same
JP2879503B2 (en) Surface mount type electronic circuit device
JPH05235567A (en) Hybrid integrated circuit device
JP2555993B2 (en) Semiconductor device
JP2880817B2 (en) Semiconductor integrated circuit device
JPH0786497A (en) Intelligent power module

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees