JP2879503B2 - Surface mount type electronic circuit device - Google Patents
Surface mount type electronic circuit deviceInfo
- Publication number
- JP2879503B2 JP2879503B2 JP4313966A JP31396692A JP2879503B2 JP 2879503 B2 JP2879503 B2 JP 2879503B2 JP 4313966 A JP4313966 A JP 4313966A JP 31396692 A JP31396692 A JP 31396692A JP 2879503 B2 JP2879503 B2 JP 2879503B2
- Authority
- JP
- Japan
- Prior art keywords
- external electrode
- piece
- metal
- insulating piece
- joined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、面実装型電子回路装置
の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a surface mount type electronic circuit device.
【０００２】[0002]
【従来の技術】個別半導体、ＩＣ、抵抗、コンデンサ等
の能動素子や受動素子によって電子回路装置を形成し、
それをプリント配線板に搭載し、電子機器等を構成する
ことが広く実用化されている。2. Description of the Related Art An electronic circuit device is formed by active and passive elements such as individual semiconductors, ICs, resistors, and capacitors.
Mounting it on a printed wiring board to construct an electronic device or the like has been widely put to practical use.
【０００３】その電子回路装置として、例えば、金属基
板に搭載したベアチップに接続子やリード線を接続して
回路組立体を構成し、その回路組立体を樹脂封止すると
共に、リード線の端部を外部電極として導出する構造が
知られている。As the electronic circuit device, for example, a connector or a lead wire is connected to a bare chip mounted on a metal substrate to form a circuit assembly, the circuit assembly is sealed with a resin, and an end portion of the lead wire. Is known as an external electrode.
【０００４】図１は、従来構造の断面構造図を示し、１
は半導体のベアチップ、２は外部電極、３は封止樹脂、
４は接続子、５は金属基板、６はプリント配線板の実装
面である。金属基板５はベアチップ１を固着する基板で
あり、外部電極２の一部を連結している。又、外部電極
２の導出された端部は、プリント配線板の実装面６への
面実装に適するように折り曲げられている。FIG. 1 is a sectional view showing a conventional structure.
Is a bare semiconductor chip, 2 is an external electrode, 3 is a sealing resin,
4 is a connector, 5 is a metal substrate, and 6 is a mounting surface of a printed wiring board. The metal substrate 5 is a substrate to which the bare chip 1 is fixed, and connects a part of the external electrode 2. Further, the leading end of the external electrode 2 is bent so as to be suitable for surface mounting on the mounting surface 6 of the printed wiring board.
【０００５】[0005]
【発明が解決しようとする課題】ａ．外部電極の導出に
おいて、封止樹脂が介在するため、リード線の長さが増
加し、電気抵抗が大となる。 ｂ．外部電極の端部を面実装型に適するようにフォーミ
ング加工するのが厄介である。 ｃ．モールド金型による樹脂封止で各構成部品の電気絶
縁性を保持すると共に、一体化するので、各部の位置精
度の確保に注意を要し、かつ、高価となる。 ｄ．半導体チップを搭載する金属基板とプリント配線板
の実装面間に封止樹脂が介在するため、熱伝導効果が悪
い。 ｅ．小電流用の外部電極を多数、導出することが困難で
ある。 これらの問題点が従来構造の解決すべき課題である。Problems to be Solved by the Invention a. In the derivation of the external electrodes, since the sealing resin is interposed, the length of the lead wire increases, and the electric resistance increases. b. It is troublesome to form the end of the external electrode so as to be suitable for the surface mount type. c. Since the electrical insulation of each component is maintained and integrated by resin sealing with a mold, attention must be paid to ensuring the positional accuracy of each component and the cost is high. d. Since the sealing resin is interposed between the metal substrate on which the semiconductor chip is mounted and the mounting surface of the printed wiring board, the heat conduction effect is poor. e. It is difficult to derive a large number of external electrodes for small current. These problems are problems to be solved by the conventional structure.
【０００６】[0006]
【課題を解決するための手段】本発明はチップ半導体を
装着した第１の金属片と第１の絶縁片を側面で接合し、
かつ第１の絶縁片に第１の金属膜を被着するか金属片を
接合して第１の外部電極を形成し、前記半導体チップの
電極と前記外部電極を接続子で接続し、半導体チップ及
び接続子を装着した基板面の周辺部に絶縁物包囲体を形
成し、絶縁物包囲体内部を樹脂封止して面実装型電子回
路装置を作成した。請求項２の発明は第１の絶縁片を接
合した第１の金属片の他端部に第２の絶縁片を接合し、
かつ第２の絶縁片に第２の金属膜上を被着するか金属片
を接合して第２の外部電極を形成し、前記半導体チップ
の他の電極と前記第２の外部電極を接続子で接続し半導
体チップが３端子以上のものに適用できるようにしたも
のである。According to the present invention, a first metal piece on which a chip semiconductor is mounted and a first insulating piece are joined on a side surface,
And attaching a first metal film to the first insulating piece or joining the metal piece to form a first external electrode, connecting the electrode of the semiconductor chip and the external electrode with a connector, In addition, an insulator enclosure was formed around the substrate surface on which the connector was mounted, and the interior of the insulator enclosure was sealed with a resin to produce a surface-mounted electronic circuit device. The invention according to claim 2 is configured such that a second insulating piece is joined to the other end of the first metal piece to which the first insulating piece is joined,
A second external electrode is formed by attaching a second metal film to the second insulating piece or joining the metal piece to the second insulating piece, and connecting another electrode of the semiconductor chip to the second external electrode. And a semiconductor chip having three or more terminals.
【０００７】[0007]
【実施例】図２は、本発明の実施例を示す構造図であ
り、（ａ）は平面図、（ｂ）は正面図である。又、１′
は半導体チップ、７は板状、棒状等の第１の金属片、８
は板状、棒状等のセラミック、樹脂材などから成る第１
の絶縁片、９は第１の絶縁片８上にメッキ処理等により
被着した第１の外部電極、１０は半導体チップ１′と第
１の外部電極９を接続するワイヤ、金属片等の第１の接
続子、１１は第１の絶縁片８を接合した第１の金属片７
の側面と反対側面に接合した第２の絶縁片、１２は第２
の絶縁片１１に接合した第２の外部電極、１３は半導体
チップ１′と第２の外部電極１２を接続する第２の接続
子、１４は枠体状、ダム状等の樹脂材、ガラス材などに
よる絶縁物包囲体である。2 is a structural view showing an embodiment of the present invention. FIG. 2 (a) is a plan view and FIG. 2 (b) is a front view. Also, 1 '
Is a semiconductor chip, 7 is a first metal piece having a plate shape, a rod shape, or the like, 8
Is the first made of ceramic, resin, etc., in the form of a plate, rod, etc.
9 is a first external electrode applied on the first insulating piece 8 by plating or the like, and 10 is a first external electrode such as a wire connecting the semiconductor chip 1 ′ and the first external electrode 9. A first connector 11 is a first metal piece 7 to which a first insulating piece 8 is bonded.
The second insulating piece joined to the side opposite to the side of
A second external electrode joined to the insulating piece 11, a second connector 13 for connecting the semiconductor chip 1 'and the second external electrode 12, a resin material such as a frame-shaped or dam-shaped material, a glass material And the like.
【０００８】図２において、第１の金属片７は、例え
ば、銅タングステン合金により板状に形成され、その一
側面に銀ロー付け等により、第１の絶縁片８、例えば、
セラミック板が接合される。又、第１の金属片７の反対
側面には第２の絶縁片１１、例えば、セラミック板、及
び第２の外部電極１２を順次、銀ロー付け等により接合
し、８−７−１１−１２の順にブロック状に接合され一
体化した基板を構成する。なお、第１の絶縁片８上には
第１の外部電極９、例えば、金ニッケル合金を表面層に
した導電膜が上面（半導体チップ搭載側の面）から下面
（図示しないプリント配線板の実装面に対向する面で、
図２（ｂ）の下方の面である。）にわたって、例えば、
２個所、設けている。In FIG. 2, a first metal piece 7 is formed in a plate shape from, for example, a copper-tungsten alloy, and a first insulating piece 8, for example,
The ceramic plates are joined. On the opposite side of the first metal piece 7, a second insulating piece 11, for example, a ceramic plate, and a second external electrode 12 are sequentially bonded by silver brazing or the like to form an 8-7-11-12. In this order to form an integrated substrate. On the first insulating piece 8, a first external electrode 9, for example, a conductive film having a surface layer of a gold-nickel alloy is mounted from the upper surface (the surface on the semiconductor chip mounting side) to the lower surface (mounting of a printed wiring board (not shown)). On the surface facing the surface,
It is a lower surface of FIG.2 (b). ) Over, for example,
Two locations are provided.
【０００９】次いで、第１の金属片７上に、半導体チッ
プ１′、例えば、トランジスタチップ２個を半田付け
し、例えば、アルミ線による第１の接続子１０及び第２
の接続子１３によって１′と第１の外部電極９間及び
１′と第２の外部電極１２をそれぞれ、例えば、ワイア
ボンドにより接続する。Next, the semiconductor chip 1 ', for example, two transistor chips, is soldered on the first metal piece 7, and the first connector 10 and the second
1 'and the first external electrode 9 and 1' and the second external electrode 12 are connected by, for example, a wire bond.
【００１０】又、ブロック状に接合一体化した基板の周
辺部に絶縁物包囲体１４を例えば、接着剤により固着
し、１４の包囲領域内に樹脂を注入し、封止する。この
ように、構成した実施例（樹脂を注入する前）を図３の
斜視構造図により示した。Further, an insulator surrounding body 14 is fixed to a peripheral portion of the substrate joined and integrated in a block shape by, for example, an adhesive, and a resin is injected into a surrounding area of the board 14 to be sealed. The embodiment thus configured (before the resin is injected) is shown in the perspective view of FIG.
【００１１】図４は本発明の他の実施例の平面構造図
で、図４においては、第１の絶縁片８の反対側面（第１
の金属片との接合面と反対側の側面）に第２の金属片１
５を接合したものである。従って、図３のように第１の
外部電極９を設けることなく、第２の金属片１５を第２
の外部電極とし、第１の接続子１０は半導体チップ１′
と１５間を接続するように装着される。ただし、第１の
外部電極９のように複数個の第２の外部電極を形成でき
ない。FIG. 4 is a plan view showing another embodiment of the present invention. In FIG. 4, the opposite side (first side) of the first insulating piece 8 is shown.
The second metal piece 1 on the side opposite to the bonding surface with the metal piece
5 are joined. Therefore, the second metal piece 15 can be connected to the second metal piece 15 without providing the first external electrode 9 as shown in FIG.
Of the semiconductor chip 1 '.
And 15 are connected. However, a plurality of second external electrodes cannot be formed like the first external electrode 9.
【００１２】図２において、第２の絶縁片１１、第２の
外部電極１２を順次、第１の金属片７に接合している
が、これを第１の絶縁片８上の第１の外部電極９のよう
に、第２の絶縁片１１上に一又は複数の外部電極を被着
する構成としてもよい。つまり、本発明に用いる基板構
成の最小限は第１の外部電極となる第１の金属片の一側
面に第１の絶縁片を接合し、又第２の外部電極として、
第１の絶縁片に、第１の外部電極を被着するか、又は第
２の金属片を接合する構成である。又、必要に応じて、
第１の金属片の他方の側面にも第２の絶縁片を接合し、
第３の外部電極として、第２の絶縁片に第２の金属膜を
被着するか、又は第２の外部電極を接合する構成を選択
的に付加し得るものである。さらに、これらの構成を多
数、縦続的に配設することもできる。In FIG. 2, the second insulating piece 11 and the second external electrode 12 are sequentially joined to the first metal piece 7, but this is joined to the first external piece 8 on the first insulating piece 8. Like the electrode 9, one or a plurality of external electrodes may be provided on the second insulating piece 11. That is, the minimum of the substrate configuration used in the present invention is to join the first insulating piece to one side surface of the first metal piece to be the first external electrode,
The configuration is such that a first external electrode is attached to a first insulating piece or a second metal piece is joined. Also, if necessary
A second insulating piece is also joined to the other side of the first metal piece,
As the third external electrode, a structure in which a second metal film is applied to a second insulating piece or a structure in which the second external electrode is joined can be selectively added. Furthermore, many of these configurations can be arranged in cascade.
【００１３】第１の外部電極、第２の外部電極を金属膜
とする場合は、第２の外部電極に金属片を選択する場合
に比し、処理電流容量が小であり、信号用等の比較的小
電流用の外部電極に適しており、又、多数の外部電極の
導出を容易とする。When the first external electrode and the second external electrode are made of metal films, the processing current capacity is smaller than when a metal piece is selected for the second external electrode, and the signal current and the like are used. It is suitable for an external electrode for a relatively small current and facilitates the derivation of a large number of external electrodes.
【００１４】段落０００５に記載した課題と対応する
と、ａについては、基板を構成する第１の金属片、第２
の金属片、又は第２の外部電極を直接、外部電極とする
ため電気抵抗が小となり、電圧降下、電力損失を低減す
る。ｂについては、基板を構成する金属片又は金属膜を
直接、外部電極とするため、フォーミング加工を必要と
しない。従って、プリント配線板上の他の部品と同一工
程により半田付けを容易になし得る。Ｃについては、モ
ールド金型を必要とせず、半導体チップ、接続子等の搭
載面レベルが同一となり、配線がやりやすく、電気絶縁
性の保持、各部の位置精度が容易となる。又、封止は、
絶縁物包囲体を用いることができ、表面封止のみにより
簡単化できる。ｄについては、半導体チップの下方は金
属片を介し、直接、プリント配線板の実装面に接触する
構造となり熱放散効果が大となる。ｅについては、絶縁
片上の金属膜の形成により、小電流用の外部電極の導出
が容易となる。Corresponding to the problem described in paragraph 0005, regarding a, the first metal piece and the second metal piece constituting the substrate
Since the metal piece or the second external electrode is directly used as the external electrode, the electric resistance is reduced, and the voltage drop and the power loss are reduced. Regarding b, since a metal piece or a metal film constituting the substrate is directly used as an external electrode, no forming process is required. Therefore, soldering can be easily performed by the same process as other components on the printed wiring board. With regard to C, no mold is required, the mounting surface levels of the semiconductor chips, connectors, and the like are the same, wiring is easy, electrical insulation is maintained, and positional accuracy of each part is facilitated. Also, the sealing is
An insulator enclosure can be used and can be simplified only by surface sealing. As for d, the structure below the semiconductor chip is in direct contact with the mounting surface of the printed wiring board via the metal piece, and the heat dissipation effect is large. Regarding e, the formation of the metal film on the insulating piece facilitates the derivation of the small current external electrode.
【００１５】本発明の実施例は、本発明の要旨の範囲で
変形、変換、削除、付加等の変更をなし得るものであ
る。半導体チップ、接続子、外部電極等は回路設計に応
じて、種類、数、形状等を選択し得るものである。The embodiments of the present invention can be modified, changed, deleted, added, etc. within the scope of the present invention. The type, number, shape, and the like of the semiconductor chip, connectors, external electrodes, and the like can be selected according to the circuit design.
【００１６】[0016]
【発明の効果】以上説明したとおり、ベアチップを含む
各種半導体チップを搭載し、回路構成した面実装型電子
回路装置を外部電極の電気抵抗が小さく、放熱性の優れ
た構造とし、プリント配線板への面実装により、電源機
器をはじめ、各種装置の小型化、低損失化、高信頼性化
等を実現し、産業上の利用効果、極めて大なるものであ
る。As described above, a surface-mounted electronic circuit device mounted with various semiconductor chips including a bare chip and configured as a circuit has a structure in which the external electrodes have a small electric resistance and excellent heat dissipation properties, and are applied to a printed wiring board. The surface mounting realizes downsizing, low loss, high reliability, etc. of various devices including power supply devices, and the industrial use effect is extremely large.
【図１】従来構造の断面構造図。FIG. 1 is a sectional structural view of a conventional structure.
【図２】本発明の実施例の構造図で、（ａ）は平面図、
（ｂ）は正面図FIG. 2 is a structural view of an embodiment of the present invention, (a) is a plan view,
(B) is a front view
【図３】本発明の実施例の斜視構造図FIG. 3 is a perspective structural view of an embodiment of the present invention.
【図４】本発明の他の実施例の平面構造図FIG. 4 is a plan structural view of another embodiment of the present invention.
１ ベアチップ １′ 半導体チップ ２ 外部電極 ３ 封止樹脂 ４ 接続子 ５ 金属基板 ６ プリント配線板の実装面 ７ 第１の金属片 ８ 第１の絶縁片 ９ 第１の外部電極 １０ 第１の接続子 １１ 第２の絶縁片 １２ 第２の外部電極 １３ 第２の接続子 １４ 絶縁物包囲体 １５ 第２の金属片 REFERENCE SIGNS LIST 1 bare chip 1 ′ semiconductor chip 2 external electrode 3 sealing resin 4 connector 5 metal substrate 6 printed wiring board mounting surface 7 first metal piece 8 first insulating piece 9 first external electrode 10 first connector DESCRIPTION OF SYMBOLS 11 2nd insulating piece 12 2nd external electrode 13 2nd connector 14 insulator enclosure 15 2nd metal piece
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−67687（ＪＰ，Ａ) 特開 昭59−217385（ＪＰ，Ａ) 特開 平２−210851（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60,23/12,25/04 H05K 1/02 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-67687 (JP, A) JP-A-59-217385 (JP, A) JP-A-2-210851 (JP, A) (58) Field (Int.Cl. 6 , DB name) H01L 21 / 60,23 / 12,25 / 04 H05K 1/02
Claims (2)
第１の絶縁片を側面で接合し、かつ前記第１の絶縁片に
第１の金属膜を被着するか金属片を接合して第１の外部
電極を形成し、前記半導体チップの電極と前記第一の外
部電極を接続子で接続し、半導体チップ及び接続子を接
続した前記第一の金属片と前記第一の絶縁片の周辺部に
絶縁物包囲体を形成し、絶縁物包囲体内部を樹脂封止し
たことを特徴とする面実装型電子回路装置。1. A first metal piece on which a semiconductor chip is mounted and a first insulating piece are joined at a side surface, and a first metal film is applied to the first insulating piece or the metal piece is joined. Forming a first external electrode, connecting the electrode of the semiconductor chip and the first external electrode with a connector, and connecting the semiconductor chip and the connector with the first metal piece and the first insulating piece. A surface mount type electronic circuit device characterized in that an insulator surrounding body is formed in a peripheral portion of the electronic device, and the inside of the insulator surrounding body is sealed with a resin.
他端部に第２の絶縁片を接合し、かつ第２の絶縁片に第
２の金属膜を被着するか金属片を接合して第２の外部電
極を形成し、前記半導体チップの他の電極と前記第２の
外部電極を接続子で接続したことを特徴とする請求項１
の面実装型電子回路装置。2. A method in which a second insulating piece is joined to the other end of the first metal piece to which the first insulating piece is joined, and a second metal film is applied to the second insulating piece. 2. The second external electrode is formed by joining pieces, and another electrode of the semiconductor chip and the second external electrode are connected by a connector.
Surface mount type electronic circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4313966A JP2879503B2 (en) | 1992-10-29 | 1992-10-29 | Surface mount type electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4313966A JP2879503B2 (en) | 1992-10-29 | 1992-10-29 | Surface mount type electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06151632A JPH06151632A (en) | 1994-05-31 |
| JP2879503B2 true JP2879503B2 (en) | 1999-04-05 |
Family
ID=18047630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4313966A Expired - Fee Related JP2879503B2 (en) | 1992-10-29 | 1992-10-29 | Surface mount type electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2879503B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4418426B4 (en) * | 1993-09-08 | 2007-08-02 | Mitsubishi Denki K.K. | Semiconductor power module and method of manufacturing the semiconductor power module |
-
1992
- 1992-10-29 JP JP4313966A patent/JP2879503B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06151632A (en) | 1994-05-31 |
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