JPH06151632A - Surface mounting type electronic circuit device - Google Patents
Surface mounting type electronic circuit deviceInfo
- Publication number
- JPH06151632A JPH06151632A JP4313966A JP31396692A JPH06151632A JP H06151632 A JPH06151632 A JP H06151632A JP 4313966 A JP4313966 A JP 4313966A JP 31396692 A JP31396692 A JP 31396692A JP H06151632 A JPH06151632 A JP H06151632A
- Authority
- JP
- Japan
- Prior art keywords
- piece
- metal
- external electrode
- metallic
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、面実装型電子回路装置
の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a surface mount type electronic circuit device.
【０００２】[0002]
【従来の技術】個別半導体、ＩＣ、抵抗、コンデンサ等
の能動素子や受動素子によって電子回路装置を形成し、
それをプリント配線板に搭載し、電子機器等を構成する
ことが広く実用化されている。2. Description of the Related Art An electronic circuit device is formed by active elements and passive elements such as individual semiconductors, ICs, resistors and capacitors.
It has been widely put into practical use to mount it on a printed wiring board to configure an electronic device or the like.
【０００３】（２） その電子回路装置として、例えば、金属基板に搭載した
ベアチップに接続子やリ−ド線を接続して回路組立体を
構成し、その回路組立体を樹脂封止すると共に、リ−ド
線の端部を外部電極として導出する構造が知られてい
る。(2) As the electronic circuit device, for example, a bare chip mounted on a metal substrate is connected with a connector or a lead wire to form a circuit assembly, and the circuit assembly is resin-sealed. A structure is known in which the ends of the lead wires are led out as external electrodes.
【０００４】図１は、従来構造の断面構造図を示し、１
は半導体のベアチップ、２は外部電極、３は封止樹脂、
４は接続子、５は金属基板、６はプリント配線板の実装
面である。金属基板５はベアチップ１を固着する基板で
あり、外部電極２の一部を連結している。又、外部電極
２の導出された端部は、プリント配線板の実装面６への
面実装に適するように折り曲げられている。FIG. 1 is a sectional view showing a conventional structure.
Is a semiconductor bare chip, 2 is an external electrode, 3 is a sealing resin,
Reference numeral 4 is a connector, 5 is a metal substrate, and 6 is a mounting surface of a printed wiring board. The metal substrate 5 is a substrate to which the bare chip 1 is fixed, and connects a part of the external electrodes 2. The lead-out end of the external electrode 2 is bent so as to be suitable for surface mounting on the mounting surface 6 of the printed wiring board.
【０００５】[0005]
ａ．外部電極の導出において、封止樹脂が介在するた
め、リ−ド線の長さが増加し、電気抵抗が大となる。 ｂ．外部電極の端部を面実装型に適するようにフォ−ミ
ング加工するのが厄介である。 ｃ．モ−ルド金型による樹脂封止で各構成部品の電気絶
縁性を保持すると共に、一体化するので、各部の位置精
度の確保に注意を要し、かつ、高価となる。 ｄ．チップ部品を搭載する金属基板とプリント配線板の
実装面間に封止樹脂が介在するため、熱伝導効果が悪
い。 ｅ．小電流用の外部電極を多数、導出することが困難で
ある。 これらの問題点が従来構造の解決すべき課題である。a. Since the encapsulating resin intervenes in the lead-out of the external electrode, the length of the lead wire increases and the electric resistance becomes large. b. It is troublesome to form the ends of the external electrodes so as to be suitable for the surface mounting type. c. Since the electrical insulation of each component is maintained and integrated by resin sealing with a mold, care must be taken to ensure the positional accuracy of each component, and it becomes expensive. d. Since the sealing resin is interposed between the mounting surface of the printed wiring board and the metal substrate on which the chip component is mounted, the heat conduction effect is poor. e. It is difficult to derive many external electrodes for small current. These problems are problems to be solved by the conventional structure.
【０００６】[0006]
【課題を解決するための手段】本発明は、（１）第１の
金属片と第１の絶縁片を側面で接合し、かつ、第１の絶
縁片に第１の金属膜を被着するか、又は第１の絶縁片に
第２の金属片を接合して形成した基板の第１の金属片上
にチップ部品を装着し、又第１の金属膜上、又は第２の
金属片上にチップ部品からの第１の接続子を装着するよ （３） うにし、第１の金属片を第１の外部電極とし、第１の金
属膜、又は第２の金属片を第２の外部電極としたことを
特徴とする構成。 （２）前記（１）項の構成において、第１の絶縁片を接
合した第１の金属片の反対側面に第２の絶縁片を接合
し、かつ、第２の絶縁片に第２の金属膜上を被着する
か、又は第２の絶縁片に第３の金属片を接合して形成し
た基板の第２の金属膜上、又は第３の金属片上にチップ
部品からの第２の接続子を装着するようにし、第２の金
属膜、又は第３の金属片を第３の外部電極としたことを
特徴とする構成。 （３）前記（１）項又は（２）項の構成において、チッ
プ部品及び接続子を装着した基板面の周辺部に絶縁物包
囲体を形成し、絶縁物包囲体内部を絶縁物封止したこと
を特徴とする構成。According to the present invention, (1) a first metal piece and a first insulating piece are joined at a side surface, and a first metal film is deposited on the first insulating piece. Alternatively, the chip component is mounted on the first metal piece of the substrate formed by joining the second metal piece to the first insulating piece, and the chip is mounted on the first metal film or the second metal piece. Mount the first connector from the component (3), and use the first metal piece as the first external electrode and the first metal film or the second metal piece as the second external electrode. The configuration that is characterized. (2) In the configuration of (1) above, the second insulating piece is joined to the opposite side of the first metal piece to which the first insulating piece is joined, and the second metal piece is attached to the second insulating piece. Second connection from the chip component on the second metal film of the substrate, which is deposited on the film or formed by joining the third metal piece to the second insulating piece, or on the third metal piece A configuration in which a child is attached, and the second metal film or the third metal piece is used as a third external electrode. (3) In the configuration of (1) or (2), an insulator enclosure is formed in the peripheral portion of the substrate surface on which the chip component and the connector are mounted, and the inside of the insulator enclosure is sealed with an insulator. A configuration characterized in that.
【０００７】[0007]
【実施例】図２は、本発明の実施例を示す構造図であ
り、（ａ）は平面図、（ｂ）は正面図である。又、１′
は能動素子、受動素子等のベア型又は封止型のチップ部
品、７は板状、棒状等の第１の金属片、８は板状、棒状
等のセラミック、樹脂材などから成る第１の絶縁片、９
は第１の絶縁片８上にメッキ処理等により被着した第１
の金属膜、１０はチップ部品１′と第１の金属膜９を接
続するワイア、金属片等の第１の接続子、１１は第１の
絶縁片８を接合した第１の金属片７の側面と反対側面に
接合した第２の絶縁片、１２は第２の絶縁片１１に接合
した第３の金属片、１３はチップ部品１′と第３の金属
片１２を接続する第２の接続子、１４は枠体状、ダム状
等の樹脂材、ガラス材などによる絶縁物包囲体である。2 is a structural view showing an embodiment of the present invention, (a) is a plan view and (b) is a front view. Also, 1 '
Is a bare or sealed chip component such as an active element or a passive element, 7 is a first metal piece having a plate-like or rod-like shape, and 8 is a first metal-resin material having a plate-like or rod-like shape. Insulation piece, 9
Is the first insulating member 8 deposited by plating or the like.
Metal film, 10 is a first connector such as a wire or a metal piece for connecting the chip component 1 ′ and the first metal film 9, and 11 is a first metal piece 7 to which the first insulating piece 8 is joined. A second insulating piece joined to the side surface and the opposite side surface, 12 is a third metal piece joined to the second insulating piece 11, and 13 is a second connection for connecting the chip component 1 ′ and the third metal piece 12. The child 14 is an insulator enclosure made of a resin material such as a frame or a dam, or a glass material.
【０００８】図２において、第１の金属片７は、例え
ば、銅タングステン合金により板状に形成され、その一
側面に銀ロ−付け等により、第１の絶縁片８、例えば、
セラミック板が接合される。又、第１の金属片７の反対
側面には第２の絶縁片１１、例えば、セラミック板、及
び第３の金属片１２を順次、銀ロ−付け （４） 等により接合し、８−７−１１−１２の順にブロック状
に接合され一体化した基板を構成する。なお、第１の絶
縁片８上には第１の金属膜９、例えば、金ニッケル合金
を表面層にした導電膜が上面（チップ部品搭載側の面）
から下面（図示しないプリント配線板の実装面に対向す
る面で、図２（ｂ）の下方の面である。）にわたって、
例えば、２個所、設けている。In FIG. 2, the first metal piece 7 is formed of, for example, a copper-tungsten alloy into a plate shape, and one side surface thereof is silver-rolled or the like to form the first insulating piece 8, for example,
The ceramic plates are joined. On the opposite side of the first metal piece 7, a second insulating piece 11, for example, a ceramic plate and a third metal piece 12 are sequentially joined by silver brazing (4) or the like, and 8-7 -11-12 is bonded in the order of blocks to form an integrated substrate. A first metal film 9, for example, a conductive film having a surface layer of gold-nickel alloy, is formed on the first insulating piece 8 as an upper surface (chip component mounting side).
From the lower surface (the surface facing the mounting surface of the printed wiring board (not shown), which is the lower surface of FIG. 2B),
For example, two locations are provided.
【０００９】次いで、第１の金属片７上に、チップ部品
１′、例えば、トランジスタチップ２個を半田付けし、
例えば、アルミ線による第１の接続子１０及び第２の接
続子１３によって１′と第１の金属膜９間及び１′と第
３の金属片１２をそれぞれ、例えば、ワイアボンドによ
り接続する。又、第１の金属片７の下面を第１の外部電
極、第１の金属膜の下面を第２の外部電極、第３の金属
片の下面を第３の外部電極として、プリント配線板の実
装面に半田付けすることができる。Then, a chip component 1 ', for example, two transistor chips are soldered onto the first metal piece 7,
For example, the first connector 10 and the second connector 13 made of aluminum wire connect 1'and the first metal film 9 and 1'and the third metal piece 12, respectively, by, for example, a wire bond. The lower surface of the first metal piece 7 is used as a first external electrode, the lower surface of the first metal film is used as a second external electrode, and the lower surface of the third metal piece is used as a third external electrode. It can be soldered to the mounting surface.
【００１０】又、ブロック状に接合一体化した基板の周
辺部に絶縁物包囲体１４を例えば、接着剤により固着
し、１４の包囲領域内に樹脂を注入し、封止する。この
ように、構成した実施例（樹脂を注入する前）を図３の
斜視構造図により示した。In addition, the insulator enclosure 14 is fixed to the peripheral portion of the block-integrated substrate by, for example, an adhesive, and a resin is injected into the enclosure area of 14 to seal it. The thus constructed embodiment (before injecting the resin) is shown by the perspective structure diagram of FIG.
【００１１】図４は本発明の他の実施例の平面構造図
で、図２、図３と同一符号は同等部分である。図４にお
いては、第１の絶縁片８の反対側面（第１の金属片との
接合面と反対側の側面）に第２の金属片１５を接合した
ものである。従って、図３のように第１の金属膜９を設け
ることなく、第２の金属片１５を第２の外部電極とし、
第１の接続子１０はチップ部品１′と１５間を接続する
ように装着される。ただし、第１の金属膜９のように複
数個の第２の外部電極を形成できない。FIG. 4 is a plan view of another embodiment of the present invention, in which the same reference numerals as those in FIGS. 2 and 3 designate the same parts. In FIG. 4, the second metal piece 15 is joined to the opposite side surface of the first insulating piece 8 (the side surface opposite to the joining surface with the first metal piece). Therefore, without providing the first metal film 9 as shown in FIG. 3, the second metal piece 15 is used as the second external electrode,
The first connector 10 is mounted so as to connect between the chip components 1 ′ and 15. However, unlike the first metal film 9, a plurality of second external electrodes cannot be formed.
【００１２】図２において、第２の絶縁片１１、第３の
金属片１２を順次、第１の金属片 （５） ７に接合しているが、これを第１の絶縁片８上の第１の
金属膜９のように、第２の絶縁片１１上に一又は複数の
金属膜を被着する構成としてもよい。つまり、本発明に
用いる基板構成の最小限は第１の外部電極となる第１の
金属片の一側面に第１の絶縁片を接合し、又第２の外部
電極として、第１の絶縁片に、第１の金属膜を被着する
か、又は第２の金属片を接合する構成である。又、必要
に応じて、第１の金属片の他方の側面にも第２の絶縁片
を接合し、第３の外部電極として、第２の絶縁片に第２
の金属膜を被着するか、又は第３の金属片を接合する構
成を選択的に付加し得るものである。さらに、これらの
構成を多数、縦続的に配設することもできる。In FIG. 2, the second insulating piece 11 and the third metal piece 12 are sequentially joined to the first metal piece (5) 7, which is the first insulating piece 8 on the first insulating piece 8. Like the first metal film 9, one or a plurality of metal films may be deposited on the second insulating piece 11. That is, the minimum substrate configuration used in the present invention is to join the first insulating piece to one side surface of the first metal piece that serves as the first external electrode, and to use the first insulating piece as the second external electrode. Then, the first metal film is adhered to the first metal piece or the second metal piece is joined. If necessary, a second insulating piece may be joined to the other side surface of the first metal piece to form a second external piece as a third external electrode.
It is possible to selectively add a structure in which the above metal film is adhered or a third metal piece is joined. Further, a large number of these configurations can be arranged in cascade.
【００１３】第２の外部電極を第１の金属膜、第３の外
部電極を第２の金属膜とする場合は、第２の金属片又は
第３の金属片を選択する場合に比し、処理電流容量が小
であり、信号用等の比較的小電流用の外部電極に適して
おり、又、多数の外部電極の導出を容易とする。When the second external electrode is the first metal film and the third external electrode is the second metal film, as compared with the case where the second metal piece or the third metal piece is selected, It has a small processing current capacity, is suitable for an external electrode for a relatively small current such as a signal, and facilitates the derivation of a large number of external electrodes.
【００１４】段落０００５に記載した課題と対応する
と、ａについては、基板を構成する第１の金属片、第２
の金属片、又は第３の金属片の底面を直接、外部電極と
するため電気抵抗が小となり、電圧降下、電力損失を低
減する。ｂについては、基板を構成する金属片又は金属
膜を直接、外部電極とするため、フォ−ミング加工を必
要としない。従って、プリント配線板上の他の部品と同
一工程により半田付けを容易になし得る。Ｃについて
は、モ−ルド金型を必要とせず、チップ部品、接続子等
の搭載面レベルが同一となり、配線がやりやすく、電気
絶縁性の保持、各部の位置精度が容易となる。又、封止
は、絶縁物包囲体を用いることができ、表面封止のみに
より簡単化できる。ｄについては、チップ部品の下方は
金属片を介し、直接、プリント配線板の実装面に接触す
る構造となり熱放散効果が大となる。ｅについては、絶
縁片上の金属膜の形成により、小電流用の外部電極の導
出 （６） が容易となる。Corresponding to the problem described in paragraph 0005, as for a, the first metal piece and the second metal piece constituting the substrate are used.
Since the metal piece or the bottom surface of the third metal piece is directly used as the external electrode, the electric resistance becomes small, and the voltage drop and the power loss are reduced. Regarding b, since the metal piece or the metal film forming the substrate is directly used as the external electrode, the forming process is not required. Therefore, soldering can be easily performed in the same process as other components on the printed wiring board. With respect to C, no mold is required, the mounting surface levels of chip parts, connectors, etc. are the same, wiring is easy, electrical insulation is maintained, and the positional accuracy of each part is easy. In addition, the encapsulation can be performed by using an insulator enclosure, which can be simplified by only surface encapsulation. As for d, the lower part of the chip component is in contact with the mounting surface of the printed wiring board directly through the metal piece, and the heat dissipation effect is great. As for e, the formation of the metal film on the insulating piece facilitates the derivation of the external electrode for the small current (6).
【００１５】本発明の実施例は、本発明の要旨の範囲で
変形、変換、削除、付加等の変更をなし得るものであ
る。例えば、絶縁物包囲体を用いないで、電子回路装置
を構成し、プリント配線板上に実装した後、プリント配
線板全体を樹脂封止するようにしてもよい。又、チップ
部品、接続子、外部電極等は回路設計に応じて、種類、
数、形状等を選択し得るものである。The embodiment of the present invention can be modified, changed, deleted, added, etc. within the scope of the present invention. For example, the electronic circuit device may be configured without using the insulator enclosure, mounted on the printed wiring board, and then the entire printed wiring board may be resin-sealed. Also, chip parts, connectors, external electrodes, etc. are
The number, shape, etc. can be selected.
【００１６】[0016]
【発明の効果】以上説明したとおり、ベアチップを含む
各種チップ部品を搭載し、回路構成した面実装型電子回
路装置を外部電極の電気抵抗が小さく、放熱性の優れた
構造とし、プリント配線板への面実装により、電源機器
をはじめ、各種装置の小型化、低損失化、高信頼性化等
を実現し、産業上の利用効果、極めて大なるものであ
る。As described above, a surface mounting type electronic circuit device having various chip parts including a bare chip mounted thereon and having a circuit structure is provided with a structure in which the electric resistance of external electrodes is small and the heat dissipation is excellent, and the surface mounting type electronic circuit device is mounted on a printed wiring board. By surface mounting, various miniaturization, low loss, high reliability of various devices including power supply equipment are realized, and the industrial use effect is extremely large.
【図１】従来構造の断面構造図である。FIG. 1 is a sectional structural view of a conventional structure.
【図２】本発明の実施例の構造図で、（ａ）は平面図、
（ｂ）は正面図である。FIG. 2 is a structural view of an embodiment of the present invention, (a) is a plan view,
(B) is a front view.
【図３】本発明の実施例の斜視構造図である。FIG. 3 is a perspective structural view of an embodiment of the present invention.
【図４】本発明の他の実施例の平面構造図である。FIG. 4 is a plan structural view of another embodiment of the present invention.
１ ベアチップ １′ チップ部品（ベアチップを含む） ２ 外部電極 ３ 封止樹脂 （７） ４ 接続子 ５ 金属基板 ６ プリント配線板の実装面 ７ 第１の金属片 ８ 第１の絶縁片 ９ 第１の金属膜 １０ 第１の接続子 １１ 第２の絶縁片 １２ 第３の金属片 １３ 第２の接続子 １４ 絶縁物包囲体 １５ 第２の金属片 1 Bare Chip 1'Chip Part (Including Bare Chip) 2 External Electrode 3 Sealing Resin (7) 4 Connector 5 Metal Board 6 Mounting Surface of Printed Wiring Board 7 1st Metal Piece 8 1st Insulation Piece 9 1st Metal film 10 First connector 11 Second insulating piece 12 Third metal piece 13 Second connector 14 Insulator enclosure 15 Second metal piece
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9355−4Ｍ Ｈ０１Ｌ 23/12 Ｌ 25/04 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 9355-4M H01L 23/12 L 25/04 Z
Claims (3)
合し、かつ、第１の絶縁片に第１の金属膜を被着する
か、又は第１の絶縁片に第２の金属片を接合して形成し
た基板の第１の金属片上にチップ部品を装着し、又第１
の金属膜上、又は第２の金属片上にチップ部品からの第
１の接続子を装着するようにし、第１の金属片を第１の
外部電極とし、第１の金属膜、又は第２の金属片を第２
の外部電極としたことを特徴とする面実装型電子回路装
置。1. A first metal piece and a first insulating piece are joined at a side surface, and a first metal film is adhered to the first insulating piece, or a second metal piece is attached to the first insulating piece. The chip component is mounted on the first metal piece of the substrate formed by joining the metal pieces of
The first connector from the chip component is mounted on the metal film or the second metal piece, and the first metal piece serves as the first external electrode, and the first metal film or the second metal piece is used. Second piece of metal
A surface-mount type electronic circuit device characterized by being used as an external electrode of.
反対側面に第２の絶縁片を接合し、かつ、第２の絶縁片
に第２の金属膜上を被着するか、又は第２の絶縁片に第
３の金属片を接合して形成した基板の第２の金属膜上、
又は第３の金属片上にチップ部品からの第２の接続子を
装着するようにし、第２の金属膜、又は第３の金属片を
第３の外部電極としたことを特徴とする請求項１の面実
装型電子回路装置。2. A method of bonding a second insulating piece to the opposite side surface of the first metal piece to which the first insulating piece is bonded, and depositing the second insulating film on the second metal film. , Or on the second metal film of the substrate formed by joining the third metal piece to the second insulating piece,
Alternatively, the second connector from the chip component is mounted on the third metal piece, and the second metal film or the third metal piece is used as the third external electrode. Surface mount electronic circuit device.
の周辺部に絶縁物包囲体を形成し、絶縁物包囲体内部を
絶縁物封止したことを特徴とする請求項１又は請求項２
の面実装型電子回路装置。3. The insulator enclosure is formed in the periphery of the substrate surface on which the chip component and the connector are mounted, and the inside of the insulator enclosure is sealed with an insulator.
Surface mount electronic circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4313966A JP2879503B2 (en) | 1992-10-29 | 1992-10-29 | Surface mount type electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4313966A JP2879503B2 (en) | 1992-10-29 | 1992-10-29 | Surface mount type electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06151632A true JPH06151632A (en) | 1994-05-31 |
| JP2879503B2 JP2879503B2 (en) | 1999-04-05 |
Family
ID=18047630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4313966A Expired - Fee Related JP2879503B2 (en) | 1992-10-29 | 1992-10-29 | Surface mount type electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2879503B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747875A (en) * | 1993-09-08 | 1998-05-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor power module with high speed operation and miniaturization |
-
1992
- 1992-10-29 JP JP4313966A patent/JP2879503B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5747875A (en) * | 1993-09-08 | 1998-05-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor power module with high speed operation and miniaturization |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2879503B2 (en) | 1999-04-05 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |