JPH06216492A - Electronic device - Google Patents

Electronic device

Info

Publication number
JPH06216492A
JPH06216492A JP5008201A JP820193A JPH06216492A JP H06216492 A JPH06216492 A JP H06216492A JP 5008201 A JP5008201 A JP 5008201A JP 820193 A JP820193 A JP 820193A JP H06216492 A JPH06216492 A JP H06216492A
Authority
JP
Japan
Prior art keywords
wiring board
hole
wiring
electronic
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5008201A
Other languages
Japanese (ja)
Inventor
Tatsushi Kudo
達志 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Akita Electronics Systems Co Ltd
Original Assignee
Hitachi Ltd
Akita Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Akita Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP5008201A priority Critical patent/JPH06216492A/en
Publication of JPH06216492A publication Critical patent/JPH06216492A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain an electronic device wherein the packaging density of an electronic component in a wiring board is high by a method wherein the electronic component is mounted in a through hole and on a film board having a wiring board structure closing the through hole. CONSTITUTION:A through hole 4 is formed at a desired part in a wiring board 1, film boards 5, 6 are pasted on the surface and the back of the wiring board 1 so as to close it. Solders 12 are formed on desired surfaces of wiring layers 10, and they are bonded to wiring layers 2 on the wiring board 1. Thereby, the film boards 5, 6 are pasted on the wiring board 1 so as to close the through hole 4. Then, a semiconductor chip 7 is fixed, via a silver paste 16, to a chip mounting pad 5 formed of the wiring layer 10 on the surface of the film board 6 inside the through hole 4, and its electrodes and the desired wiring layer 10 on the surface of the film board 6 are connected electrically by wires 17. Consequently, the through hole is closed by the film boards composed of a wiring board structure, and an electronic component is mounted on the film board inside the through hole. Consequently, the packaging density of the electronic component can be enhanced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子装置、たとえば配線
基板に多数の電子部品を実装した混成集積回路装置等の
電子装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, for example, an electronic device such as a hybrid integrated circuit device in which a large number of electronic components are mounted on a wiring board.

【0002】[0002]

【従来の技術】トランジスタ,ダイオードのような単体
あるいはIC(集積回路装置),LSI(大規模集積回
路装置)等の半導体装置にあっては、そのパッケージ形
態は配線基板に実装する形態によって挿入型や面実装型
(表面実装型)に大別される。たとえば、工業調査会発
行「プラスチック」1988年3月号、同年3月1日発行、
P78〜P84には、半導体パッケージの種類および代表的
なパッケージ外観が示されている。代表的なパッケージ
としては、プラスチックDIP(Dual Inline Packag
e),プラスチックSIP(Single Inline Package),プ
ラスチックフラット,PLCC(Plastic Leaded Chip
Carrier),ヘーメチックシール,サーディップ,ピング
リッドアレイ,セラミックDIP,セラミックフラッ
ト,LCC(Leadless Chip Carrier),プラスチックモ
ールドが記載されている。
2. Description of the Related Art In a semiconductor device such as a transistor or a diode, or a semiconductor device such as an IC (integrated circuit device) or an LSI (large-scale integrated circuit device), its package form is an insertion type depending on a form mounted on a wiring board. And surface mount type (surface mount type). For example, March 1988 issue of "Plastics" issued by the Industrial Research Board, issued on March 1, 1988,
The types of semiconductor packages and typical package appearances are shown in P78 to P84. A typical package is a plastic DIP (Dual Inline Packag).
e), plastic SIP (Single Inline Package), plastic flat, PLCC (Plastic Leaded Chip)
Carrier), hermetic seal, cerdip, pin grid array, ceramic DIP, ceramic flat, LCC (Leadless Chip Carrier), and plastic mold.

【0003】一方、電子機器は、機能面から高密度実装
化が、実装面から軽量化,小型化,薄型化が要請されて
いる。また、電子部品の製造コストの低減のために、パ
ッケージ形態は材料が安くかつ生産性が良好な樹脂(レ
ジン)によるレジンパッケージ(プラスチックパッケー
ジ)が多用されている。小型・薄型のパッケージについ
ては、日立評論社発行「日立評論」1992年第3号、平成
4年3月25日発行、P75〜P80に記載されている。この
文献には、より小型・薄型のパッケージとして、TSO
P(Thin Small Outline Package),SSOP(Shrink
Small OutlinePackage),TQFP(Thin Quad Flat
Package),STZIP(Shrink ThinZigzag Inline Pa
ckage)が開示されている。また、SOP(Small Outline
Package)はパッケージの2辺にアウターリードを配置
し、QFP(Thin Quad Flat Package)はパッケージの
4辺にアウターリードを配置した構造となっている。そ
して、TSOP,TQFPはレジン(プラスチック)か
らなるパッケージの本体厚さが1mmに薄型化されてい
る。また、日経BP社発行「日経マイクロデバイス」19
91年2月号、同年2月1日発行、P65には、TAB(Ta
pe Automated Bonding)をトランスファ・モールドして
パッケージの厚さを0.5mmとした薄型パッケージが
紹介されている。
On the other hand, electronic devices are required to have high-density mounting in terms of functions, and to be lightweight, downsized, and thin in terms of mounting. Further, in order to reduce the manufacturing cost of electronic components, a resin package (plastic package) made of a resin (resin) that is inexpensive and has high productivity is often used as a package form. The small and thin packages are described in "Hitachi Hyoron", No. 3, 1992, issued by Hitachi Hyoronsha, March 75, 1992, P75 to P80. This document describes TSO as a smaller and thinner package.
P (Thin Small Outline Package), SSOP (Shrink
Small Outline Package, TQFP (Thin Quad Flat)
Package), STZIP (Shrink ThinZigzag Inline Pa
ckage) is disclosed. In addition, SOP (Small Outline
Package) has outer leads on two sides of the package, and QFP (Thin Quad Flat Package) has outer leads on the four sides of the package. The TSOP and TQFP are made of a resin (plastic) package having a body thickness of 1 mm. In addition, Nikkei BP's "Nikkei Micro Device" 19
Issued on February 1, 1991, February 1, the same year. P65 contains TAB (Ta
pe Automated Bonding) has been introduced, and a thin package with a package thickness of 0.5 mm has been introduced.

【0004】また、日経BP社発行「日経マイクロデバ
イス」1989年2月号、同年2月1日発行、P15には、両
面に銅箔を有する両面TABテープが紹介されている。
このTABテープのスルー・ホールは、50μm径とな
っている。
Also, "Nikkei Microdevice", February 1989, published by Nikkei BP, published February 1, 1989, P15 introduces a double-sided TAB tape having copper foils on both sides.
The through hole of this TAB tape has a diameter of 50 μm.

【0005】他方、工業調査会発行「電子材料」1984年
9月号、同年9月1日発行、P64には、一般のフラット
・パッケージにおける端子形状の種類として、(a)J
型リード(Rolled-under) 、(b)ガルウィング (Gull
-wing)、(c)バットリード(Butt-lead)、(d)フラ
ットリード (Flat lead)がある旨記載されている。
On the other hand, "Electronic Materials" issued by the Industrial Research Institute, September 1984 issue, issued September 1, 1984, P64 shows (a) J as the type of terminal shape in a general flat package.
Rolled-under, (b) Gull wing
-Wing), (c) Butt-lead, and (d) Flat lead.

【0006】また、工業調査会発行「電子材料」1987年
7月号、同年7月1日発行、P115〜P120には、プリント
基板の貫通穴にチップ部品(メルフ部品)を縦にして挿
入して収納し、両面パターンにより、チップ部品とパタ
ーンを導電接続してプリント基板を組み立てる実装構造
(チップインボード)が開示されている。
In addition, the "Electronic Materials" issued by the Industrial Research Institute, July 1987 issue, July 1, the same year, P115-P120, insert the chip component (Melph component) vertically into the through hole of the printed circuit board. There is disclosed a mounting structure (chip-in-board) in which a printed circuit board is assembled by accommodating the components and conductively connecting the chip component and the pattern by a double-sided pattern.

【0007】[0007]

【発明が解決しようとする課題】多層プリント基板を使
用した電子回路では、部品実装の多くはプリント基板の
表裏面になされている。しかし、配線基板の表裏面に電
子部品を搭載する構造では、電子部品の電極部分を接続
する電極面(ランド等)と、これら電極面に繋がる配線
(配線層)の引き回しによる配線パターン面積の増大に
よって、限られたスペース内での実装密度の向上を図る
ことには限界がある。そこで、従来、前記文献に示すよ
うに、プリント基板に貫通穴を設け、この貫通穴にメル
フ部品を挿入した構造等が開発されている。本発明も配
線基板の貫通穴内に電子部品を実装する思想の技術に関
する。
In an electronic circuit using a multilayer printed circuit board, many parts are mounted on the front and back surfaces of the printed circuit board. However, in the structure in which electronic components are mounted on the front and back surfaces of the wiring board, the wiring pattern area increases due to the wiring of the electrode surfaces (lands, etc.) connecting the electrode parts of the electronic components and the wiring (wiring layer) connected to these electrode surfaces. Therefore, there is a limit in improving the packaging density in a limited space. Therefore, conventionally, as shown in the above-mentioned document, a structure in which a through hole is provided in a printed board and a melf component is inserted into the through hole has been developed. The present invention also relates to the technology of the idea of mounting an electronic component in the through hole of the wiring board.

【0008】本発明の目的は、配線基板における電子部
品の実装密度の高い電子装置を提供することにある。本
発明の前記ならびにそのほかの目的と新規な特徴は、本
明細書の記述および添付図面からあきらかになるであろ
う。
An object of the present invention is to provide an electronic device having a high mounting density of electronic components on a wiring board. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

【0009】[0009]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。すなわち、本発明の電子装置は、配
線基板に設けた貫通穴に電子部品を装着してなる電子装
置であって、前記配線基板の両面には配線基板との間で
電子回路を形成するように電気的に接続される配線基板
構造のフィルム基板が張り付けられている。また、前記
貫通穴内のフィルム基板には半導体チップが固定されて
いるとともに、この半導体チップの電極とフィルム基板
の導体層は導電性のワイヤで電気的に接続され、かつ半
導体チップやワイヤ等は樹脂で封止されている。また、
配線基板の貫通穴を塞ぐフィルム基板部分には、電子部
品が搭載されている。
The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the electronic device of the present invention is an electronic device in which an electronic component is mounted in a through hole provided in a wiring board, and an electronic circuit is formed between the wiring board and both surfaces of the wiring board. A film substrate having a wiring substrate structure that is electrically connected is attached. A semiconductor chip is fixed to the film substrate in the through hole, the electrodes of the semiconductor chip and the conductor layer of the film substrate are electrically connected by a conductive wire, and the semiconductor chip, the wire, and the like are made of resin. It is sealed with. Also,
Electronic components are mounted on the film substrate portion that closes the through holes of the wiring substrate.

【0010】本発明の他の実施例の電子装置は、配線基
板に設けた貫通穴に電子部品を装着してなる電子装置で
あって、前記配線基板の両面には配線基板との間で電子
回路を形成するように電気的に接続される配線基板構造
のフィルム基板が張り付けられている。配線基板の貫通
穴に挿入される電子部品は、その周面に複数の電極端子
が設けられている。これらの電極端子は前記貫通穴の側
壁に設けられた配線層に接合材を介して電気的に接続さ
れてい。また、配線基板の貫通穴を塞ぐフィルム基板部
分には、電子部品が搭載されている。
An electronic device according to another embodiment of the present invention is an electronic device in which electronic parts are mounted in through holes provided in a wiring board, and an electronic device is provided between the wiring board and both sides of the wiring board. A film substrate of a wiring substrate structure is attached, which is electrically connected to form a circuit. The electronic component inserted into the through hole of the wiring board is provided with a plurality of electrode terminals on its peripheral surface. These electrode terminals are electrically connected to a wiring layer provided on the side wall of the through hole via a bonding material. Electronic parts are mounted on the film substrate portion that closes the through holes of the wiring substrate.

【0011】本発明の他の実施例の電子装置は、配線基
板に設けた貫通穴に電子部品のパッケージ部分を挿入す
るとともに、パッケージの周面から突出するリード(電
極端子)を配線基板の配線層に接合材を介して電気的に
接続させた構造となっている。そして、たとえば、前記
貫通穴には上下に重ねて2つの電子部品のパッケージが
挿入され、上方の電子部品のリードは配線基板の上面の
配線層に電気的に接続され、下方の電子部品のリードは
配線基板の下面の配線層に電気的に接続されている。ま
た、貫通穴の外側には貫通穴に挿入された電子部品を跨
ぐようにして電子部品が配置実装されている。
In an electronic device according to another embodiment of the present invention, a package portion of an electronic component is inserted into a through hole provided in a wiring board, and leads (electrode terminals) protruding from the peripheral surface of the package are wired on the wiring board. The structure is such that the layers are electrically connected via a bonding material. Then, for example, the packages of two electronic components are vertically stacked and inserted into the through hole, the leads of the upper electronic component are electrically connected to the wiring layer on the upper surface of the wiring board, and the leads of the lower electronic component are connected. Are electrically connected to the wiring layer on the lower surface of the wiring board. In addition, electronic components are arranged and mounted outside the through holes so as to straddle the electronic components inserted in the through holes.

【0012】[0012]

【作用】本発明の電子装置は、配線基板に設けらた貫通
穴に電子部品が装着されているとともに、貫通穴を塞ぐ
配線基板構造のフィルム基板上にも電子部品が実装され
ていることから、実装密度が向上する。
In the electronic device of the present invention, the electronic parts are mounted in the through holes provided in the wiring board, and the electronic parts are also mounted on the film substrate of the wiring board structure that closes the through holes. , Mounting density is improved.

【0013】本発明の他の実施例における電子部品のパ
ッケージを配線基板の貫通穴に挿入する構造では、パッ
ケージ部分が貫通穴に挿入されていること、また貫通穴
部分を跨ぐようにして他の電子部品が実装されているこ
とによって、実装密度向上が達成できる。特に、一つの
貫通穴に2つの電子部品のパッケージが重ねて挿入され
る場合には、実装密度はより高くなる。
In the structure of inserting the package of the electronic component into the through hole of the wiring board according to another embodiment of the present invention, the package portion is inserted into the through hole, and the other portion is formed by straddling the through hole portion. The mounting density can be improved by mounting the electronic components. In particular, when two electronic component packages are superposedly inserted into one through hole, the mounting density becomes higher.

【0014】[0014]

【実施例】以下図面を参照して本発明の一実施例につい
て説明する。図1は本発明の一実施例による電子装置の
要部を示す断面図、図2〜図5は本発明の電子装置の製
造各工程における図であって、図2は電子装置組立の基
本部材となる配線基板を示す断面図、図3は配線基板の
下面にフィルム基板を張り付けた状態を示す断面図、図
4は配線基板の下面のフィルム基板に半導体チップを取
り込つけワイヤボンディングしかつ封止した状態を示す
断面図、図5は配線基板の上面にフィルム基板を張り付
けた状態を示す断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a main part of an electronic device according to an embodiment of the present invention, FIGS. 2 to 5 are views showing respective steps of manufacturing the electronic device of the present invention, and FIG. 2 is a basic member for assembling the electronic device. FIG. 3 is a cross-sectional view showing a wiring board to be a wiring board, FIG. 3 is a cross-sectional view showing a state where a film board is attached to the lower surface of the wiring board, and FIG. FIG. 5 is a sectional view showing a stopped state, and FIG. 5 is a sectional view showing a state in which a film substrate is attached to an upper surface of the wiring substrate.

【0015】本発明の電子装置は、配線基板に複数の電
子部品を実装してなる混成集積回路構造の電子装置であ
る。図1に本発明の一実施例による電子装置の要部を示
す断面図を示す。本発明の電子装置における配線基板1
は、多層構造の配線基板であって、ガラス・エポキシ樹
脂からなるプリント基板や、セラミック基板等で形成さ
れている。この実施例では、たとえば、配線基板1は3
層構造となり、層と層との間には、図示はしないが所望
パターンの導体層が設けられている。また、配線基板1
の表裏面にも配線層2が設けられている。また、前記配
線層2や導体層は、所望箇所でスルーホールに充填した
導体3によって電気的に接続されている。配線基板1の
厚さは、配線基板1を構成する層の数等によって種々異
なるが、この実施例では1mm程度とする。配線基板1
の表裏面には、図示はしないが受動部品としてのチップ
コンデンサーやチップ抵抗等のチップ部品が実装される
とともに、能動部品としてのIC(集積回路装置),L
SI(大規模集積回路装置)等の半導体装置が実装され
ている。
The electronic device of the present invention is an electronic device having a hybrid integrated circuit structure in which a plurality of electronic components are mounted on a wiring board. FIG. 1 is a sectional view showing a main part of an electronic device according to an embodiment of the present invention. Wiring board 1 in the electronic device of the present invention
Is a wiring board having a multilayer structure, and is formed of a printed board made of glass / epoxy resin, a ceramic board, or the like. In this embodiment, for example, the wiring board 1 has three
It has a layered structure, and although not shown, a conductor layer having a desired pattern is provided between the layers. Also, the wiring board 1
The wiring layer 2 is also provided on the front and back surfaces of the. Further, the wiring layer 2 and the conductor layer are electrically connected by a conductor 3 filling a through hole at a desired position. The thickness of the wiring board 1 varies depending on the number of layers forming the wiring board 1 and the like, but is about 1 mm in this embodiment. Wiring board 1
Although not shown, chip parts such as chip capacitors and chip resistors as passive parts are mounted on the front and back surfaces of the IC, and ICs (integrated circuit devices) and L as active parts are mounted.
A semiconductor device such as SI (Large Scale Integrated Circuit Device) is mounted.

【0016】一方、これが本発明の特徴の一つである
が、配線基板1の所望部分には貫通穴4が設けられてい
るとともに、この貫通穴4を塞ぐように配線基板1の表
裏面にはフィルム基板5、6が張り付けられ、かつ貫通
穴4内の下面側のフィルム基板6部分に電子部品、すな
わち、半導体チップ7が固定されている。前記フィルム
基板5、6は、絶縁性のポリイミド樹脂からなる厚さ7
5〜125μmのフィルム9と、このフィルム9の表裏
面に設けられた35μm厚さの配線層10と、フィルム
9の表裏面の配線層10を所定箇所で電気的に接続する
スルーホールに充填された導体11とからなっている。
また、前記フィルム基板5、6の配線層10の所望表面
箇所には半田12が設けられている。この半田12は配
線基板1の配線層2に接着されている。これによってフ
ィルム基板5、6が、前記貫通穴4を塞ぐように配線基
板1に張り付けられることになる。したがって、前記貫
通穴4の上下にもフィルム基板5、6の存在によって配
線層10が位置するようになる。前記フィルム基板5、
6は配線基板1の所望箇所に設けられている。前記フィ
ルム9は薄く、かつまた配線層10や半田12の厚さも
それぞれ数十μm程度と薄いため、フィルム基板5、6
が張り付けられた配線基板1部分はそれ程厚くならな
い。なお、フィルム基板5、6は配線基板1の全面に設
けても良い。
On the other hand, this is one of the features of the present invention. Through holes 4 are provided at desired portions of the wiring board 1, and the front and back surfaces of the wiring board 1 are closed so as to close the through holes 4. The film substrates 5 and 6 are attached, and the electronic component, that is, the semiconductor chip 7 is fixed to the film substrate 6 portion on the lower surface side in the through hole 4. The film substrates 5 and 6 have a thickness 7 made of an insulating polyimide resin.
A film 9 having a thickness of 5 to 125 μm, a wiring layer 10 having a thickness of 35 μm provided on the front and back surfaces of the film 9, and a through hole for electrically connecting the wiring layer 10 on the front and back surfaces of the film 9 at predetermined locations are filled. And a conductor 11.
Further, solder 12 is provided on a desired surface portion of the wiring layer 10 of the film substrates 5 and 6. The solder 12 is adhered to the wiring layer 2 of the wiring board 1. As a result, the film substrates 5 and 6 are attached to the wiring substrate 1 so as to close the through holes 4. Therefore, the wiring layer 10 is positioned above and below the through hole 4 due to the presence of the film substrates 5 and 6. The film substrate 5,
6 is provided at a desired portion of the wiring board 1. Since the film 9 is thin and the wiring layer 10 and the solder 12 are each as thin as several tens of μm, the film substrates 5 and 6 are formed.
The portion of the wiring board 1 to which is adhered does not become so thick. The film substrates 5 and 6 may be provided on the entire surface of the wiring substrate 1.

【0017】前記貫通穴4内において、配線基板1の下
面に張り付けられたフィルム基板6の上面の配線層10
によって形成されたチップ搭載パッド15には、半導体
チップ7が銀ペースト16を介して固定されている。ま
た、半導体チップ7の図示しない電極と、フィルム基板
6の上面の所望配線層10は、導電性のワイヤ17によ
って電気的に接続されている。また、前記半導体チップ
7,ワイヤ17等はポッティングによって形成された樹
脂19で被われている。これにより電子部品14が実装
されることになる。前記半導体チップ7は200〜40
0μm程度の厚さとなることから、貫通穴4の上部に突
出することなく実装されている。
The wiring layer 10 on the upper surface of the film substrate 6 attached to the lower surface of the wiring substrate 1 in the through hole 4 is formed.
The semiconductor chip 7 is fixed to the chip mounting pad 15 formed by using a silver paste 16. Further, an electrode (not shown) of the semiconductor chip 7 and the desired wiring layer 10 on the upper surface of the film substrate 6 are electrically connected by a conductive wire 17. The semiconductor chip 7, the wires 17 and the like are covered with a resin 19 formed by potting. As a result, the electronic component 14 is mounted. The semiconductor chip 7 is 200-40
Since the thickness is about 0 μm, it is mounted on the through hole 4 without protruding.

【0018】他方、前記配線基板1の表裏面には受動部
品や能動部品が多数実装されているが、前記貫通穴4を
塞ぐフィルム基板5、6を利用して、貫通穴4の上下部
分にも電子部品20が実装されている。図1に示す電子
部品20は、表面実装型の樹脂封止型半導体装置であ
り、パッケージ21の周面から突出するリード22はガ
ルウィング型となっている。この電子部品20は、パッ
ケージ21の厚さが1.0mmのTSOPである。この
TSOPは、配線基板1の上面では、リード22が貫通
穴4上のフィルム基板5部分に実装された例を示し、配
線基板1の下面では貫通穴4を跨ぐようにフィルム基板
6に実装された例を示す。
On the other hand, although many passive components and active components are mounted on the front and back surfaces of the wiring board 1, the film substrates 5 and 6 for closing the through hole 4 are used to form the upper and lower portions of the through hole 4. Also, the electronic component 20 is mounted. The electronic component 20 shown in FIG. 1 is a surface-mounting resin-sealed semiconductor device, and the leads 22 protruding from the peripheral surface of the package 21 are gull-wing type. The electronic component 20 is a TSOP having a package 21 having a thickness of 1.0 mm. This TSOP shows an example in which the lead 22 is mounted on the film substrate 5 portion on the through hole 4 on the upper surface of the wiring substrate 1, and is mounted on the film substrate 6 so as to straddle the through hole 4 on the lower surface of the wiring substrate 1. Here is an example.

【0019】このような実装構造の電子装置の製造につ
いて、その要部を図2〜図5を参照しながら説明する。
図2に示すように、配線基板1が用意される。この配線
基板1は、前記のように多層構造の配線基板であって、
ガラス・エポキシ樹脂からなるプリント基板や、セラミ
ック基板等で形成されていて、たとえば3層構造とな
り、層と層との間には、図示はしないが所望パターンの
導体層が設けられている。また、配線基板1の表裏面に
も配線層2が設けられている。また、前記配線層2や導
体層は、所望箇所でスルーホールに充填した導体3によ
って電気的に接続されている。配線基板1の厚さは、配
線基板1を構成する層の数等によって種々異なるが、こ
の実施例では1mm程度となっている。また、前記配線
基板1の所望部分には貫通穴4が設けられている。この
貫通穴4内には、電子部品が配置されるようになる。
Manufacture of an electronic device having such a mounting structure will be described with reference to FIGS. 2 to 5.
As shown in FIG. 2, the wiring board 1 is prepared. This wiring board 1 is a wiring board having a multilayer structure as described above,
It is formed of a printed circuit board made of glass / epoxy resin, a ceramic circuit board, or the like, and has, for example, a three-layer structure, and a conductor layer of a desired pattern is provided between the layers, although not shown. Wiring layers 2 are also provided on the front and back surfaces of the wiring board 1. Further, the wiring layer 2 and the conductor layer are electrically connected by a conductor 3 filling a through hole at a desired position. Although the thickness of the wiring board 1 varies depending on the number of layers constituting the wiring board 1 and the like, it is about 1 mm in this embodiment. Further, a through hole 4 is provided in a desired portion of the wiring board 1. Electronic components are arranged in the through holes 4.

【0020】つぎに、図3に示すように、配線基板1の
下面(裏面)には、フィルム基板6が張り付けられる。
フィルム基板6は、前記のように絶縁性のポリイミド樹
脂からなる厚さ75〜125μmのフィルム9と、この
フィルム9の表裏面に設けられた35μm厚さの配線層
10と、フィルム9の表裏面の配線層10を所定箇所で
電気的に接続するスルーホールに充填された導体11と
からなっている。また、前記フィルム基板6の配線層1
0の表面の所望箇所には半田12が設けられている。そ
こで、このようなフィルム基板6を配線基板1の下面に
張り付ける際は、フィルム基板6に配線基板1を相対的
に位置決めしかつ重ね合わせ、フィルム基板6の配線層
10に被着された半田12を再溶融することによって、
フィルム基板6を配線基板1に張り付ける。このフィル
ム基板6は局所的に設けるが、配線基板1の全面に設け
ても良い。
Next, as shown in FIG. 3, a film substrate 6 is attached to the lower surface (back surface) of the wiring board 1.
The film substrate 6 includes a film 9 made of an insulating polyimide resin having a thickness of 75 to 125 μm, a wiring layer 10 having a thickness of 35 μm provided on the front and back surfaces of the film 9, and front and back surfaces of the film 9. And a conductor 11 filled in a through hole for electrically connecting the wiring layer 10 at a predetermined position. In addition, the wiring layer 1 of the film substrate 6
Solder 12 is provided at a desired position on the surface of No. 0. Therefore, when such a film substrate 6 is attached to the lower surface of the wiring substrate 1, the wiring substrate 1 is relatively positioned and superposed on the film substrate 6, and the solder applied to the wiring layer 10 of the film substrate 6 is attached. By remelting 12,
The film substrate 6 is attached to the wiring substrate 1. Although the film substrate 6 is provided locally, it may be provided on the entire surface of the wiring substrate 1.

【0021】配線基板1の下面に張り付けられたフィル
ム基板6は、その上面の貫通穴4側に配線層10や配線
層10からなるチップ搭載パッド15が設けられてい
る。そこで、図4に示すように、前記チップ搭載パッド
15に銀ペースト16によって半導体チップ7を固定す
る。銀ペースト16による半導体チップ7の固定は、銀
ペースト16を120〜150℃に加熱することによっ
て行われる。つぎに、前記半導体チップ7の図示しない
電極と、フィルム基板6の配線層10とを導電性のワイ
ヤ17で接続する。このワイヤボンディングにおいて、
配線層10におけるボンディング位置と、貫通穴4の周
壁との間隔は、たとえば、500μm程度取って置け
ば、ボンディングツールが貫通穴4の周壁に接触するよ
うなこともない。つぎに、ポッティングによって半導体
チップ7やワイヤ17等を樹脂19で被うとともに、こ
の樹脂19をキュアーして硬化させる。
The film substrate 6 attached to the lower surface of the wiring substrate 1 is provided with the wiring layer 10 and the chip mounting pad 15 formed of the wiring layer 10 on the upper surface side of the through hole 4 side. Therefore, as shown in FIG. 4, the semiconductor chip 7 is fixed to the chip mounting pad 15 with the silver paste 16. The semiconductor chip 7 is fixed with the silver paste 16 by heating the silver paste 16 to 120 to 150 ° C. Next, an electrode (not shown) of the semiconductor chip 7 and the wiring layer 10 of the film substrate 6 are connected by a conductive wire 17. In this wire bonding,
If the distance between the bonding position on the wiring layer 10 and the peripheral wall of the through hole 4 is about 500 μm, the bonding tool will not come into contact with the peripheral wall of the through hole 4. Next, the semiconductor chip 7, the wires 17 and the like are covered with the resin 19 by potting, and the resin 19 is cured and cured.

【0022】つぎに、図5に示すように、配線基板1の
上面にフィルム基板5を張り付ける。フィルム基板5は
前記フィルム基板6と同様な構造となるが、配線層10
や導体11等による配線パターンは必ずしも同じではな
い。フィルム基板5は、その下面の配線層10にあらか
じめ設けられた半田12を再溶融して配線基板1の配線
層2に接続させることによって配線基板1に接続され
る。
Next, as shown in FIG. 5, the film substrate 5 is attached to the upper surface of the wiring substrate 1. The film substrate 5 has the same structure as the film substrate 6, except that the wiring layer 10
The wiring patterns of the conductors 11 and the like are not necessarily the same. The film substrate 5 is connected to the wiring substrate 1 by remelting the solder 12 provided in advance on the wiring layer 10 on the lower surface of the film substrate 5 and connecting it to the wiring layer 2 of the wiring substrate 1.

【0023】つぎに、配線基板1の表裏面にTSOPか
らなる電子部品20を実装する。電子部品20は、リー
ド22にあらかじめ被着されていた半田25の再溶融に
よって配線基板1に実装される。これにより、図1に示
すような実装構造が形成される。そこで、この配線基板
1を所定のパッケージに組み込むことによって所望の電
子装置が製造されることになる。
Next, the electronic parts 20 made of TSOP are mounted on the front and back surfaces of the wiring board 1. The electronic component 20 is mounted on the wiring board 1 by remelting the solder 25 previously attached to the leads 22. As a result, a mounting structure as shown in FIG. 1 is formed. Therefore, a desired electronic device is manufactured by incorporating this wiring board 1 into a predetermined package.

【0024】[0024]

【発明の効果】(1)本発明の電子装置は、配線基板に
貫通穴を設けるとともに、この貫通穴を配線基板構造か
らなるフィルム基板で塞ぎ、かつ貫通穴内のフィルム基
板上に電子部品を実装することから、実装密度が向上す
るという効果が得られる。
(1) In the electronic device of the present invention, a through hole is provided in the wiring board, the through hole is closed by a film substrate having a wiring board structure, and electronic parts are mounted on the film substrate in the through hole. As a result, the effect of improving the packaging density can be obtained.

【0025】(2)上記(1)により、本発明の電子装
置は、配線基板に貫通穴が設けられるが、この貫通穴を
フィルム基板で塞ぐことから、貫通穴の上下部分にも配
線層を延在させることができ、配線設計に支障を来さな
いという効果が得られる。
(2) According to the above (1), in the electronic device of the present invention, the wiring substrate is provided with the through hole. Since the through hole is closed by the film substrate, the wiring layer is also provided above and below the through hole. The effect of being able to extend and not hindering the wiring design is obtained.

【0026】(3)上記(1)により、本発明の電子装
置は、配線基板に貫通穴が設けられるが、この貫通穴を
フィルム基板で塞ぎ、かつ貫通穴の上下部分のフィルム
基板を利用して電子部品を実装することから、実装密度
向上が図れるという効果が得られる。
(3) According to the above (1), in the electronic device of the present invention, the wiring substrate is provided with the through hole. The through hole is closed by the film substrate, and the film substrates above and below the through hole are used. Since the electronic component is mounted by using the electronic component, the effect that the mounting density can be improved can be obtained.

【0027】(4)上記(1)〜(3)により、本発明
によれば、薄型でかつ実装密度の高い電子装置を提供す
ることができるという相乗効果が得られる。
(4) Due to the above (1) to (3), according to the present invention, there is a synergistic effect that it is possible to provide an electronic device which is thin and has a high packing density.

【0028】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない、たとえば、
前記実施例では、前記配線基板1の表裏面の配線層2お
よびフィルム基板5、6の表裏面の配線層10は露出構
造となっているが、所望配線層2,10部分を絶縁膜
(絶縁層)で被う構造としてもよい。
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, for example,
In the embodiment, the wiring layer 2 on the front and back surfaces of the wiring substrate 1 and the wiring layer 10 on the front and back surfaces of the film substrates 5 and 6 have an exposed structure, but the desired wiring layers 2 and 10 are covered with an insulating film (insulating film). The structure may be covered with layers.

【0029】図6は本発明の他の実施例による電子装置
の要部を示す断面図である。この実施例では、前記配線
基板1に設けられた貫通穴4の周壁に配線層2を設ける
とともに、前記貫通穴4内に周面に電極端子30を有す
る電子部品31を前記貫通穴4内に挿嵌する構造であ
る。この電子部品31は、絶縁性の配線基板32の上面
のチップ搭載パッド33上に半導体チップ34が固定さ
れる構造となっているとともに、前記半導体チップ34
の図示しない電極と、配線基板32上の配線層35が導
電性のワイヤ36で電気的に接続されている。また、前
記半導体チップ34やワイヤ36等は樹脂37で被われ
ている。前記配線基板32の上面の配線層35は、配線
基板32の周面にまで延在して電極端子30を形成して
いる。電極端子30と、前記貫通穴4の周壁の配線層2
は、電極端子30にあらかじめ設けられた半田39の再
溶融によって接続されている。貫通穴に挿嵌する電子部
品としては、他にLCCが適している。また、リード形
状がバットリードやJ型リードの表面実装型半導体装置
も貫通穴に挿嵌する電子部品として適している。この構
造でも、電子装置の実装密度向上が達成できる。
FIG. 6 is a sectional view showing an essential part of an electronic device according to another embodiment of the present invention. In this embodiment, the wiring layer 2 is provided on the peripheral wall of the through hole 4 provided in the wiring board 1, and the electronic component 31 having the electrode terminal 30 on the peripheral surface is provided in the through hole 4 in the through hole 4. It is a structure to be inserted. The electronic component 31 has a structure in which a semiconductor chip 34 is fixed on a chip mounting pad 33 on the upper surface of an insulating wiring board 32, and the semiconductor chip 34 is also provided.
The electrode (not shown) and the wiring layer 35 on the wiring board 32 are electrically connected by a conductive wire 36. The semiconductor chip 34, wires 36, etc. are covered with resin 37. The wiring layer 35 on the upper surface of the wiring board 32 extends to the peripheral surface of the wiring board 32 to form the electrode terminals 30. The electrode terminal 30 and the wiring layer 2 on the peripheral wall of the through hole 4
Are connected by remelting the solder 39 provided in advance on the electrode terminal 30. An LCC is also suitable as an electronic component to be inserted into the through hole. Further, a surface mount type semiconductor device whose lead shape is a butt lead or a J-type lead is also suitable as an electronic component to be inserted into the through hole. With this structure, it is possible to improve the packaging density of electronic devices.

【0030】図7は本発明の他の実施例による電子装置
の要部を示す断面図である。この実施例では、配線基板
1に設けた貫通穴4にTSOPからなる電子部品40の
パッケージ41部分を挿入するとともに、パッケージ4
1の周面から突出するリード(電極端子)42を配線基
板1の配線層2に半田43を介して接続してなるもので
ある。この例では、配線基板1の貫通穴4に、上下に重
ねて2つの電子部品40のパッケージ41が挿入され、
上方の電子部品40のリード42は配線基板1の上面の
配線層2に電気的に接続され、下方の電子部品40のリ
ード42は配線基板1の下面の配線層2に電気的に接続
されている。また、貫通穴4の外側には、貫通穴4に挿
入された電子部品40を跨ぐようにして他の電子部品2
0が実装されている。前記配線基板1の厚さは1mm程
度であり、貫通穴4内に挿入されるパッケージ41の厚
さは0.5mm、貫通穴4を跨ぐ電子部品20のパッケ
ージの厚さは1.0mm程度である。この実施例におい
ても、実装密度の向上が達成できる。
FIG. 7 is a sectional view showing an essential part of an electronic device according to another embodiment of the present invention. In this embodiment, the package 41 portion of the electronic component 40 made of TSOP is inserted into the through hole 4 provided in the wiring board 1 and the package 4
The leads (electrode terminals) 42 protruding from the peripheral surface of the wiring board 1 are connected to the wiring layer 2 of the wiring board 1 via solder 43. In this example, the packages 41 of the two electronic components 40 are inserted vertically into the through hole 4 of the wiring board 1 and
The lead 42 of the upper electronic component 40 is electrically connected to the wiring layer 2 on the upper surface of the wiring board 1, and the lead 42 of the lower electronic component 40 is electrically connected to the wiring layer 2 on the lower surface of the wiring substrate 1. There is. Further, outside the through hole 4, the other electronic component 2 is arranged so as to straddle the electronic component 40 inserted in the through hole 4.
0 is implemented. The wiring board 1 has a thickness of about 1 mm, the package 41 inserted into the through hole 4 has a thickness of 0.5 mm, and the package of the electronic component 20 straddling the through hole 4 has a thickness of about 1.0 mm. is there. Also in this embodiment, an improvement in packaging density can be achieved.

【0031】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である混成集
積回路装置構造の電子装置の製造技術に適用した場合に
ついて説明したが、それに限定されるものではなく、た
とえば、限られたスペースで作られるメモリーカード,
ポケットベル,携帯電話,ビデオカメラなど、小型多機
能製品にも適用できる。本発明は少なくとも配線基板に
複数の電子部品を実装する電子装置には適用できる。
In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the electronic device having the hybrid integrated circuit device structure, which is the field of application in the background, has been described, but the invention is not limited thereto. Not, for example, a memory card made in a limited space,
It can also be applied to small multifunctional products such as pagers, mobile phones, and video cameras. The present invention can be applied to at least an electronic device in which a plurality of electronic components are mounted on a wiring board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による電子装置の要部を示す
断面図である。
FIG. 1 is a sectional view showing a main part of an electronic device according to an embodiment of the present invention.

【図2】本発明の一実施例による電子装置の製造におけ
る配線基板を示す断面図である。
FIG. 2 is a cross-sectional view showing a wiring board in the manufacture of an electronic device according to an embodiment of the present invention.

【図3】本発明の一実施例による電子装置の製造におい
て配線基板の下面にフィルム基板を張り付けた状態を示
す断面図である。
FIG. 3 is a cross-sectional view showing a state in which a film substrate is attached to the lower surface of a wiring board in the manufacture of an electronic device according to an embodiment of the present invention.

【図4】本発明の一実施例による電子装置の製造におい
て配線基板の下面のフィルム基板に半導体チップを取り
込つけワイヤボンディングしかつ封止した状態を示す断
面図である。
FIG. 4 is a cross-sectional view showing a state in which a semiconductor chip is incorporated in the film substrate on the lower surface of the wiring substrate, wire-bonded, and sealed in the manufacture of the electronic device according to the embodiment of the present invention.

【図5】本発明の一実施例による電子装置の製造におい
て配線基板の上面にフィルム基板を張り付けた状態を示
す断面図である。
FIG. 5 is a cross-sectional view showing a state in which a film substrate is attached to the upper surface of a wiring substrate in the manufacture of an electronic device according to an embodiment of the present invention.

【図6】本発明の他の実施例による電子装置の要部を示
す断面図である。
FIG. 6 is a sectional view showing an essential part of an electronic device according to another embodiment of the present invention.

【図7】本発明の他の実施例による電子装置の要部を示
す断面図である。
FIG. 7 is a sectional view showing an essential part of an electronic device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,32…配線基板、2,10,35…配線層、3,1
1…導体、4…貫通穴、5,6…フィルム基板、7,3
4…半導体チップ、9…フィルム、12,25,39,
43…半田、14,20,31,40…電子部品、1
5,33…チップ搭載パッド、16…銀ペースト、1
7,36…ワイヤ、19,37…樹脂、21,41…パ
ッケージ、22,42…リード、30…電極端子。
1, 32 ... Wiring board, 2, 10, 35 ... Wiring layer, 3, 1
1 ... Conductor, 4 ... Through hole, 5, 6 ... Film substrate, 7, 3
4 ... Semiconductor chip, 9 ... Film, 12, 25, 39,
43 ... Solder, 14, 20, 31, 40 ... Electronic component, 1
5, 33 ... Chip mounting pad, 16 ... Silver paste, 1
7, 36 ... Wire, 19, 37 ... Resin, 21, 41 ... Package, 22, 42 ... Lead, 30 ... Electrode terminal.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 配線基板に設けた貫通穴に電子部品を装
着してなる電子装置であって、前記配線基板の少なくと
も1面には配線基板との間で電子回路を形成するように
電気的に接続される配線基板構造のフィルム基板が張り
付けられ、かつ前記貫通穴内のフィルム基板には電子部
品が電子回路を形成するように実装されていることを特
徴とする電子装置。
1. An electronic device in which an electronic component is mounted in a through hole provided in a wiring board, wherein an electronic circuit is formed on at least one surface of the wiring board so as to form an electronic circuit with the wiring board. An electronic device, wherein a film substrate having a wiring substrate structure connected to the substrate is attached, and electronic components are mounted on the film substrate in the through hole so as to form an electronic circuit.
【請求項2】 配線基板に設けた貫通穴に電子部品を装
着してなる電子装置であって、前記配線基板の少なくと
も1面には配線基板との間で電子回路を形成するように
電気的に接続される配線基板構造のフィルム基板が張り
付けられているとともに、前記電子部品の周面には複数
の電極端子が設けられ、かつこれらの電極端子に対応し
かつ接合材を介して電気的に接続される配線層が前記貫
通穴の周壁面に設けられていることを特徴とする電子装
置。
2. An electronic device in which an electronic component is mounted in a through hole provided in a wiring board, wherein an electronic circuit is formed on at least one surface of the wiring board so as to form an electronic circuit with the wiring board. A film substrate having a wiring board structure connected to the electronic component is attached to the peripheral surface of the electronic component, and a plurality of electrode terminals are provided on the peripheral surface of the electronic component. An electronic device, wherein a wiring layer to be connected is provided on a peripheral wall surface of the through hole.
【請求項3】 配線基板に設けた貫通穴に電子部品を装
着してなる電子装置であって、前記貫通穴に電子部品の
パッケージ部分を挿入するとともに、パッケージの周面
から突出するリードを配線基板の配線層に接合材を介し
て電気的に接続させてなることを特徴とする電子装置。
3. An electronic device in which an electronic component is mounted in a through hole provided in a wiring board, wherein a package portion of the electronic component is inserted into the through hole and a lead protruding from a peripheral surface of the package is wired. An electronic device, which is electrically connected to a wiring layer of a substrate through a bonding material.
【請求項4】 前記貫通穴には上下に重ねて2つの電子
部品のパッケージが挿入され、上方の電子部品のリード
は配線基板の上面の配線層に電気的に接続され、下方の
電子部品のリードは配線基板の下面の配線層に電気的に
接続されていることを特徴とする請求項3記載の電子装
置。
4. The package of two electronic components is vertically inserted into the through hole, and the leads of the upper electronic component are electrically connected to the wiring layer on the upper surface of the wiring board, and the leads of the lower electronic component are inserted. The electronic device according to claim 3, wherein the lead is electrically connected to a wiring layer on a lower surface of the wiring board.
JP5008201A 1993-01-21 1993-01-21 Electronic device Pending JPH06216492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5008201A JPH06216492A (en) 1993-01-21 1993-01-21 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5008201A JPH06216492A (en) 1993-01-21 1993-01-21 Electronic device

Publications (1)

Publication Number Publication Date
JPH06216492A true JPH06216492A (en) 1994-08-05

Family

ID=11686656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5008201A Pending JPH06216492A (en) 1993-01-21 1993-01-21 Electronic device

Country Status (1)

Country Link
JP (1) JPH06216492A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0766505A2 (en) * 1995-09-29 1997-04-02 Allen-Bradley Company, Inc. Rigid-flex circuit board having a window for an insulated mounting area
EP1093326A2 (en) * 1999-10-15 2001-04-18 Japan Aviation Electronics Industry, Limited Printed-circuit board module
WO2007086152A1 (en) * 2006-01-26 2007-08-02 Matsushita Electric Industrial Co., Ltd. Substrate structure
WO2009104599A1 (en) * 2008-02-18 2009-08-27 日本電気株式会社 Electronic apparatus, mounting board laminated body and method of manufacturing electronic apparatus and mounting board laminated body

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0766505A2 (en) * 1995-09-29 1997-04-02 Allen-Bradley Company, Inc. Rigid-flex circuit board having a window for an insulated mounting area
EP0766505A3 (en) * 1995-09-29 1998-12-23 Allen-Bradley Company, Inc. Rigid-flex circuit board having a window for an insulated mounting area
EP1093326A2 (en) * 1999-10-15 2001-04-18 Japan Aviation Electronics Industry, Limited Printed-circuit board module
EP1093326A3 (en) * 1999-10-15 2002-05-22 Japan Aviation Electronics Industry, Limited Printed-circuit board module
WO2007086152A1 (en) * 2006-01-26 2007-08-02 Matsushita Electric Industrial Co., Ltd. Substrate structure
WO2009104599A1 (en) * 2008-02-18 2009-08-27 日本電気株式会社 Electronic apparatus, mounting board laminated body and method of manufacturing electronic apparatus and mounting board laminated body
JP5604876B2 (en) * 2008-02-18 2014-10-15 日本電気株式会社 Electronic device and manufacturing method thereof

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