JPH0730059A - Multichip module - Google Patents

Multichip module

Info

Publication number
JPH0730059A
JPH0730059A JP15326393A JP15326393A JPH0730059A JP H0730059 A JPH0730059 A JP H0730059A JP 15326393 A JP15326393 A JP 15326393A JP 15326393 A JP15326393 A JP 15326393A JP H0730059 A JPH0730059 A JP H0730059A
Authority
JP
Japan
Prior art keywords
semiconductor element
recess
external input
multi
chip module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15326393A
Other languages
Japanese (ja)
Inventor
Ryoichi Nagaoka
亮一 長岡
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP15326393A priority Critical patent/JPH0730059A/en
Publication of JPH0730059A publication Critical patent/JPH0730059A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)

Abstract

PURPOSE:To enable a multichip module mounted with a plurality of semiconductor elements to be enhanced in element mounting density and lessened in size. CONSTITUTION:Semiconductor element, connecting electrodes 4 and 5 are provided to the base of a recess 3 bored in a multilayer board 1 and the upside of the multilayer board 1 respectively, a semiconductor element 6 is housed in the recess 3, and a semiconductor element 8 is mounted on the board 1 bestriding the recess 3 so as to enhance semiconductor elements mounted on the multilayer board 1 in density. By this setup, a multichip module of this constitution can be enhanced to be two to three times as high in degree of integration as or lessened to be 1/2 to 1/3 as large in size as a conventional one.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体素子及びその他の電子素子を多数表面実装し、所定の電気配線で接続して形成されるマルチチップモジュールの構造に関する。 The present invention relates to a large number surface mounting the semiconductor elements and other electronic devices, to a structure of a multi-chip module is formed by connecting a predetermined electric wiring.

【0002】 [0002]

【従来の技術】従来のマルチチップモジュールは図5に示すように電気配線基板の1平面上に半導体素子を実装している構造が1般的である。 Conventional multi-chip module structure that a semiconductor element mounted on one plane of electrical wiring board as shown in FIG. 5 is one common. 多層基板は半導体素子間及び外部入出力端子間を接続する電気配線を有し基板の1平面上に半導体素子を実装し、対抗する面は外部入出力端子を設けるかまたは放熱用のフィンで構成される。 Multilayer substrate a semiconductor element mounted on one plane of the substrate has an electrical wiring for connecting the between the semiconductor elements and the external input and output terminals, opposing faces composed of fins for either or dissipating providing an external input and output terminal It is.
多層基板の必要な大きさは実装される半導体素子の数と大きさで決定される(例えば、特開平3−93259号公報参照)。 Required size of the multilayer substrate is determined by the number and size of the semiconductor element to be mounted (e.g., see Japanese Patent Laid-Open No. 3-93259).

【0003】 [0003]

【発明が解決しようとする課題】この従来のマルチチップモジュール構造では、基板の1平面で構成する半導体素子の大きさと個数で基板寸法が決定されるため、高集積化・小型化の要求に答えることが難しいという問題点があった。 [Problems that the Invention is to Solve In this conventional multi-chip module structure, since the substrate dimensions are determined by the size and number of the semiconductor elements constituting one plane of the substrate, answering the requirements of high integration and miniaturization it was a problem that it is difficult.

【0004】本発明は、このような従来の技術が有する問題点に着目してなされたもので、半導体素子実装密度の向上及びモジュールの小型化ができるようにしたマルチチップモジュールを提供することを目的としている。 [0004] The present invention has such has been made in view of the problems the prior art has, to provide a multi-chip module to allow miniaturization of the improving and modules of the semiconductor element mounting density it is an object.

【0005】 [0005]

【課題を解決するための手段】かかる目的を達成するための本発明の要旨とするところは、以下の2項に存する。 Means for Solving the Problems] It is an gist of the present invention for achieving the above object resides in the following two paragraphs.

【0006】[1] 半導体素子を含む複数の電子素子を表面に実装し、該電子素子に接続される電気配線が形成されているマルチチップモジュールにおいて、半導体素子(6、8)及び多層基板から成り、多層基板(1) [0006] [1] a plurality of electronic devices mounted on the surface including the semiconductor element, the multi-chip module electrical wiring is formed to be connected to the electronic element, a semiconductor element (6, 8) and a multilayer substrate made, multi-layer substrate (1)
には、半導体素子(6、8)を嵌合するための凹部(1)が複数個配設され、半導体素子接続用電極(4、 , The recess for fitting the semiconductor device (6,8) (1) is plural arranged, the semiconductor element connecting electrodes (4,
5)がパタ−ンニングされ、外部と入出力信号の受け渡しをするための外部入出力端子(2)が複数個配設され、電気配線が半導体素子(6、8)間及び外部入出力端子(2)間並びに半導体素子(6、8)と前記外部入出力端子(2)との間を接続され、半導体素子(6、 5) pattern - is N'ningu, external input and output terminal for delivering the external input and output signals (2) are plural arranged, electrical wiring semiconductor elements (6, 8) and between the external input and output terminals ( 2) during said well semiconductor element and (6,8) is connected between the external input and output terminal (2), the semiconductor element (6,
8)は、凹部(3)の底部に嵌装されるか、または凹部(3)を股いで載設されていることを特徴とするマルチチップモジュール。 8) is a multi-chip module, characterized in that it is crotch Ide No設 either fitted or recess the (3) in the bottom of the recess (3).

【0007】[2] 凹部(3)を樹脂で封止したことを特徴とする上記[1]に記載のマルチチップモジュール。 [0007] [2] The multi-chip module according to the above [1] to the recess (3), characterized in that sealed with resin.

【0008】 [0008]

【実施例】本発明を図面を参照して説明する。 EXAMPLES The present invention will be described with reference to the drawings.

【0009】図1は、本発明の1実施例のマルチチップモジュールの縦断面図である。 [0009] Figure 1 is a longitudinal sectional view of a multi-chip module of one embodiment of the present invention.

【0010】半導体素子6、8及びその他の電子素子を多数表面実装し、所定の電気配線で接続して形成されるマルチチップモジュールにおいて、半導体素子6、8及び多層基板1から成る。 [0010] The semiconductor element 6, 8 and other electronic devices and many surface mount, in a multi-chip module is formed by connecting a predetermined electric wiring, comprising a semiconductor element 6, 8 and the multilayer substrate 1.

【0011】多層基板は、その底部と上部とに半導体素子接続用電極4、5がパタ−ンニングされ、半導体素子6、8を嵌合するための凹部3が複数個配設される。 [0011] multilayer substrate, a semiconductor element connection electrodes 4, 5 on its bottom and top pattern - is N'ningu recess 3 for fitting the semiconductor device 6 and 8 is a plurality arranged. 外部と入出力信号の受け渡しをするための外部入出力端子2が複数個配設される。 External input and output terminals 2 for the delivery of external input and output signals is a plurality arranged. 半導体素子6、8間、外部入出力端子2間及び半導体素子6、8・外部入出力端子間の電気配線がその底部と上部と内部に繞設される。 Between the semiconductor element 6 and 8, the electrical wiring between between the external input and output terminals 2 and semiconductor element 6,8-external input is Nyo設 inside the top and bottom thereof.

【0012】半導体素子6、8は、多層基板1の凹部3 [0012] The semiconductor element 6 and 8, the concave portion 3 of the multilayer substrate 1
の底部と凹部上部円周を用いて嵌装・載設される。 Is fitted, No設 with bottom and concave upper circumference.

【0013】凹部3の底部には半導体素子接続用の電極4を形成している。 [0013] The bottom of the recess 3 is formed an electrode 4 for semiconductor element connection. また凹部3の上部に当たる部分にも半導体素子接続用電極5を設けている。 Further it is provided a semiconductor device connecting electrode 5 in part corresponding to the top of the recess 3.

【0014】まず凹部3に半導体素子6を実装し、半導体素子6の回路と凹部底部に設けた接続用電極4を接続する。 [0014] First, the semiconductor element 6 is mounted in the recess 3, to connect the connection electrodes 4 provided on the circuit and the recess bottom of the semiconductor element 6. 図1では半導体素子6の回路面を上にし金またはアルミ細線7によるワイヤ−ボンディング法により接続されている。 Wire according to gold or aluminum fine wires 7 on the circuit surface of the semiconductor element 6 in FIG. 1 - are connected by the bonding method. 凹部3内の半導体素子6を実装後、凹部を跨ぐ様に半導体素子8を実装する。 After mounting the semiconductor element 6 in the recess 3, to mount the semiconductor device 8 so as to straddle the concave portion. 凹部を跨ぐ半導体素子8は接続用端子9が施されたプラスチックパッケ−ジやセラミックパッケ−ジに収容された構造、またはキャリアテ−プ(図3の11)に半導体素子を実装した構造の半導体素子を使用する。 Plastic package semiconductor device 8 across the recess connection terminal 9 is applied - di or ceramic packages - contained structure to di- or carrier tape, - flop semiconductor structure mounting the semiconductor element (11 in FIG. 3) using the element.

【0015】多層基板との接続は、凹部上部に設けられた接続用電極5とで行われ半田付けなどの工法を用いる。 [0015] connection with a multi-layer substrate is performed by the connection electrodes 5 provided in a recess upper employed method such as soldering.

【0016】図2は、第2の実施例を示す。 [0016] Figure 2 shows a second embodiment.

【0017】特許請求の範囲第1項記載のマルチチップモジュールにおいて、凹部3を樹脂で封止している。 [0017] In a multi-chip module of the claims preceding claim, it seals the concave portion 3 in the resin.

【0018】第1の実施例の凹部3に裸の半導体素子6 The first embodiment bare the recess 3 of the semiconductor element 6
を使用し、半導体素子6の信頼性を確保するために樹脂10にて凹部を封止している。 Using seals the recess in the resin 10 in order to ensure the reliability of the semiconductor device 6.

【0019】図3は本発明の第3の実施例である。 [0019] FIG. 3 shows a third embodiment of the present invention.

【0020】凹部3の底部に半導体素子6を実装した後、キャリアテ−プ11に実装した半導体素子6の端子のみを、凹部上部の接続用電極52と接続する。 [0020] After mounting the semiconductor element 6 to the bottom of the recess 3, the carrier tape - only terminals of the semiconductor element 6 mounted on the flop 11, connected to the connection electrodes 52 of the recess top.

【0021】更に、半導体素子6を凹部3に落とし込み、上部電極52の周囲に設けた半導体素子接続用電極52を、半導体素子8を実装する。 Furthermore, darken the semiconductor element 6 in the recess 3, the semiconductor element connecting electrodes 52 provided around the upper electrode 52, for mounting a semiconductor element 8.

【0022】図4は、凹部3に階段状の段差12を設けた第4の実施例である。 [0022] Figure 4 is a fourth embodiment in which a stair-like steps 12 in the recess 3.

【0023】半導体素子6と多層基板の接続用電極との接続距離を短くした構造を特徴とする。 [0023] and wherein the short structure of the connection distance between the connection electrode of the semiconductor element 6 and the multilayer substrate.

【0024】 [0024]

【発明の効果】以上説明したように、本発明のマルチチップモジュール構造では、半導体素子を高さ方向に重ね実装できるため、従来のマルチチップモジュールに比較し2倍〜3倍の高集積化(高密度化)、または1/2〜 As described in the foregoing, in the multi-chip module structure of the present invention, it is possible to overlap a semiconductor element mounted in the height direction, conventional compared to the multi-chip module 2 to 3 times of the high integration ( densification), or 1/2
1/3の小型化が実現できる。 Miniaturization of 1/3 can be realized. 更に凹部を樹脂で封止したことにより、半導体素子6及びモジュールの信頼性を確保できる。 Furthermore a recess by sealing with a resin, can ensure the reliability of the semiconductor element 6 and the module.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施例の縦断面図である。 1 is a longitudinal sectional view of a first embodiment of the present invention.

【図2】本発明の第2の実施例の部分縦断面図である。 2 is a partial longitudinal sectional view of a second embodiment of the present invention.

【図3】本発明の第3の実施例の部分縦断面図である。 3 is a partial longitudinal sectional view of a third embodiment of the present invention.

【図4】本発明の第4の実施例の部分縦断面図。 Partial longitudinal sectional view of a fourth embodiment of the present invention; FIG.

【図5】従来のマルチチップモジュールの縦断面図。 Figure 5 is a longitudinal sectional view of a conventional multi-chip module.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 多層基板 2 外部入出力端子 3 凹部 4 半導体素子接続用電極 5 半導体素子接続用電極 6 半導体素子 7 細線 8 半導体素子 9 接続端子 10 樹脂 11 キャリアテ−プの端子部 12 階段状段差部 13 キャップ 14 多層基板 51 半導体素子接続用電極 52 半導体素子接続用電極 1 the multilayer substrate 2 external input 3 recess 4 semiconductor element connection electrode 5 semiconductor element connection electrode 6 semiconductor device 7 fine wire 8 semiconductor devices 9 connecting terminal 10 resin 11 carrier tape - flop terminal portion 12 stepped stepped portion 13 cap 14 multilayer substrate 51 semiconductor element connection electrode 52 semiconductor element connection electrode

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体素子を含む複数の電子素子を表面に実装し、該電子素子に接続される電気配線が形成されているマルチチップモジュールにおいて、 半導体素子及び多層基板から成り、 前記多層基板には、前記半導体素子を嵌合するための凹部が複数個配設され、半導体素子接続用電極がパタ−ンニングされ、外部と入出力信号の受け渡しをするための外部入出力端子が複数個配設され、前記電気配線が前記半導体素子間及び前記外部入出力端子間並びに前記半導体素子と前記外部入出力端子との間を接続し、 前記半導体素子は、前記凹部の底部に嵌装されるか、または前記凹部を股いで載設されていることを特徴とするマルチチップモジュール。 1. A plurality of electronic devices including a semiconductor element is mounted on the surface, in the multi-chip module electrical wiring is formed to be connected to the electronic device comprises a semiconductor element and a multilayer substrate, the multilayer substrate , the recess for fitting the semiconductor element is a plurality arranged, the semiconductor element connection electrode pattern - is N'ningu, external input and output terminals a plurality arranged for the delivery of external input and output signal is, whether the electrical wiring is connected between said external input and output terminals of the semiconductor element and between said external input and output terminals and between said semiconductor element, said semiconductor element is fitted to the bottom of the recess, or multi-chip module, characterized in that it is crotch Ide No設 the recess.
  2. 【請求項2】 前記凹部を樹脂で封止したことを特徴とする特許請求の範囲第1項記載のマルチチップモジュール。 2. A claims multichip module of claim 1 wherein the, characterized in that the recess is sealed with a resin.
JP15326393A 1993-06-24 1993-06-24 Multichip module Pending JPH0730059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15326393A JPH0730059A (en) 1993-06-24 1993-06-24 Multichip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15326393A JPH0730059A (en) 1993-06-24 1993-06-24 Multichip module

Publications (1)

Publication Number Publication Date
JPH0730059A true JPH0730059A (en) 1995-01-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP15326393A Pending JPH0730059A (en) 1993-06-24 1993-06-24 Multichip module

Country Status (1)

Country Link
JP (1) JPH0730059A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801438A (en) * 1995-06-16 1998-09-01 Nec Corporation Semiconductor device mounting and multi-chip module
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US5831833A (en) * 1995-07-17 1998-11-03 Nec Corporation Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
GB2339337A (en) * 1995-06-16 2000-01-19 Nec Corp Semiconductor device mounting in recesses in a circuit board
US6043987A (en) * 1997-08-25 2000-03-28 Compaq Computer Corporation Printed circuit board having a well structure accommodating one or more capacitor components
US6154371A (en) * 1998-09-30 2000-11-28 Cisco Technology, Inc. Printed circuit board assembly and method
GB2370421A (en) * 2000-12-22 2002-06-26 Ubinetics Printed circuit board with recessed component
JP2002232145A (en) * 2001-01-30 2002-08-16 Densei Lambda Kk Multilayer printed board
DE102007020475A1 (en) * 2007-04-27 2008-11-06 Häusermann GmbH Method for producing a printed circuit board with a cavity for the integration of components and printed circuit board and application

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Publication number Priority date Publication date Assignee Title
JPS5944852A (en) * 1982-09-07 1984-03-13 Seiko Epson Corp Mounting method of multi-layer chip
JPH03280496A (en) * 1990-03-28 1991-12-11 Taiyo Yuden Co Ltd Electronic copmponent mounting structure and method of packaging
JPH0573230A (en) * 1991-09-12 1993-03-26 Chugoku Nippon Denki Software Kk Print data operating device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944852A (en) * 1982-09-07 1984-03-13 Seiko Epson Corp Mounting method of multi-layer chip
JPH03280496A (en) * 1990-03-28 1991-12-11 Taiyo Yuden Co Ltd Electronic copmponent mounting structure and method of packaging
JPH0573230A (en) * 1991-09-12 1993-03-26 Chugoku Nippon Denki Software Kk Print data operating device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2339337A (en) * 1995-06-16 2000-01-19 Nec Corp Semiconductor device mounting in recesses in a circuit board
GB2339337B (en) * 1995-06-16 2000-03-01 Nec Corp Semiconductor device mounting method and multi-chip module produced by the same
GB2302451B (en) * 1995-06-16 2000-01-26 Nec Corp Semiconductor device mounting method and multi-chip module produced by the same
US5801438A (en) * 1995-06-16 1998-09-01 Nec Corporation Semiconductor device mounting and multi-chip module
US5831833A (en) * 1995-07-17 1998-11-03 Nec Corporation Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
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