JPS6236385B2 - - Google Patents
Info
- Publication number
- JPS6236385B2 JPS6236385B2 JP56133959A JP13395981A JPS6236385B2 JP S6236385 B2 JPS6236385 B2 JP S6236385B2 JP 56133959 A JP56133959 A JP 56133959A JP 13395981 A JP13395981 A JP 13395981A JP S6236385 B2 JPS6236385 B2 JP S6236385B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- frame
- circuit chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置のパツケージ構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package structure for a semiconductor integrated circuit device.
従来、この種の半導体集積回路のパツケージに
は、デユアルインラインパツケージやセラミツク
チツプキヤリアなどがある。
Conventionally, packages for this type of semiconductor integrated circuit include dual in-line packages and ceramic chip carriers.
しかし、近年における半導体集積回路の高密度
多機能化および高速化に伴つて、入出力端子数は
増加の一途をたどり、かつ半導体集積回路チツプ
１個当たりの電力が増大している。このため、上
述の従来のパツケージ構造では、半導体集積回路
装置の性能を十分に発揮することができないとい
う欠点がある。すなわち、デユアルインラインパ
ツケージでは、入出力端子数を増加させるために
はパツケージ自体が大となるため、高密度実装が
不可能となり、かつ入出力端子までの接続線長が
長くなつて回路の高速化を妨げる欠点がある。
However, in recent years, as semiconductor integrated circuits have become more dense and multifunctional and faster, the number of input/output terminals has continued to increase, and the power per semiconductor integrated circuit chip has also increased. For this reason, the conventional package structure described above has the disadvantage that the performance of the semiconductor integrated circuit device cannot be fully demonstrated. In other words, in a dual-in-line package, increasing the number of input/output terminals requires increasing the size of the package itself, making high-density packaging impossible, and increasing the length of the connection wires to the input/output terminals, making it difficult to increase the speed of the circuit. There are drawbacks that hinder this.
また、セラミツクチツプキヤリアでは、入出力
端子数の増加によるパツケージの大きさの増大は
デユアルインラインパツケージより改善される
が、熱抵抗に関しては、パツケージに形状に伴う
限界が存在するため、半導体集積回路を高信頼度
で動作させるためには、消費電力が１〜2W程度
以下に制限されるという欠点がある。 In addition, ceramic chip carriers are better than dual-in-line packages when it comes to increasing the size of the package due to an increase in the number of input/output terminals, but in terms of thermal resistance, there is a limit due to the shape of the package, so In order to operate with high reliability, there is a drawback that power consumption is limited to about 1 to 2 W or less.
また、上記のいずれの方式ににおいても半導体
集積回路チツプと入出力端子との接続は、ワイヤ
ボンデイング法などにより１本ずつ接続されるた
め、製造コストが高くなるという欠点がある。 Furthermore, in any of the above methods, the semiconductor integrated circuit chip and the input/output terminals are connected one by one by wire bonding or the like, which has the disadvantage of increasing manufacturing costs.
これらの解決手段として、出願人は半導体集積
回路チツプを囲う四角の接続枠を用い、この接続
枠に半導体集積回路チツプの電極と接続する複数
のリードを設けて半導体集積回路チツプをプリン
ト基板に実装する技術を提案した（特開昭53−
41177号公報、特開昭47−57363号公報）。 As a means of solving these problems, the applicant used a rectangular connection frame surrounding the semiconductor integrated circuit chip, provided a plurality of leads connected to the electrodes of the semiconductor integrated circuit chip in this connection frame, and mounted the semiconductor integrated circuit chip on a printed circuit board. proposed a technology to
41177, JP-A-47-57363).
しかしながら、この出願人提案の技術は、接続
枠により半導体集積回路チツプにリードを接続す
るが、この接続枠には、半導体集積回路チツプを
保護する機能はなく、また、半導体集積回路チツ
プの放熱を効率よく放散するものではなかつた。 However, although the technique proposed by the applicant connects the leads to the semiconductor integrated circuit chip using a connection frame, this connection frame does not have the function of protecting the semiconductor integrated circuit chip and also prevents the heat dissipation of the semiconductor integrated circuit chip. It did not dissipate efficiently.
本発明の目的は、上述の欠点を解決し、多端子
の場合においても小型かつ高密度に半導体集積回
路チツプを実装し、かつ半導体集積回路チツプの
保護と熱放散性を高める半導体集積回路装置を提
供することにある。 An object of the present invention is to provide a semiconductor integrated circuit device that solves the above-mentioned drawbacks, mounts semiconductor integrated circuit chips in a compact and high-density manner even in the case of multiple terminals, and improves the protection and heat dissipation of the semiconductor integrated circuit chips. It is about providing.
本発明の半導体集積回路装置は、半導体集積回
路チツプと、このチツプを囲む絶縁材料からなる
額縁状の枠と、この枠の周辺部に固着され前記半
導体集積回路チツプの電極と接続する複数のリー
ドとを備えた半導体集積回路装置において、
前記枠に段部が形成され、前記複数のリードは
この枠の下段部に固着しされ、かつ枠上面に形成
された入出力端子と導体によつて接続され、前記
枠の上段部には、シール板を載置され、前記半導
体集積回路チツプの下に直接にヒートシンクが接
着されたことを特徴とする。
The semiconductor integrated circuit device of the present invention includes a semiconductor integrated circuit chip, a frame-like frame made of an insulating material surrounding the chip, and a plurality of leads fixed to the periphery of the frame and connected to electrodes of the semiconductor integrated circuit chip. In the semiconductor integrated circuit device, the frame has a stepped part, and the plurality of leads are fixed to the lower part of the frame and connected to input/output terminals formed on the top surface of the frame by conductors. A sealing plate is placed on the upper part of the frame, and a heat sink is bonded directly under the semiconductor integrated circuit chip.
段差が設けられた枠内の半導体集積回路チツプ
の電極には枠の下段部に固着されたリードが接続
されて枠の外部の入出力端子に接続される。この
枠の上段部にはシール板が載置されて半導体集積
回路チツプを保護する。また、半導体集積回路チ
ツプと枠の下面にはヒートシンクが直接接着され
て半導体集積回路チツプの放熱を放散する。
Leads fixed to the lower part of the frame are connected to electrodes of the semiconductor integrated circuit chip within the stepped frame, and are connected to input/output terminals outside the frame. A sealing plate is placed on the upper part of this frame to protect the semiconductor integrated circuit chip. Further, a heat sink is directly bonded to the lower surface of the semiconductor integrated circuit chip and the frame to dissipate heat from the semiconductor integrated circuit chip.
次に、本発明について、図面を参照して詳細に
説明する。
Next, the present invention will be explained in detail with reference to the drawings.
第１図は、本発明の一実施例を示す組立前の斜
視図であり、第２図はその断面図である。すなわ
ち、半導体集積回路チツプ１を囲む枠２に段部を
形成し、上段部に半導体集積回路チツプ１を保護
するシール板５を取付けられるようにしている。
そして、リード３は、枠２の下段部に形成された
電極２３と集積回路チツプ１の電極とを接続す
る。枠２の図中上面周辺部に入出力端子２１を設
け、入出力端子２１は導体２２によつて電極２３
と接続されている。枠２は、アルミナセラミツク
またはプラスチツク等の絶縁材料を使用する。リ
ード３は例えば35〜70mm程度の厚さの銅箔を、わ
ずかな酸素を含む窒素雰囲気中で1075゜±５℃に
加熱しながら前記枠２に接合したのち、エツチン
グ技術によりリードパターンを形成することによ
り得られる。枠２との接合は接着材を用いても差
支えない。また必要によりメツキを施しても良
い。リードパターン先に形成して、それぞれ枠に
貼付けしてもよい。リードパターンはエツチング
技術により一定のパターンに形成されるから半導
体集積回路チツプの電極４と容易に位置合わせす
ることができる。リード３と電極４とを位置合わ
せしたのち、熱圧着ボンデイング法等により、多
数の端子を一括して接続することができる。すな
わち、従来のようにワイヤボンデイング法で１本
ずつ接続する必要がないから、生産性が向上し、
製造コストを低減できる効果がある。 FIG. 1 is a perspective view of an embodiment of the present invention before assembly, and FIG. 2 is a sectional view thereof. That is, a stepped portion is formed in the frame 2 surrounding the semiconductor integrated circuit chip 1, and a seal plate 5 for protecting the semiconductor integrated circuit chip 1 can be attached to the upper step.
The leads 3 connect the electrodes 23 formed on the lower part of the frame 2 and the electrodes of the integrated circuit chip 1. An input/output terminal 21 is provided around the upper surface of the frame 2 in the figure, and the input/output terminal 21 is connected to an electrode 23 by a conductor 22.
is connected to. The frame 2 is made of an insulating material such as alumina ceramic or plastic. For the lead 3, for example, a copper foil with a thickness of about 35 to 70 mm is bonded to the frame 2 while being heated to 1075°±5°C in a nitrogen atmosphere containing a small amount of oxygen, and then a lead pattern is formed by etching technology. It can be obtained by An adhesive may be used for joining with the frame 2. Further, plating may be applied if necessary. The lead pattern may be formed first and attached to each frame. Since the lead pattern is formed into a certain pattern by etching technology, it can be easily aligned with the electrode 4 of the semiconductor integrated circuit chip. After aligning the leads 3 and the electrodes 4, a large number of terminals can be connected at once by thermocompression bonding or the like. In other words, there is no need to connect each wire one by one using the wire bonding method as in the past, improving productivity.
This has the effect of reducing manufacturing costs.
さらに、半導体集積回路チツプ１の裏側（図中
下面）にはヒートシンク６が直接取付られてい
る。上述の枠は、セラミツク枠にタングステンや
モリブデンなどの高耐熱金属を用いたペーストを
印刷焼成することにより容易に製造可能である。 Further, a heat sink 6 is directly attached to the back side of the semiconductor integrated circuit chip 1 (lower side in the figure). The above-mentioned frame can be easily manufactured by printing and firing a paste using a highly heat-resistant metal such as tungsten or molybdenum on a ceramic frame.
シール板およびヒートシンクの取付けは半田付
けや溶接によつて可能である。この場合は、前述
の効果に加えて封止を行うことにより取り扱いが
容易となり、かつ信頼性も向上する利点がある。 The seal plate and heat sink can be attached by soldering or welding. In this case, in addition to the above-mentioned effects, sealing has the advantage of facilitating handling and improving reliability.
以上のように、本発明は、半導体集積回路チツ
プを段差のある絶縁性の額縁状の枠で囲み、この
枠の下段に半導体集積回路チツプの電極と接続す
るリード線を設けて接続し、上段には半導体集積
回路チツプのシール板を取付け、下面にヒートシ
ンクを設けているので、半導体集積回路装置の生
産性を向上し、シール板によつて半導体集積回路
チツプを保護し、熱の放散性を高めて許容電力を
大きくすることができる。
As described above, the present invention surrounds a semiconductor integrated circuit chip with an insulating frame-like frame with steps, provides lead wires to connect to the electrodes of the semiconductor integrated circuit chip in the lower part of the frame, and connects the semiconductor integrated circuit chip with the electrodes of the semiconductor integrated circuit chip in the upper part. A seal plate for the semiconductor integrated circuit chip is attached to the holder, and a heat sink is provided on the bottom surface, which improves the productivity of semiconductor integrated circuit devices.The seal plate protects the semiconductor integrated circuit chip and improves heat dissipation. It is possible to increase the allowable power by increasing the power consumption.
第１図は本発明一実施例を示す組立前の斜視
図。第２図は実施例の組立後の断面図。
１……半導体集積回路チツプ、２……枠、３…
…リード、４……半導体集積回路チツプの電極、
５……シール板、６……ヒートシンク、２１……
入出力端子、２２……導体、２３……電極。
FIG. 1 is a perspective view of an embodiment of the present invention before assembly. FIG. 2 is a sectional view of the embodiment after assembly. 1... Semiconductor integrated circuit chip, 2... Frame, 3...
...lead, 4...electrode of semiconductor integrated circuit chip,
5... Seal plate, 6... Heat sink, 21...
Input/output terminal, 22...conductor, 23...electrode.
Claims (1)
２と、 この枠の周辺部に固着され前記半導体集積回路
チツプの電極と接続する複数のリード３と を備えた半導体集積回路装置において、 前記枠に段部が形成され、前記複数のリードは
この枠の下段部に固着され、かつ枠上面に形成さ
れた入出力端子と導体とによつて接続され、前記
枠の上段部には、シール板５を載置され、前記半
導体集積回路チツプの下面に直接にヒートシンク
６が接着された ことを特徴とする半導体集積回路装置。[Scope of Claims] 1. A semiconductor integrated circuit chip 1, a frame-shaped frame 2 made of an insulating material surrounding the chip, and a plurality of leads fixed to the periphery of the frame and connected to electrodes of the semiconductor integrated circuit chip. 3, wherein the frame has a stepped portion, the plurality of leads are fixed to the lower step of the frame, and are connected by input/output terminals and conductors formed on the upper surface of the frame. A semiconductor integrated circuit device, characterized in that a sealing plate 5 is placed on the upper part of the frame, and a heat sink 6 is bonded directly to the lower surface of the semiconductor integrated circuit chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56133959A JPS5835952A (en) | 1981-08-28 | 1981-08-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56133959A JPS5835952A (en) | 1981-08-28 | 1981-08-28 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5835952A JPS5835952A (en) | 1983-03-02 |
| JPS6236385B2 true JPS6236385B2 (en) | 1987-08-06 |
Family
ID=15117075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56133959A Granted JPS5835952A (en) | 1981-08-28 | 1981-08-28 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5835952A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437042A (en) * | 1987-07-31 | 1989-02-07 | Ibiden Co Ltd | Substrate for carrying electronic component |
| US9698646B2 (en) | 2011-11-09 | 2017-07-04 | Mitusubishi Electric Corporation | Rotating electrical machine |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4728441U (en) * | 1971-04-14 | 1972-12-01 | ||
| JPS4957363A (en) * | 1972-10-04 | 1974-06-04 | ||
| JPS5117667A (en) * | 1974-08-05 | 1976-02-12 | Matsushita Electric Ind Co Ltd | Handotaisochino seizohoho |
| JPS5341177A (en) * | 1976-09-28 | 1978-04-14 | Nec Corp | Mounting method of electronic parts |
| JPS54148377A (en) * | 1978-05-15 | 1979-11-20 | Ngk Spark Plug Co | Leadless package for attaching semiconductor chip |
| JPS5669897A (en) * | 1979-11-09 | 1981-06-11 | Nippon Electric Co | High density package structure |
-
1981
- 1981-08-28 JP JP56133959A patent/JPS5835952A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4728441U (en) * | 1971-04-14 | 1972-12-01 | ||
| JPS4957363A (en) * | 1972-10-04 | 1974-06-04 | ||
| JPS5117667A (en) * | 1974-08-05 | 1976-02-12 | Matsushita Electric Ind Co Ltd | Handotaisochino seizohoho |
| JPS5341177A (en) * | 1976-09-28 | 1978-04-14 | Nec Corp | Mounting method of electronic parts |
| JPS54148377A (en) * | 1978-05-15 | 1979-11-20 | Ngk Spark Plug Co | Leadless package for attaching semiconductor chip |
| JPS5669897A (en) * | 1979-11-09 | 1981-06-11 | Nippon Electric Co | High density package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5835952A (en) | 1983-03-02 |
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