JPH0338845A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH0338845A
JPH0338845A JP1174624A JP17462489A JPH0338845A JP H0338845 A JPH0338845 A JP H0338845A JP 1174624 A JP1174624 A JP 1174624A JP 17462489 A JP17462489 A JP 17462489A JP H0338845 A JPH0338845 A JP H0338845A
Authority
JP
Japan
Prior art keywords
electrode
electronic component
conductor
layer
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1174624A
Other languages
Japanese (ja)
Inventor
Kenichi Ono
大野　兼一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1174624A priority Critical patent/JPH0338845A/en
Publication of JPH0338845A publication Critical patent/JPH0338845A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73261—Bump and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce a circuit area by connecting the following to conductor parts on an insulating substrate: an electrode, which has been formed on a face facing the conductor part on the insulating substrate, of an electronic component which is provided with an active part and a passive part on both the surface and the rear; and an electrode which has been formed on the other face of the electronic component after it has been connected to the conductor part. CONSTITUTION:An active part 21 such as a transistor or the like is formed on the surface side of an electronic component 14; it is protected by insulating layers 22, 23; the inside of the electronic component 14 is wired by using a conductor layer 24 through openings in the insulating layers; an electrode 25 to be connected to the outside is formed. A resistance layer 32 and, in addition, a conductor layer 33 are formed on an insulating layer 31 on the rear side of the electronic component 14. The electronic component 14 is connected to an electrode 2 via the electrode 25 by using a soldering method, a thermocompression bonding method or the like; after that, the conductor layer 33 which has been formed on the resistor layer 32 is connected to an electrode 2' by using an Au thin wire 34 or the like. Thereby, the number of components to be used for a hybrid integrated circuit can be reduced and its area can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of hybrid integrated circuits.

〔従来の技術〕[Conventional technology]

従来より混成集積回路に醤゛いては、半導体集積回路と
絶縁性基板上に形成されるか搭載された抵抗或いはコン
デンサ等を別個の部品として組合せて使っていた。Conventionally, hybrid integrated circuits have used a combination of a semiconductor integrated circuit and a resistor or capacitor formed or mounted on an insulating substrate as separate components.

第３図は従来から実施されて来た混成集積回路の構造を
示す断面図である。第３図に於いて１は電気的に絶縁性
を示すアルミナセラミック等から成る基板であり、その
基板１の上に抵抗体３配線用の導体２が形成されている
。Ｓｉ単結晶とベースとした半導体集積回路（以下ＩＣ
と記す〉、４は基板１の上に設けられたＩＣ４用のマウ
ントランド５の上に塗布された接着剤６等により固定さ
れている。又、ＩＣ４は周囲の電気部品例えば、抵抗２
と電気的に接続する為にボンディング用のＡｕ細線等に
より接続が為されている。FIG. 3 is a sectional view showing the structure of a conventional hybrid integrated circuit. In FIG. 3, reference numeral 1 denotes a substrate made of electrically insulative alumina ceramic or the like, and a conductor 2 for wiring the resistor 3 is formed on the substrate 1. Semiconductor integrated circuit (hereinafter referred to as IC) based on Si single crystal
4 is fixed by an adhesive 6 or the like applied onto a mounting land 5 for the IC 4 provided on the substrate 1. In addition, IC4 is connected to surrounding electrical components such as resistor 2.
In order to make an electrical connection with the wire, a thin Au wire for bonding or the like is used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の構造では、混成集積回路を構成する為に
半導体部品と抵抗コンデンサ等の受動部品を別個の部品
として組合せていたので、混成集積回路を実現する為の
面積が大きくなるという構造的な欠点があった。In the conventional structure described above, semiconductor components and passive components such as resistor capacitors were combined as separate components to form a hybrid integrated circuit, which resulted in structural problems such as an increase in the area required to realize the hybrid integrated circuit. There were drawbacks.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の混成集積回路は、表裏両面に能動部分と受動部
分とを有する電子部品の絶縁性基板上の導体部分に相対
する面に設けられた電極と、前記導体部分に接続した後
に前記電子部品の他方の面に設けられた電極を前記絶縁
性基板上の導体部分に接続されている。The hybrid integrated circuit of the present invention has an electrode provided on a surface facing a conductor part on an insulating substrate of an electronic component having an active part and a passive part on both the front and back sides, and An electrode provided on the other surface of the substrate is connected to a conductor portion on the insulating substrate.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１の実施例を示す断面図である。１
は絶縁性の基板の示しその上に接続及び配線用の導体２
が形成されている。１４は基板１の上に搭載された電気
部品を示す。電子部品１４の表面側にはトランジスタ等
の能動部分２１が形成され、絶縁層２２．２３により保
護されると共に絶縁層の開口部の通して導体層２４によ
り電子部品１４内部での配線が為されると共に外部へ接
続する為の電ｆｌｉ２５が形成される。電子部品１４の
裏面側には絶縁層３１の上に抵抗層３２さらに導体層３
３が形成されている。FIG. 1 is a sectional view showing a first embodiment of the present invention. 1
indicates an insulating substrate with conductor 2 for connection and wiring on it
is formed. Reference numeral 14 indicates an electrical component mounted on the board 1. An active part 21 such as a transistor is formed on the surface side of the electronic component 14, and is protected by insulating layers 22 and 23, and wiring inside the electronic component 14 is formed by a conductor layer 24 through the opening of the insulating layer. At the same time, a power line 25 for connection to the outside is formed. On the back side of the electronic component 14, a resistive layer 32 is disposed on an insulating layer 31, and a conductive layer 3.
3 is formed.

電子部品１４は電極２５を介して電極２とハンダづけ或
いは熱圧着等の方法により接続された後、抵抗体層３２
の上に形成された導体層３３と電極２′がＡｕ細線３４
等により接続される。After the electronic component 14 is connected to the electrode 2 via the electrode 25 by a method such as soldering or thermocompression bonding, the resistor layer 32
The conductor layer 33 and electrode 2' formed on the Au thin wire 34
Connected by etc.

第２図は本発明の第２の実施例の断面図である。本例で
は予め配列されて保持板３５によりその間隔向きが一定
に保たれそれぞれの両端が電極２′、３Ｂに平行になる
よう曲げられてさらに予備的にハンダ或いはＡｕ等の接
続用電極３７が付着されたリード列３６ハンダリフロー
又は熱圧着等により電極２′、３３に接続した状態を示
している。FIG. 2 is a sectional view of a second embodiment of the invention. In this example, they are arranged in advance, their spacing direction is kept constant by a holding plate 35, and both ends of each are bent so as to be parallel to the electrodes 2' and 3B. The attached lead row 36 is shown connected to the electrodes 2' and 33 by solder reflow, thermocompression bonding, or the like.

この場合は電子部品１４の両側の接続が一括で可能とな
るはかりではなく、反対側の接続についても一括又は各
リード列毎に一括で接続できる利点がある。In this case, it is not possible to connect both sides of the electronic component 14 at once, but there is an advantage that the connection on the opposite side can also be connected at once or for each lead row.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の混成集積回路は搭載する電
子部品の両面に能動部分受動部分を持つことにより、混
成集積回路の使用部品を減らすと共にその面積の小さく
することが可能であるばがりではなく、搭載部品の接続
に掛がる作業時間を短縮できる効果がある。As explained above, the hybrid integrated circuit of the present invention has an active part and a passive part on both sides of the mounted electronic components, so that it is possible to reduce the number of parts used in the hybrid integrated circuit and to reduce its area. This has the effect of reducing the work time required to connect mounted components.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例を示す断面図、第２図は
本発明の第２の実施例の断面図、第３図は従来の混成集
積回路の一例の断面図である。 １・・・基板３．２．２′・・・導体、３・・・抵抗体
、４・・・ＩＣｌ３・・・マウントランド、６・・・接
着剤、７・・・Ａｕ細線、１４・・・電子部品、２１・
・能動部品、２２．２３・・絶縁層、２４・・・導体層
、２５・・・電極、３１・・・絶縁層、３２・・・抵抗
体層、３３・・・導体層、３４・・・Ａｕ細線、３５・
・・保持板、３６・・・リード列、３７・・・接続用電
極。FIG. 1 is a sectional view showing a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the invention, and FIG. 3 is a sectional view of an example of a conventional hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1... Substrate 3.2.2'... Conductor, 3... Resistor, 4... ICl3... Mount land, 6... Adhesive, 7... Au thin wire, 14...・・Electronic parts, 21・
- Active component, 22.23... Insulating layer, 24... Conductor layer, 25... Electrode, 31... Insulating layer, 32... Resistor layer, 33... Conductor layer, 34...・Au thin wire, 35・
...Holding plate, 36... Lead row, 37... Connection electrode.

Claims (1)

【特許請求の範囲】[Claims] 表裏両面に能動部分と受動部分とを有する電子部品の絶
縁性基板上の導体部分に相対する面に設けられた電極と
、前記導体部分に接続した後に前記電子部品の他方の面
に設けられた電極を前記絶縁性基板上の導体部分に接続
したことを特徴とする混成集積回路。An electrode provided on a surface facing a conductor portion on an insulating substrate of an electronic component having an active part and a passive part on both front and back surfaces, and an electrode provided on the other surface of the electronic component after being connected to the conductor part. A hybrid integrated circuit characterized in that an electrode is connected to a conductor portion on the insulating substrate.
JP1174624A 1989-07-05 1989-07-05 Hybrid integrated circuit Pending JPH0338845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1174624A JPH0338845A (en) 1989-07-05 1989-07-05 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1174624A JPH0338845A (en) 1989-07-05 1989-07-05 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH0338845A true JPH0338845A (en) 1991-02-19

Family

ID=15981851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1174624A Pending JPH0338845A (en) 1989-07-05 1989-07-05 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH0338845A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001015230A1 (en) * 1999-08-25 2001-03-01 Hitachi, Ltd. Electronic device
KR101400463B1 (en) * 2010-02-19 2014-05-28 다이-이치 세이코 가부시키가이샤 Electrical connector and electrical connector assembly

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001015230A1 (en) * 1999-08-25 2001-03-01 Hitachi, Ltd. Electronic device
US6740969B1 (en) 1999-08-25 2004-05-25 Renesas Technology Corp. Electronic device
KR101400463B1 (en) * 2010-02-19 2014-05-28 다이-이치 세이코 가부시키가이샤 Electrical connector and electrical connector assembly

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