JPS6022348A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6022348A
JPS6022348A JP58130521A JP13052183A JPS6022348A JP S6022348 A JPS6022348 A JP S6022348A JP 58130521 A JP58130521 A JP 58130521A JP 13052183 A JP13052183 A JP 13052183A JP S6022348 A JPS6022348 A JP S6022348A
Authority
JP
Japan
Prior art keywords
insulating substrate
substrate
peripheral components
semiconductor device
connection terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58130521A
Other languages
Japanese (ja)
Other versions
JPH0458189B2 (en
Inventor
Fumio Takeyama
竹山　文雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP58130521A priority Critical patent/JPS6022348A/en
Publication of JPS6022348A publication Critical patent/JPS6022348A/en
Publication of JPH0458189B2 publication Critical patent/JPH0458189B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To eliminate the necessity of arranging peripheral components on a printed circuit board and facilitate a high density mounting of an electric machine by a method wherein the peripheral components are attached and connected to the surface of an insulating substrate in which a semiconductor element is incorporated. CONSTITUTION:A recessed part 11 is formed at the center of an insulating substrate 10 and a semiconductor element 12 is attached to the recessed part 11 by die-bonding. A plurality of connection terminals 13 are lead out radially from the inside of the recessed part 11 to the sides and further to the bottom of the substrate 10 through the surface of the substrate 10. One end of the terminal 13 is connected to an electrode of the element 12 by wire bonding with a fine gold wire. On the surface of an auxiliary substrate 20, connection terminals 21 are lead out. Peripheral components 22 are attached to the surface of the substrate 20. The substrate 20 is mounted on the substrate 10. With this constitution, a high density mounting of an electric machine can be realized.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 この発明は高密度実装に通した半導体装置に関する。[Detailed description of the invention] (b) Industrial application fields The present invention relates to a semiconductor device that is subjected to high-density packaging.

（ロ）従来技術 近年の電子機器の小型化に伴い、これらに用いられる半
導体部品も著しく小型化されてきた。しかして、今日、
前記半導体部品のみならずその周辺部品をも含めた半導
体装置全体としての小型化が要望されるに至っている。(B) Prior Art As electronic devices have become smaller in recent years, the semiconductor components used in these devices have also become significantly smaller. However, today,
There is a growing demand for miniaturization of the entire semiconductor device, including not only the semiconductor components but also their peripheral components.

（ハ）目的 この発明は周辺部品をも含めた装置全体としての小型化
が容易で、高密度実装に適した半導体装置を提供するこ
とを目的としている。(C) Purpose This invention aims to provide a semiconductor device that can be easily miniaturized as a whole including peripheral components and is suitable for high-density packaging.

（ニ）構成 この発明に係る半導体装置は、絶縁基板表面に設けた凹
部に半導体素子を固着し、前記凹部内面から前記絶縁基
板表面を通って外部へ導出された接続端子と、前記半導
体素子の所定の電極間を接続するとともに、絶縁基板表
面において、所定の接続端子間を周辺部品で接続したこ
とを特徴としている。(D) Structure A semiconductor device according to the present invention has a semiconductor element fixed in a recess provided on the surface of an insulating substrate, and a connecting terminal led out from the inner surface of the recess through the surface of the insulating substrate, and a connecting terminal of the semiconductor element. It is characterized in that predetermined electrodes are connected, and predetermined connection terminals on the surface of the insulating substrate are connected by peripheral parts.

（ホ）実施例 第１図はこの発明に係る半導体装置の一実施例の構成を
示す解体斜視図、第２図は第１図に示した実施例の断面
図である。(e) Embodiment FIG. 1 is an exploded perspective view showing the structure of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view of the embodiment shown in FIG. 1.

第１図及び第２図において、１０はセラミック等からな
る絶縁基板であり、この絶縁基板１０の表面中央部には
凹部１１が形成されている。凹部１１の底面中央の凹所
には半導体素子１２がグイボンディングされている。そ
して、凹部１１の内面から絶縁基板１０の表面を通って
、絶縁基板１０の側面、さらには必要に応じその絶縁基
板１０の底面にまで複数の接続端子１３が放射状に導出
される。この接続端子１３は例えば、厚膜で印刷形成さ
れる。接続端子１３の一端と半導体素子１２・の所定の
電極間は極細金線１４等でワイヤボンディングされる。In FIGS. 1 and 2, 10 is an insulating substrate made of ceramic or the like, and a recess 11 is formed in the center of the surface of this insulating substrate 10. In FIG. A semiconductor element 12 is bonded to a recess at the center of the bottom surface of the recess 11 . Then, a plurality of connection terminals 13 are radially led out from the inner surface of the recess 11, through the surface of the insulating substrate 10, to the side surface of the insulating substrate 10, and even to the bottom surface of the insulating substrate 10 if necessary. This connection terminal 13 is formed by printing a thick film, for example. Wire bonding is performed between one end of the connection terminal 13 and a predetermined electrode of the semiconductor element 12 using an ultrafine gold wire 14 or the like.

ワイヤボンディングされた後、凹部１１に例えばエポキ
シ樹脂１５が充填され前記半導体素子１４が封止される
。After wire bonding, the recess 11 is filled with, for example, an epoxy resin 15 to seal the semiconductor element 14.

２０はセラミック等の絶縁性の基板よりなるサブ基板で
あって、その表面には厚膜で適宜の門己線パターンが形
成され、接続端子２１がサブ基板２０の底面にまで導出
される。そして、このサブ基板２０の表面には、例えば
チップ抵抗器、チップコンデンサ、小型トランジスタ等
の周辺部品２２が取りつけ接続されている。Reference numeral 20 denotes a sub-substrate made of an insulating substrate such as ceramic, on the surface of which a suitable gate line pattern is formed with a thick film, and connection terminals 21 are led out to the bottom surface of the sub-substrate 20. On the surface of this sub-board 20, peripheral components 22 such as chip resistors, chip capacitors, small transistors, etc. are attached and connected.

しかして、前記サブ基板２０は、絶縁基板１０の表面に
載置され、両基板の所定の接続端子間が導電ペーストや
半田付けでもって接続されることにより固定される。Thus, the sub-board 20 is placed on the surface of the insulating board 10 and fixed by connecting predetermined connection terminals of both boards with conductive paste or soldering.

尚、第１図に示した実施例では、絶縁基板１０は単体の
ものとして構成されているが、これは第３図に示すよう
に複数の絶縁基板１０゛を連設した長尺の絶縁板３０を
用い、前述したような半導体素子のボンディング作業、
周辺部品の接続、さらには電気的特性の測定の後に各絶
縁基板１０′を区画するＶ溝３１に沿って各絶縁基板１
０”を分離するものであってもよい。絶縁基板ｌＯ“を
このように形成することにより、接続端子を絶縁基板の
短辺側に導出することはできなくなるが、量産時におけ
る半導体装置の組立を容易にするこができる。In the embodiment shown in FIG. 1, the insulating substrate 10 is constructed as a single piece, but as shown in FIG. 30, the bonding work of semiconductor elements as described above,
After connecting peripheral components and measuring electrical characteristics, each insulating substrate 1 is connected along the V groove 31 that partitions each insulating substrate 10'.
0". By forming the insulating substrate lO" in this way, it becomes impossible to lead out the connection terminal to the short side of the insulating substrate, but it is easy to assemble the semiconductor device during mass production. This can be done easily.

また、上述の実施例において、絶縁基板表面の接続端子
間の周辺部品の接続は、周辺部品が接続されたサブ基板
を絶縁基板に取りつけることにより行うと説明したが、
これはチップ抵抗器等の周辺部品を前記絶縁基板表面の
接続端子間に直接に接続することにより行うものであっ
てもよいことは勿論である。Further, in the above embodiment, it was explained that the connection of peripheral components between the connection terminals on the surface of the insulating substrate is performed by attaching the sub-board to which the peripheral components are connected to the insulating substrate.
Of course, this may be done by directly connecting peripheral components such as chip resistors between the connection terminals on the surface of the insulating substrate.

（へ）効果 この発明に係る半導体装置は、半導体素子が組み込まれ
た絶縁基板の表面に周辺部品を取りつけ接続するもので
あるから、周辺部品をプリント基板に配置する必要がな
くなり電気機器の高密度実装が容易になる。(f) Effects Since the semiconductor device according to the present invention is for attaching and connecting peripheral components to the surface of an insulating substrate in which a semiconductor element is incorporated, there is no need to arrange peripheral components on a printed circuit board, allowing for high-density electrical equipment. Easier to implement.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明に係る半導体装置の一実施例の構成を
示す解体斜視図、第２図は第１図に示した実施例の断面
図、第３図は他の実施例の外観斜視図である。 １０．１０“・・・絶縁基板、１１・・・凹部、１２・
・・半導体素子、１３・・・接続端子、２０・・・サブ
基板、２１・・・接続端子、２２・・・周辺部品。 特許出願人　ローム株式会社 代理人　弁理士　大　西　孝　治 第１図 ２２ 第２図 第３図FIG. 1 is an exploded perspective view showing the configuration of one embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional view of the embodiment shown in FIG. 1, and FIG. 3 is an external perspective view of another embodiment. It is. 10.10"...Insulating substrate, 11...Recess, 12.
... Semiconductor element, 13... Connection terminal, 20... Sub board, 21... Connection terminal, 22... Peripheral components. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney: Takaharu Ohnishi Figure 1, 22, Figure 2, Figure 3

Claims (4)

【特許請求の範囲】[Claims] （１）絶縁基板表面に設けた凹部に半導体素子を固着し
、前記凹部内面から前記絶縁基板表面を通って外部へ導
出された接続端子と、前記半導体素子の所定の電極間を
接続するとともに、絶縁基板′表面において、所定の接
続端子間を周辺部品で接続したことを特徴とする半導体
装置。(1) A semiconductor element is fixed to a recess provided on the surface of an insulating substrate, and a connection terminal led out from the inner surface of the recess through the surface of the insulating substrate and a predetermined electrode of the semiconductor element are connected, A semiconductor device characterized in that predetermined connection terminals are connected by peripheral parts on the surface of an insulating substrate. （２）前記絶縁基板表面におりる所定の接続端子間の周
辺部品の接続は、配線パターンが形成されたサブ基板に
周辺部品を取りつけ、このサブ基板を絶縁基板表面に載
置して所定の端子間を接続することにより行われるもの
であることを特徴とする特許請求の範囲第１項記載の半
導体装置。(2) To connect peripheral components between predetermined connection terminals on the surface of the insulating substrate, attach the peripheral components to a sub-board on which a wiring pattern is formed, place this sub-board on the surface of the insulating substrate, 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured by connecting terminals. （３）前記絶縁基板表面における所定の接続端子間の周
辺部品の接続は、絶縁基板表面の接続端子間を周辺部品
でもって直接に接続することにより行われるものである
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。(3) A patent claim characterized in that the connection of peripheral components between predetermined connection terminals on the surface of the insulating substrate is performed by directly connecting the connection terminals on the surface of the insulating substrate with peripheral components. The semiconductor device according to item 1. （４）前記絶縁基板は、該絶縁基板が複数個連設された
長尺の絶縁板を分離して形成されるものであることを特
徴とする特許請求の範囲第１項記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the insulating substrate is formed by separating a long insulating plate having a plurality of insulating substrates arranged in series.
JP58130521A 1983-07-18 1983-07-18 Semiconductor device Granted JPS6022348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58130521A JPS6022348A (en) 1983-07-18 1983-07-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58130521A JPS6022348A (en) 1983-07-18 1983-07-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6022348A true JPS6022348A (en) 1985-02-04
JPH0458189B2 JPH0458189B2 (en) 1992-09-16

Family

ID=15036282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58130521A Granted JPS6022348A (en) 1983-07-18 1983-07-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6022348A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6088574U (en) * 1983-11-24 1985-06-18 日本電気株式会社 Chip carrier type package connection structure
US5444296A (en) * 1993-11-22 1995-08-22 Sun Microsystems, Inc. Ball grid array packages for high speed applications
US5666272A (en) * 1994-11-29 1997-09-09 Sgs-Thomson Microelectronics, Inc. Detachable module/ball grid array package
US5825084A (en) * 1996-08-22 1998-10-20 Express Packaging Systems, Inc. Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4814961U (en) * 1971-06-30 1973-02-20

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH419186A (en) * 1965-03-05 1966-08-31 Escher Wyss Ag Rotor for a centrifugal machine, in particular a steam or gas turbine

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4814961U (en) * 1971-06-30 1973-02-20

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6088574U (en) * 1983-11-24 1985-06-18 日本電気株式会社 Chip carrier type package connection structure
JPH0220847Y2 (en) * 1983-11-24 1990-06-06
US5444296A (en) * 1993-11-22 1995-08-22 Sun Microsystems, Inc. Ball grid array packages for high speed applications
US5666272A (en) * 1994-11-29 1997-09-09 Sgs-Thomson Microelectronics, Inc. Detachable module/ball grid array package
US5825084A (en) * 1996-08-22 1998-10-20 Express Packaging Systems, Inc. Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices

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