JPS58159361A - Multi-layer hybrid integrated circuit device - Google Patents

Multi-layer hybrid integrated circuit device

Info

Publication number
JPS58159361A
JPS58159361A JP4326082A JP4326082A JPS58159361A JP S58159361 A JPS58159361 A JP S58159361A JP 4326082 A JP4326082 A JP 4326082A JP 4326082 A JP4326082 A JP 4326082A JP S58159361 A JPS58159361 A JP S58159361A
Authority
JP
Japan
Prior art keywords
substrates
integrated circuit
hybrid integrated
circuit device
external leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4326082A
Other languages
Japanese (ja)
Other versions
JPS6250063B2 (en
Inventor
Yoshio Miura
三浦　敬男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP4326082A priority Critical patent/JPS58159361A/en
Publication of JPS58159361A publication Critical patent/JPS58159361A/en
Publication of JPS6250063B2 publication Critical patent/JPS6250063B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405—Edge mounted components, e.g. terminals

Abstract

PURPOSE:To obtain a improved multi-layer hybrid integrated circuit device by a method wherein external leads with a forked end are employed to provide a gap between two substrates and to electrically connect said two substrates. CONSTITUTION:Two substrates 10 are arranged so that electrode pads 11 are opposite to one another. External leads 12 with a forked end are placed between the electrode pads 11 and the assembly is heated on a hot plate for soldering. The forked ends of the external leads 12 work as a separating means between the two substrates 10, providing a gap between them. The leads 12 also connect electrically the two subsrates 10 for the integration of the two in terms of circuit functioning. By using the external leads 12 with a forked end, the two substrates 10 are connected electrically to each other and integrated into one body, without using through holes, facilitating the production of multi-layer hybrid integrated circuit devices being a unitary body to function as a circuit by means of the conventional mass-producing method.

Description

【発明の詳細な説明】 本発明は多層混成集積回路装置の改良に関する多層混成
集積回路として周知のものにマイクロモジエールがある
。マイクロモジエールは複数の絶縁基板に所望の小型回
路素子を組み込みスルーホール電極を介して積層したも
のである。斯るマイクロモジュールは小型化は図れるが
、組み込みできる回路素子の制約が大きくすべての回路
番ζ適用できるものではない。またスルーホール電極を
不可欠としているので、製造技術上も量産性δこ乏しい
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the improvement of a multilayer hybrid integrated circuit device. MicroMosier is a well-known multilayer hybrid integrated circuit. MicroMosier is a product in which desired small circuit elements are built into a plurality of insulating substrates and laminated via through-hole electrodes. Although such a micromodule can be miniaturized, there are large restrictions on the circuit elements that can be incorporated, and it cannot be applied to all circuit numbers ζ. Furthermore, since through-hole electrodes are essential, mass productivity δ is poor in terms of manufacturing technology.

そこで、多層の簡易化された構造を第１図に示ｔ−０（
１）は混成集積回路基板、（２）は枠状の離間材、（３
）は外部リードである。本構造では別々の混成集積回路
基板（１）に別々の工程で所望の回路を形成し外部リー
ド（３）を固着した後、枠状の離間材（２）で両基板ｆ
ｌ）（１）を一体化するものである。従ってパッケージ
ング上は多層構造と言えるが、回路上に別々の回路を近
接したにすぎない。これは両基板（１）を電気的に接続
する有効な手段が採り得ないからである。Therefore, a simplified multilayer structure is shown in Figure 1 t-0(
1) is a hybrid integrated circuit board, (2) is a frame-shaped spacer, (3 is
) is an external lead. In this structure, after forming desired circuits on separate hybrid integrated circuit boards (1) in separate steps and fixing external leads (3), both boards f are attached using a frame-shaped spacer (2).
l) It integrates (1). Therefore, although it can be said to have a multilayer structure in terms of packaging, it is simply a circuit with separate circuits placed close to each other. This is because no effective means can be taken to electrically connect both substrates (1).

本発明は断点に鑑みてなされ、従来の欠点を大巾に改善
した多層混成集積回路装置を提供するものである。以下
に第２図および第３図を参照して本発明の一実施例を詳
述する。The present invention has been made in view of the drawbacks and provides a multilayer hybrid integrated circuit device that greatly improves the conventional drawbacks. An embodiment of the present invention will be described in detail below with reference to FIGS. 2 and 3.

本発明に依る多層混成集積回路装置は、第２図の如く、
複数の混成集積回路基板頭と、各基板叫に形成された電
極パ噌ドαυと、本発明の特徴とするかぶら状外部リー
ド（２）より構成される。The multilayer hybrid integrated circuit device according to the present invention is as shown in FIG.
It is composed of a plurality of hybrid integrated circuit board heads, electrode pads αυ formed on each board, and a cover-shaped external lead (2) which is a feature of the present invention.

混成集積回路基板叫としては、セラミックス等の絶縁物
、あるいは表面を酸化したアルミニウム基板を用いる。As the hybrid integrated circuit board, an insulating material such as ceramics or an aluminum substrate with an oxidized surface is used.

また設計上必要であればこれらの基板の組合せでも良い
。斯る基板ａ１１ｈには独自に銅箔番こよる導電路、ス
クリーン印刷番こよる抵抗体あるいはトランジスタ、Ｉ
Ｃ等の半導体素子を付着し所望の回路を形成する。例え
ば金属基板頭上番こは電力消費の大きいパワー回路を、
絶縁基板叫ＩＣは高周波回路を形成しても良い。断る基
板叫は別工程で製造され、スルーホール工程がないので
量産できる。Further, if necessary in terms of design, a combination of these substrates may be used. Such a board a11h has its own conductive paths made of copper foil, resistors or transistors made of screen printing, and I
A semiconductor element such as C is attached to form a desired circuit. For example, a board on a metal board carries a power circuit that consumes a lot of power.
The insulated substrate IC may form a high frequency circuit. The printed circuit board is manufactured in a separate process, and there is no through-hole process, so it can be mass-produced.

電極パ噌ドαυは基板叫の周端部に一定間隔で設ける。The electrode pads αυ are provided at regular intervals on the peripheral edge of the substrate.

斯る電極パッドαυは位置的に対応しており前述した導
電路の形成の際に同時に作ると良い。Such electrode pads αυ correspond to each other in position, and are preferably formed at the same time as the above-described conductive path is formed.

本発明の最大の特徴はかぶら状外部リード（至）・・・
（２）にある。このリード叫・・・（２）は図示の如く
先端部二叉にしたかぶら状に形成され、上述した各基板
叫の対向する電極パ噌ドαυ関に半田付けされる。The biggest feature of the present invention is the turnip-shaped external lead...
(2). This lead wire (2) is formed into a forked tip as shown in the figure, and is soldered to the opposing electrode pads αυ of each of the above-mentioned substrate wires.

すなわち両基板叫を電極パ噌ドαυが対向する様に配置
し、電極パ・ラド（１１）間に外部リード（２）・・・
（２）を配置してホ噌ドブレート上で加熱して半田付け
するのである。That is, both boards are arranged so that the electrode pads αυ face each other, and the external leads (2)... are placed between the electrode pads (11).
(2) is placed and heated on a hot plate to solder it.

斯る本発明の多層混成集積回路装置では、斯る聞手段と
して働き、両基板αＩ（ＩＩ）を一定間隔で離間させる
。また外部リード（２）は両基板叫の電気的接続手段と
しても働き、両基板αｅの回路同志の接続を可能にして
両者の回路機能を一体番こできる。従って第３図に示す
如く外部リード（２）として用いない場合は、先端付近
で切断して除去すると良い。In the multilayer hybrid integrated circuit device of the present invention, it functions as such a means and separates both substrates αI(II) at a constant interval. Further, the external lead (2) also functions as an electrical connection means for both substrates, and enables the circuits of both substrates αe to be connected to each other, so that the circuit functions of both substrates can be integrated. Therefore, if it is not used as an external lead (2) as shown in FIG. 3, it is best to cut it near the tip and remove it.

以上に詳述した如く本発明３ど依れば、かぶら状外部リ
ード（至）によりスルーホール技術を用いず基板間の電
気的接続を行うことがで舎、回路構成上も一体化した多
層混成集積回路装置を従来の量産技術により容易に製造
できる。また本発明は回路基板の選択により幅広い回路
に適用することが可能である。更に本発明では外側に露
出するのは基板の裏側であり、平坦できれいであるので
樹脂モールドする必要もなく、放熱板にも直接取付けで
きる、As described in detail above, according to the third aspect of the present invention, it is possible to electrically connect between boards by means of a cover-shaped external lead (through) without using through-hole technology, and a multilayer hybrid structure with an integrated circuit configuration. Integrated circuit devices can be easily manufactured using conventional mass production techniques. Further, the present invention can be applied to a wide variety of circuits by selecting a circuit board. Furthermore, in the present invention, what is exposed to the outside is the back side of the board, which is flat and clean, so there is no need for resin molding and it can be directly attached to the heat sink.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を説明する断面図、１１２図およびＩＩ
！３図は本発明を説明する断面図および上面図である。 叫は混成集積回路基板、αυは電極パ噌ド、（２）はか
ぶら状の外部リードである。 第１図 第２図Fig. 1 is a sectional view explaining a conventional example, Fig. 112 and II
! FIG. 3 is a sectional view and a top view illustrating the present invention. (2) is a hybrid integrated circuit board, αυ is an electrode pad, and (2) is a cap-shaped external lead. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 １、複数の混成集積回路基板と、該基板の周端番こ設け
た複数の電極パ噌ドと、対向した該電極１４ツドに先端
部を固着したかぶら状外部リードとを具備し、前記基板
の離間と両基板の電気的接続を行うことを特徴とする。 多層混成集積回路装置。[Scope of Claims] 1. A plurality of hybrid integrated circuit boards, a plurality of electrode pads provided at the circumference of the board, and a capped external lead having a tip fixed to the opposing electrode pad. The method is characterized in that the substrate is separated and the two substrates are electrically connected. Multilayer hybrid integrated circuit device.
JP4326082A 1982-03-17 1982-03-17 Multi-layer hybrid integrated circuit device Granted JPS58159361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4326082A JPS58159361A (en) 1982-03-17 1982-03-17 Multi-layer hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4326082A JPS58159361A (en) 1982-03-17 1982-03-17 Multi-layer hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS58159361A true JPS58159361A (en) 1983-09-21
JPS6250063B2 JPS6250063B2 (en) 1987-10-22

Family

ID=12658876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4326082A Granted JPS58159361A (en) 1982-03-17 1982-03-17 Multi-layer hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58159361A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
US5296737A (en) * 1990-09-06 1994-03-22 Hitachi, Ltd. Semiconductor device with a plurality of face to face chips
US5313367A (en) * 1990-06-26 1994-05-17 Seiko Epson Corporation Semiconductor device having a multilayer interconnection structure
US5479051A (en) * 1992-10-09 1995-12-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US5602420A (en) * 1992-09-07 1997-02-11 Hitachi, Ltd. Stacked high mounting density semiconductor devices
NL2021293A (en) * 2017-07-14 2019-01-25 Shindengen Electric Mfg Electronic module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
US5313367A (en) * 1990-06-26 1994-05-17 Seiko Epson Corporation Semiconductor device having a multilayer interconnection structure
US5296737A (en) * 1990-09-06 1994-03-22 Hitachi, Ltd. Semiconductor device with a plurality of face to face chips
US5602420A (en) * 1992-09-07 1997-02-11 Hitachi, Ltd. Stacked high mounting density semiconductor devices
US5479051A (en) * 1992-10-09 1995-12-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
NL2021293A (en) * 2017-07-14 2019-01-25 Shindengen Electric Mfg Electronic module

Also Published As

Publication number Publication date
JPS6250063B2 (en) 1987-10-22

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