JPH0558665B2 - - Google Patents

Info

Publication number
JPH0558665B2
JPH0558665B2 JP62059358A JP5935887A JPH0558665B2 JP H0558665 B2 JPH0558665 B2 JP H0558665B2 JP 62059358 A JP62059358 A JP 62059358A JP 5935887 A JP5935887 A JP 5935887A JP H0558665 B2 JPH0558665 B2 JP H0558665B2
Authority
JP
Japan
Prior art keywords
electrodes
chip carrier
lead
hybrid integrated
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62059358A
Other languages
Japanese (ja)
Other versions
JPS63226053A (en
Inventor
Koji Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62059358A priority Critical patent/JPS63226053A/en
Publication of JPS63226053A publication Critical patent/JPS63226053A/en
Publication of JPH0558665B2 publication Critical patent/JPH0558665B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、高密度混成集積回路のリードレス混
成集積チツプモジユールに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a leadless hybrid integrated chip module for high density hybrid integrated circuits.

従来の技術 従来のリードレス型混成集積回路モジユール
は、単品基板、又は多層集積基板の側面部に外嵌
する導電性部材によつて、複数の電気的取出し電
極を設けたものである。また前記側面部に導電性
インク材料を用いて外部接続用電極端子を形成し
たものである。
2. Description of the Related Art A conventional leadless hybrid integrated circuit module has a plurality of electrical lead-out electrodes formed by conductive members fitted onto the side surface of a single substrate or a multilayer integrated substrate. Moreover, an electrode terminal for external connection is formed on the side surface using a conductive ink material.

発明が解決しようとする問題点 しかし上記従来のものは、回路形成された前記
基板の側面印刷工程が複雑であり、作業上コスト
高となると共に、側面電極の印刷ピツチがバラツ
キ、かつ印刷作業ミスなどによる損失コストが高
くつく欠点がある。また性能的にも、側面電極の
機械的強度が十分得られない欠点を有している。
また本発明はこのような問題点を解決し、製造が
容易なものとすることを目的とする。
Problems to be Solved by the Invention However, in the above-mentioned conventional method, the process of printing the side surfaces of the circuit-formed circuit board is complicated, resulting in high operational costs, and the printing pitch of the side electrodes varies, and errors occur in the printing process. The disadvantage is that the loss costs due to such factors are high. Also, in terms of performance, it has the disadvantage that the mechanical strength of the side electrodes is not sufficient.
Further, it is an object of the present invention to solve these problems and to facilitate manufacturing.

問題点を解決するための手段 本発明は従来の欠点を除去するために、配線回
路構成された印刷回路基板、欠は多層積層基板の
底面の外周部に沿つて入出力信号の内部取出し用
電極を複数個設け、かつ前記内部取出し電極に接
続される外部取出し電極を複数個設けたセラミツ
ク又は成形樹脂から成るチツプキヤリヤの上に、
前記基板を配置したものである。
Means for Solving the Problems In order to eliminate the conventional drawbacks, the present invention provides a printed circuit board having a wiring circuit structure, in which electrodes for internal extraction of input/output signals are provided along the outer periphery of the bottom surface of the multilayer laminated board. on a chip carrier made of ceramic or molded resin, which is provided with a plurality of electrodes connected to the internal electrode, and a plurality of external electrodes connected to the internal electrode.
The above-mentioned substrate is arranged.

作 用 本発明は、配線回路構成された印刷回路基板、
又は多層基板と、外部取出し電極を複数個有する
チツプキヤリヤを個別に作り、積載後、内部及び
外部取出し電極を各々対応させ、半田付した後、
一体化したものであり、このため基板は、基板側
面に取出し用電極を設けることなく、容易に基板
底面のみに内部取出し電極を設けるだけで済み、
印刷作業が容易で、かつ基板エツジ電極部の導通
品質劣化の悪影響も生じない。
Function The present invention provides a printed circuit board configured with a wiring circuit,
Alternatively, a multilayer board and a chip carrier having multiple externally-extracted electrodes are made separately, and after loading, the internal and externally-extracted electrodes are made to correspond to each other, and then soldered.
Because it is an integrated board, there is no need to provide a lead-out electrode on the side of the board, and the internal lead-out electrode can be easily provided only on the bottom of the board.
Printing work is easy, and there is no adverse effect of deterioration in conduction quality of the edge electrode portion of the substrate.

実施例 本発明の一実施例を第1図〜第3図を用いて説
明する。まず第2図示すように印刷配線回路基板
1は、単層、又は多層の配線回路から成り、各層
間はスルホール2、又はビアホールで導通され、
最上層、及び底面に、チツプ部品(能動・受動部
品)7がマウント、又はワイヤーボンデイングさ
れたものであり、底面の外周部に沿つて入出力信
号の内部取り出し電極3を複数個形成している。
なお、9はガラス保護膜である。
Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 to 3. First, as shown in FIG. 2, the printed wiring circuit board 1 consists of a single-layer or multi-layer wiring circuit, and each layer is electrically connected through a through hole 2 or a via hole.
Chip components (active/passive components) 7 are mounted or wire bonded on the top layer and the bottom, and a plurality of internal extraction electrodes 3 for input/output signals are formed along the outer periphery of the bottom. .
Note that 9 is a glass protective film.

一方、前記印刷配線基板1を積載するチツプキ
ヤリヤ4は、第3図のようにパツケージの周壁に
沿つて、前記内部取出し電極3に対応する溝5を
設け、その周辺に半田上がりが可能な外部取出し
電極6を等ピツチで複数個設けた構成である。こ
のチツプキヤリヤ4の上に積載される印刷配線基
板1の内部取出し電極3と前記外部取出し電極6
が半田付されている。また、印刷配線基板1の底
面に突出したチツプ部品7を防湿保護し、かつ印
刷配線基板1とチツプキヤリヤ4の接着を行なう
ため、チツプキヤリヤ中央部の開口部8より、樹
脂を流し込んでいる。なお、印刷配線基板1の上
に耐湿性と絶縁性を向上させるため、ガラス保護
膜9や合成樹脂保護膜が形成されている。
On the other hand, the chip carrier 4 on which the printed wiring board 1 is loaded has a groove 5 along the peripheral wall of the package corresponding to the internal lead-out electrode 3 as shown in FIG. This is a configuration in which a plurality of electrodes 6 are provided at equal pitches. The internal lead-out electrode 3 and the external lead-out electrode 6 of the printed wiring board 1 loaded on this chip carrier 4
is soldered. Further, in order to protect the chip components 7 protruding from the bottom surface of the printed wiring board 1 from moisture and to bond the printed wiring board 1 and the chip carrier 4, resin is poured into the opening 8 at the center of the chip carrier. Note that a glass protective film 9 and a synthetic resin protective film are formed on the printed wiring board 1 in order to improve moisture resistance and insulation.

発明の効果 以上のように本発明は、印刷回路基板や、それ
に電気的導通を図つた外部取出し電極をもつチツ
プキヤリヤを個別に構成することにより、積載さ
れる印刷回路基板の設計自由度が増す。例えば印
刷回路基板の内部取出し電極は、底面に一度の印
刷で構成できるため、単層・多層基板にかかわら
ず、チツプ部品を基板の両面にマウントやワイヤ
ーボンデイングしたものなど、積載可能な混成集
積回路が多岐にわたる。またチツプキヤリヤの外
部取出し電極の形成は、個別に行えるため、安価
な合成樹脂成形基板が使え、かつ半田付接着強度
の強いメタライズ導体電極の採用も可能となる。
またアルミナ基板など機械的強度の強い材質でチ
ツプキヤリヤを構成することにより、当該適用チ
ツプモジユールは、信頼性の高い実装部品とな
る。一方印刷回路基板とチツプキヤリヤの機械的
接続は、内部取出し電極部の半田付以外に、開口
されたチツプキヤリヤの底面より、耐湿保護膜を
兼ねた接着用樹脂を流し込むことにより、印刷回
路基板とチツプキヤリヤの接着をより強固にする
ことも可能である。
Effects of the Invention As described above, according to the present invention, the degree of freedom in designing the printed circuit boards to be loaded is increased by individually configuring the printed circuit boards and the chip carriers having the external lead-out electrodes that are electrically connected to the printed circuit boards. For example, the internal lead-out electrodes of a printed circuit board can be configured by printing once on the bottom surface, so whether it is a single-layer or multi-layer board, it is possible to mount hybrid integrated circuits such as those with chip components mounted or wire bonded on both sides of the board. are wide-ranging. In addition, since the external lead-out electrodes of the chip carrier can be formed individually, it is possible to use an inexpensive synthetic resin molded substrate, and also to use metallized conductor electrodes with strong solder bonding strength.
Furthermore, by constructing the chip carrier from a material with high mechanical strength such as an alumina substrate, the applied chip module becomes a highly reliable mounting component. On the other hand, the mechanical connection between the printed circuit board and the chip carrier is achieved by, in addition to soldering the internal lead-out electrodes, by pouring an adhesive resin that also serves as a moisture-resistant protective film from the open bottom of the chip carrier. It is also possible to make the adhesion stronger.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による混成集積チツ
プモジユールの断面図、第2図は印刷回路基板の
実施例としての多層印刷混成集積基板の断面図、
第3図は積載されるチツプキヤリヤの斜視図であ
る。 1……印刷配線回路基板、3……内部取出し電
極、4……チツプキヤリヤ、5……溝、6……外
部取出し電極、7……チツプ部品、8……開口
部。
FIG. 1 is a sectional view of a hybrid integrated chip module according to an embodiment of the present invention, FIG. 2 is a sectional view of a multilayer printed hybrid integrated board as an embodiment of a printed circuit board,
FIG. 3 is a perspective view of the loaded chip carrier. DESCRIPTION OF SYMBOLS 1... Printed wiring circuit board, 3... Internal lead-out electrode, 4... Chip carrier, 5... Groove, 6... External lead-out electrode, 7... Chip component, 8... Opening.

Claims (1)

【特許請求の範囲】 1 外部取出し電極を周壁に複数個設けたチツプ
キヤリヤ上に、内部取出し電極を前記外部取出し
電極に対応して底面に設けた印刷配線回路基板を
配置し、かつ印刷配線基板の内部取出し電極を前
記チツプキヤリヤの外部取出し電極に電気的に接
続した混成集積チツプモジユール。 2 印刷配線基板は、単層又は多層セラミツク基
板の上面又は底面に、チツプ部品を配置して混成
集積回路を形成したものである特許請求の範囲第
1項に記載の混成集積チツプモジユール。 3 チツプキヤリヤは、内部取出し電極に対応し
て周壁に溝を複数個設け、その溝に半田上りが可
能な外部取出し用の導体電極を設けたものである
特許請求の範囲第1項に記載の混成集積チツプモ
ジユール。 4 チツプキヤリヤは、セラミツク、又は樹脂成
形基材から成り、中央部に貫通する空間を設けた
ものである特許請求の範囲第1項に記載の混成集
積チツプモジユール。
[Scope of Claims] 1. A printed wiring circuit board having internal lead-out electrodes provided on the bottom surface corresponding to the external lead-out electrodes is disposed on a chip carrier having a plurality of external lead-out electrodes on the peripheral wall, and A hybrid integrated chip module in which an internal lead-out electrode is electrically connected to an external lead-out electrode of the chip carrier. 2. The hybrid integrated chip module according to claim 1, wherein the printed wiring board is a hybrid integrated circuit formed by arranging chip components on the top or bottom surface of a single-layer or multilayer ceramic substrate. 3. The chip carrier is a hybrid device according to claim 1, wherein a plurality of grooves are provided in the peripheral wall corresponding to the internal lead-out electrodes, and conductive electrodes for external lead-out to which solder can be applied are provided in the grooves. Integrated chip module. 4. The hybrid integrated chip module according to claim 1, wherein the chip carrier is made of a ceramic or resin molded base material and has a penetrating space in the center.
JP62059358A 1987-03-13 1987-03-13 Hybrid integrated chip module Granted JPS63226053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62059358A JPS63226053A (en) 1987-03-13 1987-03-13 Hybrid integrated chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62059358A JPS63226053A (en) 1987-03-13 1987-03-13 Hybrid integrated chip module

Publications (2)

Publication Number Publication Date
JPS63226053A JPS63226053A (en) 1988-09-20
JPH0558665B2 true JPH0558665B2 (en) 1993-08-27

Family

ID=13110962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62059358A Granted JPS63226053A (en) 1987-03-13 1987-03-13 Hybrid integrated chip module

Country Status (1)

Country Link
JP (1) JPS63226053A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102486A (en) * 1999-07-28 2001-04-13 Seiko Epson Corp Substrate for semiconductor device, semiconductor-chip mounting substrate, semiconductor device, their manufacturing method, circuit board and electronic device

Also Published As

Publication number Publication date
JPS63226053A (en) 1988-09-20

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