JP2970075B2 - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JP2970075B2 JP2970075B2 JP15535191A JP15535191A JP2970075B2 JP 2970075 B2 JP2970075 B2 JP 2970075B2 JP 15535191 A JP15535191 A JP 15535191A JP 15535191 A JP15535191 A JP 15535191A JP 2970075 B2 JP2970075 B2 JP 2970075B2
- Authority
- JP
- Japan
- Prior art keywords
- sided
- sided board
- circuit pattern
- board
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【０００１】[0001]
【産業上の利用分野】本発明は能動素子、受動素子等の
各種素子を搭載するとともに、実装基板等に搭載して前
記素子を実装基板に電気回路接続するためのチップキャ
リヤに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier for mounting various elements such as an active element and a passive element, and for mounting the element on a mounting board or the like to connect the element to an electric circuit.
【０００２】[0002]
【従来の技術】図３は従来提供されているチップキャリ
ヤの断面図である。両面基板１Ａの表面回路パターン１
ａ上に素子４をＡｇペースト等の接着剤５により固着さ
せ、20μφ〜50μφの純金線等の金属細線６を用いて素
子４と表面回路パターン１ａを電気的に接続して回路を
形成する。その後、樹脂枠７等を利用して充填させた封
止樹脂８により素子４等の封止を行う。又、両面基板１
Ａの裏面には裏面回路パターン１ｂ及び接続電極１ｃが
設けられており、スルーホール９ａ，９ｂを通して表面
回路パターン１ａに電気接続し、表面回路パターン１ａ
のみでは構成できない回路の構成を可能とするととも
に、その一部を接続電極として構成し、チップキャリヤ
を実装基板に実装したときに、実装基板に設けた回路パ
ターンに接続電極を接続するように構成している。更
に、実装時に考えられる裏面回路パターン１ｂと実装基
板の回路パターンとの接触による電気的な短絡防止のた
め、接続電極以外の裏面回路パターン１ｂを被覆するソ
ルダーレジスト１１が20〜40μｍの厚さで印刷方式によ
り形成されている。2. Description of the Related Art FIG. 3 is a sectional view of a conventionally provided chip carrier. Surface circuit pattern 1 of double-sided board 1A
The element 4 is fixed on the substrate a with an adhesive 5 such as an Ag paste, and a circuit is formed by electrically connecting the element 4 and the surface circuit pattern 1a using a thin metal wire 6 such as a pure gold wire of 20 μφ to 50 μφ. Thereafter, the element 4 and the like are sealed with the sealing resin 8 filled using the resin frame 7 and the like. Also, double-sided board 1
A back surface circuit pattern 1b and a connection electrode 1c are provided on the back surface of A, and are electrically connected to the front surface circuit pattern 1a through the through holes 9a and 9b.
In addition to enabling the configuration of circuits that cannot be configured only by itself, a part of them is configured as connection electrodes, and when the chip carrier is mounted on the mounting board, the connection electrodes are connected to the circuit pattern provided on the mounting board. doing. Further, in order to prevent an electrical short circuit caused by contact between the back circuit pattern 1b and the circuit pattern of the mounting board, which can be considered at the time of mounting, the solder resist 11 covering the back circuit pattern 1b other than the connection electrodes has a thickness of 20 to 40 μm. It is formed by a printing method.
【０００３】[0003]
【発明が解決しようとする課題】このような従来のチッ
プキャリヤは、裏面回路パターン１ｂと実装基板の回路
パターンとの電気的短絡を防止するためにソルダーレジ
スト１１を印刷しているが、ソルダーレジストには通常
ボイド・ピンホールが発生し易い。又、一般的にスルー
ホール９ａ，９ｂを形成した部分は外周より１段高くメ
ッキされて凸起形状となるため、図４にその部分を拡大
図示するように、この部分Ｘでスルーホールの一部がソ
ルダーレジストから露出することになる。したがって、
前記したボイド・ピンホールやこのスルーホールの露出
によってソルダーレジストによる絶縁効果が低下され、
裏面回路パターンと実装基板の回路パターンの電気的短
絡が生じ、信頼性が低下されるとい問題がある。In such a conventional chip carrier, a solder resist 11 is printed in order to prevent an electrical short circuit between the back circuit pattern 1b and the circuit pattern of the mounting board. In general, voids and pinholes are easily generated. In general, the portion where the through holes 9a and 9b are formed is plated one step higher than the outer periphery to form a protruding shape. Therefore, as shown in an enlarged view in FIG. The part is exposed from the solder resist. Therefore,
The insulating effect of the solder resist is reduced by the above-described void pinhole and exposure of this through hole,
There is a problem that an electrical short circuit occurs between the circuit pattern on the back surface and the circuit pattern on the mounting board, thereby lowering reliability.
【０００４】又、従来のチップキャリヤでは素子の上側
に金属板を設けてシールドを施すことは可能であるが、
素子の裏面側にシールドを施すことができないため、充
分なシールド効果を得ることができず、高周波素子のよ
うにシールドが要求される場合にはこの種のチップキャ
リヤを適用することができないという問題がある。本発
明の目的は、チップキャリヤと実装基板との電気的短絡
を有効に防止したチップキャリヤを提供することにあ
る。又、シールド効果の高いチップキャリヤを提供する
ことにある。In a conventional chip carrier, it is possible to provide a metal plate on the upper side of the element to provide a shield.
The problem is that a shield cannot be provided on the back side of the element, so that a sufficient shielding effect cannot be obtained, and this type of chip carrier cannot be applied when a shield is required as in a high-frequency element. There is. An object of the present invention is to provide a chip carrier in which an electric short circuit between the chip carrier and the mounting board is effectively prevented. Another object is to provide a chip carrier having a high shielding effect.
【０００５】[0005]
【課題を解決するための手段】本発明のチップキャリヤ
は、表面に設けた表面回路パターンに素子等を搭載した
両面基板の裏面に片面基板を一体的に接続し、この片面
基板の裏面にのみ接続電極を設けるとともに、この片面
基板に設けたスルーホールを介して接続電極を両面基板
の表面回路パターン及び裏面回路パターンに電気接続し
た構成とする。又、片面基板を、両面基板に直接接続さ
れる第１片面基板と、この第１片面基板の裏面に接続さ
れる第２片面基板とで構成し、第２片面基板の裏面に接
続電極を形成し、第２片面基板に設けた穴を通して露呈
される第１片面基板の裏面にシールドパターンを形成す
る。Chip carrier of the present invention SUMMARY OF THE INVENTION are integrally connected to one side board on the back surface of the double-sided board having elements or the like on the surface circuit pattern formed on the surface, only the back surface of the single-sided board A connection electrode is provided, and the connection electrode is electrically connected to the front surface circuit pattern and the back surface circuit pattern of the double-sided substrate via through holes provided in the single-sided substrate. Further, the single-sided substrate is composed of a first single-sided substrate directly connected to the double-sided substrate and a second single-sided substrate connected to the backside of the first single-sided substrate, and a connection electrode is formed on the backside of the second single-sided substrate. Then, a shield pattern is formed on the back surface of the first single-sided substrate exposed through a hole provided in the second single-sided substrate.
【０００６】[0006]
【作用】本発明によれば、片面基板によって両面基板の
裏面回路パターンが被覆され、実装基板には片面基板の
裏面が接触されるため、裏面回路パターンが実装基板の
回路パターンに接触して電気的短絡が生じることはな
い。又、第２片面基板に露呈される第１片面基板に設け
たシールドパターンによって素子の裏面側のシールドが
可能とされる。According to the present invention, the backside circuit pattern of the double-sided board is covered with the single-sided board, and the backside of the single-sided board is brought into contact with the mounting board. No short circuit occurs. Further, the shield on the back side of the device can be shielded by the shield pattern provided on the first single-sided substrate exposed on the second single-sided substrate.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の第１実施例を示す断面図である。両
面基板１は表面に表面回路パターン１ａを有し、裏面に
裏面回路パターン１ｂを有している。前記表面回路パタ
ーン１ａの所要位置には素子、例えば半導体素子４を接
着剤５で固着し、表面回路パターン１ａの他の部分と金
属細線６を用いてワイヤボンディング法により回路接続
する。そして、電気的・機械的保護のため周囲に樹脂
枠、或いは印刷枠７を形成し、この枠７内に充填した封
止樹脂８により封止している。又、両面基板１の裏面に
は、片面基板２の表面側を一体的に接続する。この片面
基板２の裏面には接続電極２ａを設けており、前記両面
基板１の表面回路パターン１ａ或いは裏面回路パターン
１ｂと接続電極２ａとはこれら両面基板１及び片面基板
２を通して形成したスルーホール９ａ或いは端面スルー
ホール９ｂによって電気接続を行っている。Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. The double-sided board 1 has a front surface circuit pattern 1a on the front surface and a back surface circuit pattern 1b on the rear surface. An element, for example, a semiconductor element 4 is fixed to a required position of the surface circuit pattern 1 a with an adhesive 5, and is connected to another part of the surface circuit pattern 1 a by a wire bonding method using a thin metal wire 6. Then, a resin frame or a printing frame 7 is formed around the periphery for electrical and mechanical protection, and the frame 7 is sealed with a sealing resin 8 filled therein. Also, the front side of the single-sided board 2 is integrally connected to the back side of the double-sided board 1. A connection electrode 2a is provided on the back surface of the single-sided substrate 2, and the surface circuit pattern 1a or the backside circuit pattern 1b of the double-sided substrate 1 and the connection electrode 2a are formed through the through-hole 9a formed through the double-sided substrate 1 and the single-sided substrate 2. Alternatively, the electrical connection is made through the end face through hole 9b.
【０００８】この構造によれば、チップキャリヤを実装
する実装基板パターンとの接触部分は全て片面基板２の
裏面側となり、この裏面側には接続電極２ａのみが存在
し、他の回路パターンは存在していない。したがって、
従来のチップキャリヤに見られたようなソルダーレジス
トのピンホール・ボイド、或いはソルダーレジストが存
在しない部分での電気的短絡が生じることはない。According to this structure, all contact portions with the mounting board pattern on which the chip carrier is mounted are on the back side of the single-sided board 2, and only the connection electrodes 2a are present on the back side, and other circuit patterns are present. I haven't. Therefore,
There is no pinhole or void in the solder resist as in a conventional chip carrier, or an electrical short circuit in a portion where no solder resist exists.
【０００９】図２は本発明の第２実施例を示す断面図で
ある。例えば板厚が 0.2〜 0.6mmの両面基板１の裏面回
路パターン１ａ側に、板厚が 0.1〜 0.2mmの片面基板２
を一体的に接続している。そして、この片面基板２の裏
面には、更に板厚が 0.1〜 0.2mmの第２片面基板３を貼
付けており、この第２片面基板３は枠状に形成され、そ
の中央部は第１片面基板２の裏面が露呈されている。
又、第２片面基板３の裏面には接続電極３ａが形成され
ており、前記両面基板１とは、第１片面基板２及び第２
片面基板３を通して設けられた端面スルーホール９ｂに
よって電気接続を行っている。更に、この第２片面基板
３の中央部には前記第１片面基板２の裏面が露呈されて
おり、この第１片面基板２の裏面にはシールドパターン
１０が形成され、ソルダーレジスト１１によって被覆し
ている。FIG. 2 is a sectional view showing a second embodiment of the present invention. For example, on the backside circuit pattern 1a side of the double-sided board 1 having a board thickness of 0.2 to 0.6 mm, a single-sided board 2 having a board thickness of 0.1 to 0.2 mm is provided.
Are connected integrally. A second single-sided substrate 3 having a thickness of 0.1 to 0.2 mm is further adhered to the back surface of the single-sided substrate 2. The second single-sided substrate 3 is formed in a frame shape, and the central portion thereof is the first single-sided substrate. The back surface of the substrate 2 is exposed.
A connection electrode 3a is formed on the back surface of the second single-sided substrate 3, and the double-sided substrate 1 is different from the first single-sided substrate 2 and the second single-sided substrate 2.
Electrical connection is made by end-face through holes 9b provided through the single-sided substrate 3. Further, the back surface of the first single-sided substrate 2 is exposed at the center of the second single-sided substrate 3, and a shield pattern 10 is formed on the back surface of the first single-sided substrate 2 and is covered with a solder resist 11. ing.
【００１０】尚、前記両面基板１の表面回路パターン１
ａには素子４を接着剤５で接着し、20〜50μφの純金線
からなる金属細線６で前記接続し、樹脂枠、或いは印刷
枠７を利用して樹脂８で封止することは第１実施例と同
じである。又、この場合、樹脂封止の際、樹脂硬化前に
アルミニウム箔或いは銅箔で形成された金属板１２を樹
脂８上に浮かせて樹脂を硬化させることで樹脂表面に固
着させる。前記金属板１２とシールドパターン１０は溶
接法，半田付法等により電気的にＧＮＤに接続してあ
る。The surface circuit pattern 1 of the double-sided board 1
a, the element 4 is bonded with an adhesive 5, connected with a thin metal wire 6 made of a pure gold wire of 20 to 50 μφ, and sealed with a resin 8 using a resin frame or a printing frame 7. This is the same as the embodiment. In this case, at the time of resin sealing, the metal plate 12 made of aluminum foil or copper foil is floated on the resin 8 before the resin is cured, and the resin is cured to be fixed to the resin surface. The metal plate 12 and the shield pattern 10 are electrically connected to GND by a welding method, a soldering method, or the like.
【００１１】この構造においても、第２片面基板３の裏
面には接続電極３ａが存在するのみであるため、電気的
な短絡を防止することができる。又、この構成では、金
属板１２とシールドパターン１０を設けたことによるシ
ールド機能を有したチップキャリヤとして構成すること
ができる。更に、シールドパターン１０と接続電極３ａ
との間には、第２片面基板３の厚さに相当する段差が設
けられるため、実装性（接続，洗浄）の向上等、多種の
機能向上を図ることもできる。Also in this structure, since only the connection electrode 3a is present on the back surface of the second single-sided substrate 3, an electrical short circuit can be prevented. Further, in this configuration, it is possible to configure a chip carrier having a shielding function by providing the metal plate 12 and the shield pattern 10. Further, the shield pattern 10 and the connection electrode 3a
Since a step corresponding to the thickness of the second single-sided substrate 3 is provided between them, various functions can be improved, such as improvement in mountability (connection, cleaning).
【００１２】[0012]
【発明の効果】以上説明したように本発明は、裏面にの
み接続電極を有する片面基板を、素子を搭載した両面基
板の裏面回路パターン側にスルーホールを介して接続し
ているので、実装基板には片面基板の裏面側が接触され
ることになり、実装基板との電気的短絡を防止する効果
がある。この場合、接続電極あるいは接続電極と両面基
板の回路パターンとを接続するための電極がスルーホー
ルであるために、片面基板の側面には当該電極が突出状
態に形成されることがなく、片面基板の側面における電
気的短絡も防止できる。又、片面基板を第１片面基板と
第２片面基板とで構成することで、第１片面基板にシー
ルドパターンを形成することが可能となり、このシール
ドパターンによって素子をシールドすることができると
いう効果もある。この場合、第２片面基板によって、実
装面とシールドパターンとの間に段差が形成され、実装
性（接続，洗浄）の向上が図れるという効果も有する。As described above, the present invention provides a
Since the single-sided board having only connection electrodes is connected to the backside circuit pattern side of the double-sided board on which the elements are mounted via through holes, the backside of the single-sided board comes into contact with the mounting board. Has the effect of preventing an electrical short circuit with In this case, the connection electrode or the connection electrode and the double-sided base
The electrodes for connecting to the circuit pattern on the board
The electrodes are protruding on the side of the single-sided substrate.
Is not formed in the
A mechanical short circuit can also be prevented. Also, by forming the single-sided substrate with the first single-sided substrate and the second single-sided substrate, it is possible to form a shield pattern on the first single-sided substrate, and it is possible to shield the element by the shield pattern. There is also an effect that can be done. In this case, a step is formed between the mounting surface and the shield pattern by the second single-sided substrate, and there is also an effect that the mountability (connection, cleaning) can be improved.
【図１】本発明のチップキャリヤの第１実施例の断面図
である。FIG. 1 is a sectional view of a first embodiment of a chip carrier of the present invention.
【図２】本発明のチップキャリヤの第２実施例の断面図
である。FIG. 2 is a sectional view of a second embodiment of the chip carrier of the present invention.
【図３】従来のチップキャリヤの断面図である。FIG. 3 is a cross-sectional view of a conventional chip carrier.
【図４】図３のチップキャリヤの問題点を説明するため
の拡大断面図である。FIG. 4 is an enlarged sectional view for explaining a problem of the chip carrier of FIG. 3;
１ 両面基板 １ａ 表面回路パターン １ｂ
裏面回路パターン ２ 片面基板（第１片面基板） ３ 第２片面基板 ２ａ，３ａ 接続電極 ４ 素子 ８ 封止樹脂 ９ａ，９ｂ スルーホール １０ シールドパターン １２ 金属板1 double-sided board 1a surface circuit pattern 1b
Back circuit pattern 2 Single-sided substrate (first single-sided substrate) 3 Second single-sided substrate 2a, 3a Connection electrode 4 Element 8 Sealing resin 9a, 9b Through hole 10 Shield pattern 12 Metal plate
Claims (2)
を搭載し、裏面に設けた裏面回路パターンで所要の電気
回路を構成する両面基板で構成されるチップキャリヤに
おいて、前記両面基板の裏面に片面基板を一体的に接続
し、この片面基板の裏面にのみ接続電極を設けるととも
に、前記片面基板に設けたスルーホールを介して前記接
続電極を前記表面回路パターン及び裏面回路パターンに
電気接続したことを特徴とするチップキャリヤ。1. A chip carrier comprising a double-sided board on which elements and the like are mounted on a front-side circuit pattern provided on a front side and a required electric circuit is formed by a back-side circuit pattern provided on a back side. the single-sided board and integrally connected, is provided with the connection electrode only on the rear surface of the single-sided board, the contact <br/> the surface circuit connection electrode pattern and the rear surface circuit pattern via through holes provided in the single-sided board A chip carrier electrically connected to a chip carrier.
を搭載し、裏面に設けた裏面回路パターンで所要の電気
回路を構成する両面基板で構成されるチップキャリヤに
おいて、前記両面基板の裏面に片面基板を一体的に接続
し、この片面基板の裏面に接続電極を設けるとともに、
前記片面基板に設けたスルーホールを介して前記接続電
極を前記表面回路パターン及び裏面回路パターンに電気
接続し、前記片面基板は、前記両面基板に直接接続され
る第１片面基板と、この第１片面基板の裏面に接続され
る第２片面基板とで構成され、前記第２片面基板の裏面
に接続電極を形成し、前記第２片面基板に設けた穴を通
して露呈される前記第１片面基板の裏面にシールドパタ
ーンを形成したことを特徴とするチップキャリヤ。2. An element or the like on a surface circuit pattern provided on the surface.
And the required electric power is provided by the backside circuit pattern provided on the backside.
For chip carriers composed of double-sided boards that make up circuits
In this case, a single-sided board is integrally connected to the back side of the double-sided board.
And, while providing the connection electrode on the back surface of the single-sided substrate,
Through the through holes provided in the single-sided board, the connection
Electrodes are applied to the front and back circuit patterns
Connect the single-sided board includes a first single-sided board to be connected directly to the double-sided substrate is composed of a second single-sided board to be connected to the back surface of the first single-sided board, on the back surface of the second single-sided board forming a connection electrode, the chip carrier, characterized in that the formation of the shield pattern on the back surface of the first single-sided board to be exposed through the hole formed in the second single-sided board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15535191A JP2970075B2 (en) | 1991-05-31 | 1991-05-31 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15535191A JP2970075B2 (en) | 1991-05-31 | 1991-05-31 | Chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04354355A JPH04354355A (en) | 1992-12-08 |
| JP2970075B2 true JP2970075B2 (en) | 1999-11-02 |
Family
ID=15604002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15535191A Expired - Fee Related JP2970075B2 (en) | 1991-05-31 | 1991-05-31 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2970075B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07297560A (en) * | 1994-04-28 | 1995-11-10 | Hitachi Ltd | Multilayer printed wiring board and its mounting structure |
| JP2001244376A (en) | 2000-02-28 | 2001-09-07 | Hitachi Ltd | Semiconductor device |
-
1991
- 1991-05-31 JP JP15535191A patent/JP2970075B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04354355A (en) | 1992-12-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |