JPS63283051A - Substrate for hybrid integrated circuit device - Google Patents
Substrate for hybrid integrated circuit deviceInfo
- Publication number
- JPS63283051A JPS63283051A JP11846687A JP11846687A JPS63283051A JP S63283051 A JPS63283051 A JP S63283051A JP 11846687 A JP11846687 A JP 11846687A JP 11846687 A JP11846687 A JP 11846687A JP S63283051 A JPS63283051 A JP S63283051A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- insulating substrate
- substrate
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置用基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a substrate for a hybrid integrated circuit device.
従来、混成集積回路装置用基板は、絶縁基板上に回路部
品搭載用ランド、配線及び端子パッドを設けておき、前
記ランドを前記端子パッドにはんだ付は等により接続を
行うか、あるいは外部端子をあらかじめ端子パッドに接
続した後、回路部品の搭載を行っていた。Conventionally, boards for hybrid integrated circuit devices are provided with lands for mounting circuit components, wiring, and terminal pads on an insulating board, and the lands are connected to the terminal pads by soldering, etc., or external terminals are connected to the terminal pads by soldering or the like. After connecting to the terminal pads in advance, circuit components were mounted.
第２図は従来の混成集積回路装置の一例を示す斜視図で
ある。FIG. 2 is a perspective view showing an example of a conventional hybrid integrated circuit device.
第２図に示すように、ます、平坦な面を持つアルミナセ
ラミック等の絶縁基板１１上に端子パッド１５と配線層
１６等の導体層をタングステンまたはモリブデンペース
トを塗布、焼成して形成する。As shown in FIG. 2, terminal pads 15 and conductor layers such as wiring layers 16 are formed on an insulating substrate 11 having a flat surface made of alumina ceramic or the like by applying tungsten or molybdenum paste and firing.
次に、後工程の外装樹脂封止後に外部に露出する導体層
、例えば端子パッド１５の表面にニッケルめっきを行っ
た後、更にその上に金めつきを行う。Next, after nickel plating is performed on the surface of the conductor layer exposed to the outside after the exterior resin sealing in a later step, for example, the surface of the terminal pad 15, gold plating is further performed thereon.
次に、絶縁基板１１に回路部品を搭載する。Next, circuit components are mounted on the insulating substrate 11.
次に、リン青銅等の金属板を成形して作った外部端子１
３を端子パッド１５に接するように絶縁基板１１に挟み
こみ、はんだ付けを行う。Next, external terminal 1 made by molding a metal plate such as phosphor bronze
3 is sandwiched between the insulating substrate 11 so as to be in contact with the terminal pad 15, and soldered.
最後に、モールド成形等により外装樹脂にて外部端子１
３以外の部分を封止し、混成集積回路装置を得る。Finally, the external terminal 1 is made with exterior resin by molding etc.
The parts other than 3 are sealed to obtain a hybrid integrated circuit device.
上述したように、従来の絶縁基板の端子パッドは、ラン
ド、配線が形成されている絶縁基板主面上に形成されて
いるため、外部端子を端子パッドにはんだ付けする場合
に、はんたが流れて隣接する端子パッドが短絡すること
があるという問題がある。更に、混成集積回路装置をプ
リント配線板に実装する場合には、絶縁基板の端子パッ
ドの形成された面がプリント配線板に対向して接続され
るのて、接続するはんだが流れて隣接する端子パッドを
短絡し、短絡した場合でも短絡部が絶縁基板の裏面にあ
るため外観の点検では検出出来ないという問題点があっ
た。As mentioned above, the terminal pads of conventional insulating substrates are formed on the main surface of the insulating substrate on which lands and wiring are formed, so when soldering external terminals to the terminal pads, there is a problem with solder. There is a problem in that the current may flow and short-circuit adjacent terminal pads. Furthermore, when a hybrid integrated circuit device is mounted on a printed wiring board, the surface of the insulating substrate on which the terminal pads are formed is connected to the printed wiring board so that the connecting solder flows and connects to the adjacent terminal. There is a problem in that even if the pads are short-circuited, the short circuit cannot be detected by external inspection because the short circuit is on the back side of the insulating substrate.
本発明の目的は、はんだが隣の端子パッドへ流れるのを
防止し、隣接する端子パッドとの間の短絡のない混成集
積回路装置用基板を提供することにある。An object of the present invention is to provide a substrate for a hybrid integrated circuit device that prevents solder from flowing to adjacent terminal pads and prevents short circuits between adjacent terminal pads.
本発明の混成集積回路装置用基板は、絶縁基板と、該絶
縁基板上の周辺部に形成された複数の端子パッドと、該
端子パッドに接続する配線層と、前記絶縁基板の端面の
前記端子パッドとそれぞれ対応する位置に取付けた外部
端子とを有する混成集積回路装置用基板において、前記
端子パッドか形成される前記絶縁基板部分に前記外部端
子の板厚よりも深く、かつ、底部が平坦なくぼみを設け
である。A substrate for a hybrid integrated circuit device of the present invention includes an insulating substrate, a plurality of terminal pads formed on a peripheral portion of the insulating substrate, a wiring layer connected to the terminal pads, and the terminals on an end surface of the insulating substrate. In a substrate for a hybrid integrated circuit device having pads and external terminals attached at corresponding positions, the insulating substrate portion where the terminal pads are formed is deeper than the thickness of the external terminal and has a flat bottom. It is provided with a depression.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ＞、（ｂ）は本発明の一実施例を示す斜視図
及びＡ−Ａ′線断面図である。FIGS. 1(a) and 1(b) are a perspective view and a sectional view taken along the line A-A', showing an embodiment of the present invention.
第１図（ａ＞、（ｂ）に示すように、ます、アルミナセ
ラミック等の絶縁基板１の周辺部に外部端子３の板厚よ
りも深く、かつ、底部が平坦なくぼみを設ける。次に絶
縁基板１に配線層６を、くぼみの底部に端子パッド５を
、そして配線層６と端子パッド５とを接続する導体層を
側壁面に、タングステンまたはモリブデンペーストの塗
布、焼成により形成する。As shown in FIGS. 1(a) and 1(b), a recess with a flat bottom and deeper than the thickness of the external terminal 3 is provided at the periphery of the insulating substrate 1 made of alumina ceramic or the like.Next, A wiring layer 6 is formed on the insulating substrate 1, a terminal pad 5 is formed at the bottom of the recess, and a conductor layer connecting the wiring layer 6 and the terminal pad 5 is formed on the side wall surface by applying tungsten or molybdenum paste and firing.
次に、後工程の外装樹脂封止後に外部に露出する導体層
部分の表面にニッケルめっきを行った後、更に金めつき
を行う。Next, after nickel plating is performed on the surface of the conductor layer portion exposed to the outside after the exterior resin sealing in the post-process, gold plating is further performed.
次に、絶縁基板１上に回路部品を搭載する。Next, circuit components are mounted on the insulating substrate 1.
次に、リン青銅等の金属板を成形した外部端子３を底部
の端子パッド５に接するようにくぼみ２の端子パッド５
にはんだ付けする。このとき、溶融したけんだ４はくぼ
みの壁に遮られて隣接する端子パッド５に流れることが
なく、隣接する端子パッドとの短絡を防止出来る。Next, the external terminal 3 made of a metal plate such as phosphor bronze is placed in contact with the terminal pad 5 in the recess 2 so as to be in contact with the terminal pad 5 at the bottom.
to solder. At this time, the molten solder 4 is blocked by the wall of the recess and does not flow to the adjacent terminal pad 5, thereby preventing short circuit with the adjacent terminal pad.
最後に、モールド成形等により外装樹脂にて外部端子以
外の部分を封止し混成集積回路装置を得る。Finally, parts other than the external terminals are sealed with an exterior resin by molding or the like to obtain a hybrid integrated circuit device.
このようにして得られた混成集積回路装置をプリント配
線板に実装する場合には、くぼみ２の形成された面がプ
リント配線板に対向して接続されるので、はんだの流れ
がくぼみ２の壁によって遮られて隣接する端子パッド５
との短絡が防止出来る。When the hybrid integrated circuit device obtained in this way is mounted on a printed wiring board, the surface on which the recess 2 is formed is connected to the printed wiring board facing the printed wiring board, so that the flow of solder is directed to the wall of the recess 2. adjacent terminal pad 5 blocked by
This can prevent short circuits.
以上説明したように、本発明は、混成集積回路装置用基
板の端子パッドが形成される絶縁基板部分に外部端子の
板厚よりも深く、かつ、底部が平坦なくぼみを設けるこ
とにより次に列挙する効果を有する。As explained above, the present invention provides a recess which is deeper than the board thickness of the external terminal and has a flat bottom in the insulating substrate portion where the terminal pad of the hybrid integrated circuit device substrate is formed. It has the effect of
（１）端子パッドに外部端子を接続するときのはんだ付
けの際に隣接する端子パッドとの短絡を防止出来る。(1) Short circuits with adjacent terminal pads can be prevented during soldering when connecting external terminals to terminal pads.
（２）混成集積回路装置をプリント基板に実装するとき
のはんだ付けの際に隣接する端子パッドとの短絡を防止
出来る。(2) Short circuits with adjacent terminal pads can be prevented during soldering when the hybrid integrated circuit device is mounted on a printed circuit board.
第１図（ａ）、（ｂ）は本発明の一実施例を示す斜視図
及びＡ−Ａ′線断面図、第２図は従来の混成集積回路装
置用基板の一例を示す斜視図であ６一
る。
１・・・絶縁基板、２・・・くぼみ、３・・外部端子、
４・・・はんた、５・・・端子バット、６・・・配線層
、１１・・・絶縁基板、１３・・・外部端子、１５・・
・端子パッド、１６・・・配線層。FIGS. 1(a) and 1(b) are a perspective view and a sectional view taken along the line A-A' of an embodiment of the present invention, and FIG. 2 is a perspective view showing an example of a conventional board for a hybrid integrated circuit device. 6. 1... Insulating board, 2... Hollow, 3... External terminal,
4... Solder, 5... Terminal bat, 6... Wiring layer, 11... Insulating board, 13... External terminal, 15...
- Terminal pad, 16... wiring layer.
Claims (1)
の端子パッドと、該端子パッドに接続する配線層と、前
記絶縁基板の端面の前記端子パッドとそれぞれ対応する
位置に取付けた外部端子とを有する混成集積回路装置用
基板において、前記端子パッドが形成される前記絶縁基
板部分に前記外部端子の板厚よりも深く、かつ、底部が
平坦なくぼみを設けたことを特徴とする混成集積回路装
置用基板。an insulating substrate, a plurality of terminal pads formed around the insulating substrate, a wiring layer connected to the terminal pads, and an external terminal attached to an end surface of the insulating substrate at positions corresponding to the terminal pads, respectively. A substrate for a hybrid integrated circuit device having a substrate for a hybrid integrated circuit device, wherein a recess is provided in the insulating substrate portion where the terminal pad is formed, the recess being deeper than the board thickness of the external terminal and having a flat bottom. Board for circuit devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11846687A JPS63283051A (en) | 1987-05-14 | 1987-05-14 | Substrate for hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11846687A JPS63283051A (en) | 1987-05-14 | 1987-05-14 | Substrate for hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63283051A true JPS63283051A (en) | 1988-11-18 |
Family
ID=14737362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11846687A Pending JPS63283051A (en) | 1987-05-14 | 1987-05-14 | Substrate for hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63283051A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0941020A2 (en) * | 1998-03-04 | 1999-09-08 | Philips Patentverwaltung GmbH | Printed circuit board having SMD components |
| US6320247B2 (en) * | 1996-07-31 | 2001-11-20 | Oki Electric Industry Co., Ltd. | Unit type clip lead terminal, clip lead terminal connecting method, lead terminal connecting board, and method of producing board with lead terminals |
| EP0952761A4 (en) * | 1996-05-31 | 2005-06-22 | Rohm Co Ltd | Method for mounting terminal on circuit board and circuit board |
| US20170202082A1 (en) * | 2016-01-07 | 2017-07-13 | Nhk Spring Co., Ltd. | Thin circuit board having wall for solder material |
-
1987
- 1987-05-14 JP JP11846687A patent/JPS63283051A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0952761A4 (en) * | 1996-05-31 | 2005-06-22 | Rohm Co Ltd | Method for mounting terminal on circuit board and circuit board |
| US6320247B2 (en) * | 1996-07-31 | 2001-11-20 | Oki Electric Industry Co., Ltd. | Unit type clip lead terminal, clip lead terminal connecting method, lead terminal connecting board, and method of producing board with lead terminals |
| EP0941020A2 (en) * | 1998-03-04 | 1999-09-08 | Philips Patentverwaltung GmbH | Printed circuit board having SMD components |
| EP0941020A3 (en) * | 1998-03-04 | 2001-02-07 | Philips Patentverwaltung GmbH | Printed circuit board having SMD components |
| US20170202082A1 (en) * | 2016-01-07 | 2017-07-13 | Nhk Spring Co., Ltd. | Thin circuit board having wall for solder material |
| US10021781B2 (en) * | 2016-01-07 | 2018-07-10 | Nhk Spring Co., Ltd. | Thin circuit board having wall for solder material |
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