JPS63226053A - Hybrid integrated chip module - Google Patents

Hybrid integrated chip module

Info

Publication number
JPS63226053A
JPS63226053A JP62059358A JP5935887A JPS63226053A JP S63226053 A JPS63226053 A JP S63226053A JP 62059358 A JP62059358 A JP 62059358A JP 5935887 A JP5935887 A JP 5935887A JP S63226053 A JPS63226053 A JP S63226053A
Authority
JP
Japan
Prior art keywords
chip carrier
electrodes
internal
hybrid integrated
wiring circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62059358A
Other languages
Japanese (ja)
Other versions
JPH0558665B2 (en
Inventor
Koji Nishida
孝治 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62059358A priority Critical patent/JPS63226053A/en
Publication of JPS63226053A publication Critical patent/JPS63226053A/en
Publication of JPH0558665B2 publication Critical patent/JPH0558665B2/ja
Granted legal-status Critical Current

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Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To facilitate a printing process and prevent a substrate edge electrode section from degrading in conductivity by a method wherein a plurality of internal leadout electrodes are provided along the bottom circumference of a substrate mounted with a wiring circuit and the substrate is placed on a chip carrier provided with a plurality of external leadout electrodes to be connected to said internal leadout electrodes. CONSTITUTION:A printed wiring circuit substrate 1 includes a single-layer or multilayer wiring circuit, and is provided with a plurality of internal leadout electrodes 3 along its bottom circumference for input/output signals. A glass- made protecting film 9 is provided. In a chip carrier 4, along the peripheral walls of a package, grooves 5 are provided, which correspond to the internal leadout electrodes 3. Along the circumference of the chip carrier 4, a plurality of solderable external leadout electrodes 6 are built at equal intervals. The internal leadout electrodes 3 of the printed wiring circuit substrate 1 to be installed thereon are soldered to said external leadout electrodes 6. Resin is caused to flow into an opening 8 provided at the middle of the chip carrier 4 for the protection of chip parts 7 against moisture. The resin also establishes adhesion between the printed wiring circuit substrate 1 and chip carrier 4.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、高密度混成集積回路のリードレス混成集積チ
ップモジュールに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to leadless hybrid integrated chip modules of high density hybrid integrated circuits.

従来の技術 従来のリードレス型混成集積回路モジュールは、単品基
板、又は多層積層基板の側面部に外嵌する導電性部材に
よって、複数の電気的取出し電極を設けたものである。
BACKGROUND OF THE INVENTION A conventional leadless hybrid integrated circuit module has a plurality of electrical lead-out electrodes formed by conductive members fitted onto the side surface of a single substrate or a multilayer laminated substrate.

また前記側面部に導電性インク材料を用いて外部接続用
電極端子を形成したものである。
Moreover, an electrode terminal for external connection is formed on the side surface using a conductive ink material.

発明が解決しようとする問題点 しかし上記従来のものは、回路形成された前記基板の側
面印刷工程が複雑であり、作業上コスト高となると共に
、側面電極の印刷ピッチがバラツキ、かつ印刷作業ミス
などによる損失コストが高くつく欠点がある。また性能
的にも、側面電極の機械的強度が十分得られない欠点を
有している。
Problems to be Solved by the Invention However, in the above-mentioned conventional method, the process of printing the side surfaces of the circuit-formed circuit board is complicated, resulting in high operational costs, and the printing pitch of the side electrodes varies, and errors occur in the printing process. The disadvantage is that the loss costs due to such factors are high. Also, in terms of performance, it has the disadvantage that the mechanical strength of the side electrodes is not sufficient.

また本発明はこのような問題点を解決し、製造が容易な
ものとすることを目的とする。
Further, it is an object of the present invention to solve these problems and to facilitate manufacturing.

問題点を解決するための手段 本発明は従来の欠点を除去するために、配線回路構成さ
れた印刷回路基板、欠は多層積層基板の底面の外周部に
清って入出力信号の内部取出し用電極を複数個設け、か
つ前記内部取出し電極に接続される外部取出し電極を複
数個設けたセラミック又は成形樹脂から成るチップキャ
リヤの上に、前記基板を配置したものである。
Means for Solving the Problems In order to eliminate the drawbacks of the prior art, the present invention has a printed circuit board configured with a wiring circuit, and a multi-layer laminated board that is equipped with a printed circuit board, in which the outer periphery of the bottom surface is cleaned for internal extraction of input/output signals. The substrate is placed on a chip carrier made of ceramic or molded resin and provided with a plurality of electrodes and a plurality of external electrodes connected to the internal electrodes.

作用 本発明は、配線回路構成された印刷回路基板、又は多層
基板と、外部取出し電極を複数個有するチップキャリヤ
を個別に作り、積載後、内部及び外部取出し電極を各々
対応させ、半田付した後、一体化したものであり、この
ため基板は、基板側面に取出し用電極を設けることなく
、容易に基板底面のみに内部取出し電極を設けるだけで
済み、印刷作業が容易で、かつ基板エツジ電極部の導通
品質劣化の悪影響も生じない。
Effects of the present invention The printed circuit board or multilayer board configured with a wiring circuit and the chip carrier having a plurality of external lead-out electrodes are individually manufactured, and after being loaded, the internal and external lead-out electrodes are made to correspond to each other, and then soldered. Therefore, the board does not need to provide lead-out electrodes on the side of the board, and only the internal lead-out electrodes are provided on the bottom of the board, which makes printing work easy, and there is no need to provide lead-out electrodes on the board edge electrodes. There is no adverse effect of deterioration in conduction quality.

実施例 本発明の一実施例を第1図〜第3図を用いて説明する。Example An embodiment of the present invention will be described using FIGS. 1 to 3.

まず第2図示すように印刷配線回路基板1は、単層、又
は多層の配線回路から成り、各層間はスルホール2.又
はピアホールで導通され、最上層、及び底面に、チップ
部品(能動・受動部品)7がマウント、又はワイヤーボ
ンディングされたものであり、底面の外周部に清って入
出力信号の内部取り出し電極3を複数個形成している。
First, as shown in FIG. 2, the printed wiring circuit board 1 consists of a single-layer or multi-layer wiring circuit, and there are through holes 2 between each layer. Alternatively, it is electrically connected through a peer hole, and chip components (active/passive components) 7 are mounted or wire bonded on the top layer and the bottom surface, and internal extraction electrodes 3 for input/output signals are formed on the outer periphery of the bottom surface. It forms multiple pieces.

なお、9はガラス保護膜である。Note that 9 is a glass protective film.

一方、前記印刷配線基板1を積載するチップキャリヤ4
は、第3図のようにパッケージの周壁に泊って、前記内
部取出し電極3に対応する溝5を設け、その周辺に半田
上がりが可能な外部取出し電極6を等ピッチで複数個設
けた構成である。このチップキャリヤ4の上に積載され
る印刷配線基板1の内部取出し電極3と前記外部取出し
電極6が半田付されている。また、印刷配線基板1の底
面に突出したチップ部品γを防湿保護し、かつ印刷配線
基板1とチップキャリヤ4の接着を行なうため、チップ
キャリヤ中央部の開口部8より、樹脂金流し込んでいる
。なお、印刷配線基板1の上に耐湿性と絶縁性を向上さ
せるため、ガラス保護膜9や合成樹脂保護膜が形成され
ている。
On the other hand, a chip carrier 4 on which the printed wiring board 1 is loaded
As shown in Fig. 3, a groove 5 is provided on the peripheral wall of the package to correspond to the internal lead-out electrode 3, and a plurality of external lead-out electrodes 6 to which solder can be applied are provided around the groove 5 at equal pitches. be. The internal lead-out electrode 3 and the external lead-out electrode 6 of the printed wiring board 1 mounted on the chip carrier 4 are soldered. Further, in order to protect the chip component γ protruding from the bottom surface of the printed wiring board 1 from moisture and to bond the printed wiring board 1 and the chip carrier 4, resin gold is poured into the opening 8 at the center of the chip carrier. Note that a glass protective film 9 and a synthetic resin protective film are formed on the printed wiring board 1 in order to improve moisture resistance and insulation.

発明の効果 以上のように本発明は、印刷回路基板と、それに電気的
導通を図った外部取出し電極をもつチップキャリヤを個
別に構成することにより、積載される印刷回路基板の設
計自由度が増す。例えば印刷回路基板の内部取出し電極
は、底面に一度の印刷で構成できるため、単層・多層基
板にかかわらず、チップ部品を基板の両面にマウントや
ワイヤーボンディングしたものなど、積載可能な混成集
積回路が多岐にわたる。またチップキャリヤの外部取出
し電極の形成は、個別に行えるため、安価な合成樹脂成
形基板が使え、かつ半田付接着強度の強いメタライズ導
体電極の採用も可能となる。
Effects of the Invention As described above, the present invention increases the degree of freedom in designing the printed circuit board to be loaded by separately configuring a printed circuit board and a chip carrier having external lead-out electrodes that are electrically connected to the printed circuit board. . For example, the internal lead-out electrodes of a printed circuit board can be configured by printing once on the bottom surface, so regardless of whether it is a single-layer or multi-layer board, it is possible to mount hybrid integrated circuits such as those with chip components mounted or wire bonded on both sides of the board. is wide-ranging. Furthermore, since the external lead electrodes of the chip carrier can be formed individually, an inexpensive synthetic resin molded substrate can be used, and metallized conductor electrodes with strong solder bonding strength can also be used.

またアルミナ基板など機械的強度の強い材質でチップキ
ャリヤを構成することにより、当該適用チップモジュー
ルは、信頼性の高い実装部品となる。
Furthermore, by constructing the chip carrier from a material with high mechanical strength such as an alumina substrate, the applied chip module becomes a highly reliable mounting component.

一方印刷回路基板とチップキャリヤの機械的接続は、内
部取出し電極部の半田付以外に、開口されたチップキャ
リヤの底面より、耐湿保護膜を兼ねた接着用樹脂を流し
込むことにより、印刷回路基板とチップキャリヤの接着
をより強固にすることも可能である。
On the other hand, the mechanical connection between the printed circuit board and the chip carrier is achieved by not only soldering the internal lead-out electrodes, but also by pouring an adhesive resin that also serves as a moisture-resistant protective film from the open bottom of the chip carrier. It is also possible to make the adhesion of the chip carrier stronger.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による混成集積チップモジュ
ールの断面図、第2図は印刷回路基板の実施例としての
多層印刷混成集積基板の断面図、第3図は積載されるチ
ップキャリヤの斜視図である。 1・・・・・・印刷配線回路基板、3・川・・内部取出
し電極、4・・・・・・チップキャリヤ、6・・印・溝
、6・川・・外部取出し電極、ア・・・・・・チップ部
品、8・旧・・開口部。
FIG. 1 is a cross-sectional view of a hybrid integrated chip module according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a multilayer printed hybrid integrated board as an embodiment of the printed circuit board, and FIG. 3 is a cross-sectional view of a chip carrier to be loaded. FIG. 1... Printed wiring circuit board, 3... Internal lead-out electrode, 4... Chip carrier, 6... Mark/groove, 6... External lead-out electrode, A... ...Chip parts, 8.Old...Opening.

Claims (4)

【特許請求の範囲】[Claims] (1)外部取出し電極を周壁に複数個設けたチップキャ
リヤ上に、内部取出し電極を前記外部取出し電極に対応
して底面に設けた印刷配線回路基板を配置し、かつ印刷
配線基板の内部取出し電極を前記チップキャリヤの外部
取出し電極に電気的に接続した混成集積チップモジュー
ル。
(1) A printed circuit board with internal lead-out electrodes provided on the bottom surface corresponding to the external lead-out electrodes is arranged on a chip carrier having a plurality of external lead-out electrodes on the peripheral wall, and the internal lead-out electrodes of the printed wiring board are A hybrid integrated chip module, which is electrically connected to an external lead-out electrode of the chip carrier.
(2)印刷配線基板は、単層又は多層セラミック基板の
上面又は底面に、チップ部品を配置して混成集積回路を
形成したものである特許請求の範囲第1項に記載の混成
集積チップモジュール。
(2) The hybrid integrated chip module according to claim 1, wherein the printed wiring board is a hybrid integrated circuit formed by arranging chip components on the top or bottom surface of a single-layer or multilayer ceramic substrate.
(3)チップキャリヤは、内部取出し電極に対応して周
壁に溝を複数個設け、その溝に半田上りが可能な外部取
出し用の導体電極を設けたものである特許請求の範囲第
1項に記載の混成集積チップモジュール。
(3) The chip carrier is provided with a plurality of grooves in the peripheral wall corresponding to the internal lead-out electrodes, and a conductor electrode for external lead-out to which solder can be applied is provided in the groove. The hybrid integrated chip module described.
(4)チップキャリヤは、セラミック、又は樹脂成形基
材から成り、中央部に貫通する空間を設けたものである
特許請求の範囲第1項に記載の混成集積チップモジュー
ル。
(4) The hybrid integrated chip module according to claim 1, wherein the chip carrier is made of a ceramic or resin molded base material, and has a penetrating space in the center.
JP62059358A 1987-03-13 1987-03-13 Hybrid integrated chip module Granted JPS63226053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62059358A JPS63226053A (en) 1987-03-13 1987-03-13 Hybrid integrated chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62059358A JPS63226053A (en) 1987-03-13 1987-03-13 Hybrid integrated chip module

Publications (2)

Publication Number Publication Date
JPS63226053A true JPS63226053A (en) 1988-09-20
JPH0558665B2 JPH0558665B2 (en) 1993-08-27

Family

ID=13110962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62059358A Granted JPS63226053A (en) 1987-03-13 1987-03-13 Hybrid integrated chip module

Country Status (1)

Country Link
JP (1) JPS63226053A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774500B1 (en) * 1999-07-28 2004-08-10 Seiko Epson Corporation Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774500B1 (en) * 1999-07-28 2004-08-10 Seiko Epson Corporation Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipment

Also Published As

Publication number Publication date
JPH0558665B2 (en) 1993-08-27

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