JPH0722730A - Composite electronic component - Google Patents
Composite electronic componentInfo
- Publication number
- JPH0722730A JPH0722730A JP16681793A JP16681793A JPH0722730A JP H0722730 A JPH0722730 A JP H0722730A JP 16681793 A JP16681793 A JP 16681793A JP 16681793 A JP16681793 A JP 16681793A JP H0722730 A JPH0722730 A JP H0722730A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- multilayer circuit
- circuit boards
- composite electronic
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、複合電子部品に関す
るもので、特に、多層回路基板とそこに実装される電子
部品チップとの組合わせを備える複合電子部品に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite electronic component, and more particularly to a composite electronic component including a combination of a multilayer circuit board and an electronic component chip mounted thereon.
【０００２】[0002]
【従来の技術】図４は、この発明にとって興味ある従来
の複合電子部品１を示す斜視図である。複合電子部品１
は、多層回路基板２およびその上にマウントされるＩＣ
チップのような複数個の電子部品チップ３を備える。電
子部品チップ３には、しばしばベアチップが用いられ
る。また、この複合電子部品１は、マルチチップモジュ
ールと呼ばれることもある。2. Description of the Related Art FIG. 4 is a perspective view showing a conventional composite electronic component 1 of interest to the present invention. Composite electronic component 1
Is a multilayer circuit board 2 and an IC mounted thereon.
A plurality of electronic component chips 3 such as chips are provided. A bare chip is often used as the electronic component chip 3. The composite electronic component 1 may also be called a multi-chip module.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上述し
た複合電子部品１には、次のような問題がある。However, the above-mentioned composite electronic component 1 has the following problems.
【０００４】複数個の電子部品チップ３が多層回路基板
２上に平面的に配置されるものであるので、この複合電
子部品１の占有面積が比較的大きい。Since a plurality of electronic component chips 3 are arranged in a plane on the multilayer circuit board 2, the area occupied by the composite electronic component 1 is relatively large.
【０００５】また、電子部品チップ３のそれぞれの良・
不良を個々の電子部品チップ３を多層回路基板２にマウ
ントする前に評価することは、電子部品チップ３が小さ
すぎて困難である。そのため、複合電子部品１の状態に
してから、個々の電子部品チップ３の良・不良を評価す
ることになるが、この場合、電子部品チップ３が１個で
も不良であると、複合電子部品１全体が不良となり、複
合電子部品１の歩留りが低下し、そのため、コストの上
昇を招く。In addition, each of the electronic component chips 3
It is difficult to evaluate the defects before mounting the individual electronic component chips 3 on the multilayer circuit board 2 because the electronic component chips 3 are too small. Therefore, the quality of each individual electronic component chip 3 is evaluated after the composite electronic component 1 is in the state. In this case, if even one electronic component chip 3 is defective, the composite electronic component 1 The whole becomes defective and the yield of the composite electronic component 1 is reduced, which causes an increase in cost.
【０００６】それゆえに、この発明の目的は、上述した
問題を解決し得る複合電子部品を提供しようとすること
である。Therefore, it is an object of the present invention to provide a composite electronic component which can solve the above-mentioned problems.
【０００７】[0007]
【課題を解決するための手段】この発明にかかる複合電
子部品は、積み重ねられ互いに接合された複数個の多層
回路基板からなる基板アセンブリを備える。この基板ア
センブリの側面には、外部接続用端子電極が形成され
る。また、複数個の多層回路基板の少なくとも１つに
は、キャビティが形成され、このキャビティには、少な
くとも１個の電子部品チップが内蔵される。SUMMARY OF THE INVENTION A composite electronic component according to the present invention comprises a substrate assembly comprising a plurality of multi-layer circuit boards stacked and bonded together. External connection terminal electrodes are formed on the side surfaces of the substrate assembly. A cavity is formed in at least one of the plurality of multilayer circuit boards, and at least one electronic component chip is built in the cavity.
【０００８】[0008]
【作用】この発明では、複数個の多層回路基板を備える
ので、多層回路基板が必要とする機能をこれら複数個の
多層回路基板によって分担することができ、その結果、
１個の多層回路基板を小さくすることができる。According to the present invention, since a plurality of multilayer circuit boards are provided, the functions required by the multilayer circuit boards can be shared by the plurality of multilayer circuit boards. As a result,
It is possible to reduce the size of one multilayer circuit board.
【０００９】また、個々の電子部品チップの良・不良
を、それを少なくとも多層回路基板にマウントした段階
で評価することができる。そして、評価されるべき電子
部品チップが複数個ある場合、これらは、複数個の多層
回路基板に分けてマウントすることになる。そのため、
複数個備える多層回路基板の各々ごとに電子部品チップ
の良・不良を判別することができる。Further, it is possible to evaluate the quality of each electronic component chip at least when it is mounted on a multilayer circuit board. If there are a plurality of electronic component chips to be evaluated, these will be mounted separately on a plurality of multilayer circuit boards. for that reason,
It is possible to determine whether the electronic component chip is good or bad for each of the plurality of multilayer circuit boards.
【００１０】[0010]
【発明の効果】このように、この発明によれば、上述し
た比較的小さい複数個の多層回路基板が積み重ねられて
基板アセンブリを構成するので、複合電子部品全体とし
ての占有面積を小さくすることができる。As described above, according to the present invention, since a plurality of relatively small multilayer circuit boards described above are stacked to form a board assembly, it is possible to reduce the area occupied by the composite electronic component as a whole. it can.
【００１１】また、前述したように、電子部品チップの
良・不良の評価を多層回路基板ごとに行なうことができ
るので、このような多層回路基板ごとの良・不良を判別
してから、完成品としての複合電子部品の組立てを行な
うことができる。したがって、完成品としての複合電子
部品の歩留りが向上し、その結果、コストの低減も図る
ことができる。Further, as described above, the quality of the electronic component chip can be evaluated for each multilayer circuit board. Therefore, after determining the quality of each multilayer circuit board, the finished product As a result, it is possible to assemble the composite electronic component. Therefore, the yield of the composite electronic component as a finished product is improved, and as a result, the cost can be reduced.
【００１２】[0012]
【実施例】図１は、この発明の一実施例による複合電子
部品１１の外観を示す斜視図である。図２は、図１に示
した複合電子部品１１の断面図である。1 is a perspective view showing the external appearance of a composite electronic component 11 according to an embodiment of the present invention. FIG. 2 is a sectional view of the composite electronic component 11 shown in FIG.
【００１３】複合電子部品１１は、複数個の多層回路基
板１２からなる基板アセンブリ１３を備える。基板アセ
ンブリ１３を構成するため、複数個の多層回路基板１２
は、積み重ねられ、かつ、図２に示すように、接着剤１
４を介して互い接合される。基板アセンブリ１３の側面
には、図１に示すように、複数個の外部接続用端子電極
１５が形成される。The composite electronic component 11 includes a board assembly 13 composed of a plurality of multilayer circuit boards 12. In order to form the board assembly 13, a plurality of multilayer circuit boards 12
Are stacked and, as shown in FIG. 2, adhesive 1
They are joined together via 4. As shown in FIG. 1, a plurality of external connection terminal electrodes 15 are formed on the side surface of the substrate assembly 13.
【００１４】多層回路基板１２には、図２に示すよう
に、キャビティ１６が形成される。このような多層回路
基板１２は、たとえば、次のように製造されることがで
きる。A cavity 16 is formed in the multilayer circuit board 12 as shown in FIG. Such a multilayer circuit board 12 can be manufactured as follows, for example.
【００１５】低温焼結セラミック材料からなるグリーン
シートを用意する。このグリーンシート上に、必要な配
線パターンを銅ペーストでスクリーン印刷する。次に、
グリーンシートに、パンチングにより、キャビティ１６
となるべき穴を設けるとともに、必要なビアホール接続
部を与える穴を設ける。ビアホール接続部を与える穴に
は、銅ペーストが充填される。このようにして得られた
グリーンシートを所定枚数積み重ね、プレスする。次い
で、これを、中性ないし弱還元性雰囲気中、９６０℃で
１時間焼成する。次いで、必要により、外部電極を付与
し、これに金めっき等を施す。A green sheet made of a low temperature sintered ceramic material is prepared. A required wiring pattern is screen-printed with a copper paste on this green sheet. next,
Cavity 16 by punching on the green sheet
A hole to be provided is provided, and a hole for providing a necessary via hole connection portion is provided. The holes that provide the via hole connection portions are filled with copper paste. A predetermined number of the green sheets thus obtained are stacked and pressed. Then, this is fired at 960 ° C. for 1 hour in a neutral or weakly reducing atmosphere. Then, if necessary, an external electrode is provided and gold plating or the like is applied to this.
【００１６】このようにして得られた多層回路基板１２
のキャビティ１６内に、ＩＣチップのような電子部品チ
ップ１７を配置し、ダイボンディングにより固定すると
ともに、ワイヤボンディングにより電気的接続を達成す
る。図２において、ワイヤボンディングにより形成され
たボンディングワイヤ１８が図示されている。なお、上
述したダイボンディングは、電気的接続を兼ねるように
してもよい。The multilayer circuit board 12 thus obtained
An electronic component chip 17 such as an IC chip is placed in the cavity 16 and fixed by die bonding, and electrical connection is achieved by wire bonding. In FIG. 2, the bonding wire 18 formed by wire bonding is shown. The die bonding described above may also serve as electrical connection.
【００１７】電子部品チップ１７をキャビティ１６に内
蔵した後、キャビティ１６は、蓋１９により封止され
る。蓋１９は、金属、樹脂またはセラミックのような任
意の材料から構成される。蓋１９が金属から構成される
とき、多層回路基板１２の蓋１９に接する部分には、予
め金属膜が形成され、半田を蓋１９と多層回路基板１２
との隙間に埋めることにより、蓋１９が多層回路基板１
２に接合される。また、蓋１９が樹脂またはセラミック
からなる場合、熱硬化性の接着剤により、蓋１９と多層
回路基板１２とが接合される。なお、キャビティ１６
は、樹脂で充填されてもよい。After the electronic component chip 17 is built in the cavity 16, the cavity 16 is sealed by a lid 19. The lid 19 is made of any material such as metal, resin or ceramic. When the lid 19 is made of metal, a metal film is formed in advance on the portion of the multilayer circuit board 12 that is in contact with the lid 19, and solder is applied to the lid 19 and the multilayer circuit board 12.
By filling in the gap between the lid 19 and the multilayer circuit board 1
It is joined to 2. Further, when the lid 19 is made of resin or ceramic, the lid 19 and the multilayer circuit board 12 are joined by a thermosetting adhesive. The cavity 16
May be filled with resin.
【００１８】上述した段階で、個々の多層回路基板１２
ごとに、この多層回路基板１２に設けられた電極を介し
て、内蔵された電子部品チップ１７の特性が評価され、
その良・不良が判別される。At the above-mentioned stage, the individual multilayer circuit boards 12 are
Each time, the characteristics of the built-in electronic component chip 17 are evaluated via the electrodes provided on the multilayer circuit board 12,
The good or bad is discriminated.
【００１９】その後、複数個の多層回路基板１２は、基
板アセンブリ１３を得るべく、積み重ねられ、接着剤１
４により互いに接合される。このとき、複数個の多層回
路基板１２に内蔵される電子部品チップ１７の種類は、
通常、互い異なっている。Thereafter, the plurality of multilayer circuit boards 12 are stacked to obtain the board assembly 13, and the adhesive 1
4 are joined together. At this time, the types of the electronic component chips 17 built in the plurality of multilayer circuit boards 12 are
Usually different from each other.
【００２０】上述した基板アセンブリ１３の側面には、
スパッタリング等の方法により、外部接続用端子電極１
５が形成される。この外部接続用端子電極１５は、個々
の多層回路基板１２に設けられた電極を外部に引出す機
能を果たすとともに、複数個の多層回路基板１２相互間
での電気的接続の機能も果たす。なお、図１では、外部
接続用端子電極１５の代表的なもののみが図示されてい
る。On the side surface of the substrate assembly 13 described above,
External connection terminal electrode 1 by a method such as sputtering
5 is formed. The external connection terminal electrode 15 has a function of drawing out the electrodes provided on each of the multilayer circuit boards 12 to the outside, and also has a function of electrical connection between the plurality of multilayer circuit boards 12. Note that, in FIG. 1, only typical external connection terminal electrodes 15 are shown.
【００２１】この発明の他の実施例として、図３に示す
ように、複合電子部品１１を、絶縁性材料からなる台座
２０上に取付けてもよい。台座２０の周縁部には、複数
個のリード端子２１が設けられている。また、これらリ
ード端子２１と関連の外部接続用端子電極１５とを電気
的に接続するため、台座２０の主面上には、複数個の配
線パターン２２が形成される。As another embodiment of the present invention, as shown in FIG. 3, the composite electronic component 11 may be mounted on a pedestal 20 made of an insulating material. A plurality of lead terminals 21 are provided on the peripheral portion of the pedestal 20. Further, a plurality of wiring patterns 22 are formed on the main surface of the pedestal 20 in order to electrically connect the lead terminals 21 and the related external connection terminal electrodes 15.
【００２２】図１に示した複合電子部品１１の状態で
も、そのまま、適宜の回路基板上に半田付け等により実
装することができるが、図３に示すように、台座２０を
複合電子部品１１に取付ければ、その実装信頼性をより
向上させることができる。Even in the state of the composite electronic component 11 shown in FIG. 1, it can be mounted as it is on a suitable circuit board by soldering or the like. However, as shown in FIG. If attached, its mounting reliability can be further improved.
【００２３】以上、この発明を図示した実施例に関連し
て説明したが、この発明の範囲内において、以下のよう
ないくつかの変形例が可能である。Although the present invention has been described with reference to the illustrated embodiments, the following modifications are possible within the scope of the present invention.
【００２４】たとえば、図２に示すように、多層回路基
板１２の各々のキャビティ１６のすべてが蓋１９によっ
て封止されたが、多層回路基板１２のうち、他の多層回
路基板１２の下に位置するものについては、上の多層回
路基板１２によってキャビティ１６を封止することがで
きるので、蓋１９がなくてもよい。For example, as shown in FIG. 2, all the cavities 16 of each of the multilayer circuit boards 12 are sealed by a lid 19, but the multilayer circuit board 12 is positioned below the other multilayer circuit boards 12. The above-mentioned multi-layered circuit board 12 can seal the cavity 16 so that the lid 19 is not necessary.
【００２５】また、この発明にかかる複合電子部品に備
える多層回路基板は、そのすべてがキャビティを備えて
いなくてもよい。キャビティを備えない、すなわち電子
部品チップを内蔵しない多層回路基板が、電子部品チッ
プを内蔵する多層回路基板と混ざった状態で積み重ねら
れてもよい。Further, the multilayer circuit board provided in the composite electronic component according to the present invention does not have to have all the cavities. A multilayer circuit board that does not include a cavity, that is, does not contain an electronic component chip, may be stacked in a state of being mixed with a multilayer circuit board that has an electronic component chip.
【００２６】また、多層回路基板に設けられるキャビテ
ィには、２個以上の電子部品チップが内蔵されてもよ
い。Further, two or more electronic component chips may be built in the cavity provided in the multilayer circuit board.
【００２７】また、この発明にかかる複合電子部品に備
える基板アセンブリを構成する多層回路基板の数は任意
である。The number of multilayer circuit boards constituting the board assembly provided in the composite electronic component according to the present invention is arbitrary.
【図１】この発明の一実施例による複合電子部品１１の
外観を示す斜視図である。FIG. 1 is a perspective view showing an external appearance of a composite electronic component 11 according to an embodiment of the present invention.
【図２】図１に示した複合電子部品１１の断面図であ
る。2 is a sectional view of the composite electronic component 11 shown in FIG.
【図３】この発明の他の実施例による複合電子部品１１
の外観を示す斜視図である。FIG. 3 is a composite electronic component 11 according to another embodiment of the present invention.
3 is a perspective view showing the external appearance of FIG.
【図４】この発明にとって興味ある従来の複合電子部品
１を示す斜視図である。FIG. 4 is a perspective view showing a conventional composite electronic component 1 which is of interest to the present invention.
１１ 複合電子部品 １２ 多層回路基板 １３ 基板アセンブリ １４ 接着剤 １５ 外部接続用端子電極 １６ キャビティ １７ 電子部品チップ 11 Composite Electronic Component 12 Multilayer Circuit Board 13 Board Assembly 14 Adhesive 15 External Connection Terminal Electrode 16 Cavity 17 Electronic Component Chip
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 Ｈ０５Ｋ 3/46 Ｑ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 25/18 H05K 3/46 Q 6921-4E
Claims (1)
多層回路基板からなる基板アセンブリを備え、 前記基板アセンブリの側面には、外部接続用端子電極が
形成され、 前記複数個の多層回路基板の少なくとも１つには、キャ
ビティが形成され、 前記キャビティには、少なくとも１個の電子部品チップ
が内蔵されている、 複合電子部品。1. A substrate assembly comprising a plurality of multilayer circuit boards stacked and bonded to each other, wherein external connection terminal electrodes are formed on side surfaces of the substrate assembly, and at least one of the plurality of multilayer circuit boards. One is formed with a cavity, and at least one electronic component chip is embedded in the cavity, A composite electronic component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16681793A JPH0722730A (en) | 1993-07-06 | 1993-07-06 | Composite electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16681793A JPH0722730A (en) | 1993-07-06 | 1993-07-06 | Composite electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0722730A true JPH0722730A (en) | 1995-01-24 |
Family
ID=15838219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16681793A Pending JPH0722730A (en) | 1993-07-06 | 1993-07-06 | Composite electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722730A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000025558A1 (en) * | 1998-10-26 | 2000-05-04 | Telefonaktiebolaget Lm Ericsson | A circuit board and a method for manufacturing the same |
| JP2009289790A (en) * | 2008-05-27 | 2009-12-10 | Japan Radio Co Ltd | Printed wiring board with built-in component and its manufacturing method |
| CN102299081A (en) * | 2011-08-30 | 2011-12-28 | 深南电路有限公司 | Method for manufacturing packaging substrate and packaging substrate |
| JP2014526795A (en) * | 2011-09-07 | 2014-10-06 | コミサリア ア レネルジ アトミク エ オウ エネルジ アルタナティヴ | Printed circuit board, magnetic field sensor and current sensor |
-
1993
- 1993-07-06 JP JP16681793A patent/JPH0722730A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000025558A1 (en) * | 1998-10-26 | 2000-05-04 | Telefonaktiebolaget Lm Ericsson | A circuit board and a method for manufacturing the same |
| US6449168B1 (en) | 1998-10-26 | 2002-09-10 | Telefonaktiebolaget Lm Ericcson (Publ) | Circuit board and a method for manufacturing the same |
| JP2009289790A (en) * | 2008-05-27 | 2009-12-10 | Japan Radio Co Ltd | Printed wiring board with built-in component and its manufacturing method |
| CN102299081A (en) * | 2011-08-30 | 2011-12-28 | 深南电路有限公司 | Method for manufacturing packaging substrate and packaging substrate |
| JP2014526795A (en) * | 2011-09-07 | 2014-10-06 | コミサリア ア レネルジ アトミク エ オウ エネルジ アルタナティヴ | Printed circuit board, magnetic field sensor and current sensor |
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| Date | Code | Title | Description |
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| A02 | Decision of refusal |
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