JPH0645763A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH0645763A
JPH0645763A JP4195771A JP19577192A JPH0645763A JP H0645763 A JPH0645763 A JP H0645763A JP 4195771 A JP4195771 A JP 4195771A JP 19577192 A JP19577192 A JP 19577192A JP H0645763 A JPH0645763 A JP H0645763A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
board
hole
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4195771A
Other languages
Japanese (ja)
Inventor
Satoshi Goto
智 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4195771A priority Critical patent/JPH0645763A/en
Publication of JPH0645763A publication Critical patent/JPH0645763A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a printed wiring board mounted with electronic parts high in mounting density by a method wherein semiconductor chips are built in holes provided inside the board. CONSTITUTION:A printed wiring board is composed of two outer boards 2 and an inner board 1 sandwiched in between the two outer boards 2 and equipped with circuit wiring layers 3 each provided onto the surface of the wiring board and between the boards. A hole 7 is provided to the inner board 1 at a prescribed position, and a pad and a wiring used for mounting an IC chip 6 are formed on the circuit wiring layer 3 exposed at the hole 7. The IC chip 6 is mounted on the circuit wiring layer 3 through the intermediary of bumps 5. Electronic parts 4 are formed on the surfaces of the printed wiring board at prescribed positions. As mentioned above, an IC is mounted inside the hole 7 provided to the inner board 1, so that elements mounted on a printed wiring board can be enhanced in number per unit area.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は印刷配線板に関し、特に
高密度実装が可能な印刷配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to a printed wiring board capable of high-density mounting.

【0002】[0002]

【従来の技術】従来の印刷配線板は、図3に示すよう
に、ガラスエポキシやポリイミド材等の絶縁材からなる
内層基板1と外層基板2及び主に銅材からなる回路配線
層3等により構成されている。外層基板2の外側即ち印
刷配線板の表面に形成された回路配線層3には電子部品
4等を実装する為のパッドや各電子部品4間を電気的に
接続する為の回路が形成されている。又、内層基板1と
外層基板2との間に形成された回路配線層3には印刷配
線板の表面に形成しきれない回路が形成されている。
2. Description of the Related Art As shown in FIG. 3, a conventional printed wiring board includes an inner layer substrate 1 and an outer layer substrate 2 made of an insulating material such as glass epoxy or a polyimide material, and a circuit wiring layer 3 mainly made of copper material. It is configured. On the circuit wiring layer 3 formed on the outer side of the outer layer substrate 2, that is, on the surface of the printed wiring board, pads for mounting electronic components 4 and circuits for electrically connecting the electronic components 4 are formed. There is. Further, the circuit wiring layer 3 formed between the inner layer substrate 1 and the outer layer substrate 2 is provided with circuits that cannot be formed on the surface of the printed wiring board.

【発明が解決しようとする課題】この従来の印刷配線板
では、表面にのみ電子部品を実装している為、実装密度
を上げるためには電子部品の小型化や多ピン狭ピッチ部
品の実装技術の向上によらなければならず、現在のとこ
ろ飛躍的に実装密度を上げることが困難であるという問
題点があった。
In this conventional printed wiring board, the electronic components are mounted only on the surface. Therefore, in order to increase the mounting density, the electronic components can be downsized and the mounting technique for the multi-pin narrow-pitch components. There is a problem that it is difficult to dramatically increase the packaging density at present.

【0003】本発明の目的は、電子部品の実装密度の高
い印刷配線板を提供することにある。
An object of the present invention is to provide a printed wiring board having a high mounting density of electronic components.

【0004】[0004]

【課題を解決するための手段】本発明は、複数の電子部
品を表面と裏面とのうちの少くともいずれか一方の面に
実装する印刷配線板において、内部に空孔を設け該空孔
に半導体チップを内蔵する。
DISCLOSURE OF THE INVENTION The present invention provides a printed wiring board on which a plurality of electronic components are mounted on at least one of the front surface and the back surface, and a hole is provided inside the printed wiring board. Built-in semiconductor chip.

【0005】[0005]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0006】図1は本発明の第1の実施例の断面図であ
る。
FIG. 1 is a sectional view of a first embodiment of the present invention.

【0007】第1の実施例は、図1に示すように、内層
基板1と内層基板1を挟む2枚の外層基板2とから成
り、表面及び各層間に回路配線層3を有している。内層
基板1には所定の位置に空孔7が設けられ、図示してい
ないが、空孔7部に露出した回路配線層3にはICチッ
プ6を実装する為のパッド及び配線が形成されている。
ICチップ6はバンプ5を介して回路配線層3に実装さ
れている。又、印刷配線板の表面にも所定の位置に電子
部品4が実装されている。
As shown in FIG. 1, the first embodiment comprises an inner layer substrate 1 and two outer layer substrates 2 sandwiching the inner layer substrate 1, and has a circuit wiring layer 3 on the surface and between layers. . Holes 7 are provided at predetermined positions in the inner layer substrate 1, and although not shown, pads and wirings for mounting the IC chip 6 are formed on the circuit wiring layer 3 exposed in the holes 7 portion. There is.
The IC chip 6 is mounted on the circuit wiring layer 3 via the bumps 5. The electronic component 4 is also mounted on the surface of the printed wiring board at a predetermined position.

【0008】なお、内層基板1内のICチップ6はバン
プ5による実装の他、ワイヤボンディングによる電気的
接続又は、TCP(テープキャリアパッケージ)による
実装も可能である。
The IC chip 6 in the inner layer substrate 1 can be mounted by bumps 5, electrical connection by wire bonding or mounting by TCP (tape carrier package).

【0009】このように、内層基板1の空孔7にICチ
ップ6を実装することにより、従来の印刷配線板に比べ
て単位面積当りの素子実装数が上がるという効果があ
る。
As described above, by mounting the IC chip 6 in the hole 7 of the inner layer substrate 1, the number of elements mounted per unit area is increased as compared with the conventional printed wiring board.

【0010】図2は本発明の第2の実施例の断面図であ
る。
FIG. 2 is a sectional view of the second embodiment of the present invention.

【0011】第2の実施例の構成要素は、図2に示すよ
うに、第1の実施例とほぼ同様であるが、空孔を外層基
板2に設けてICチップ6を実装し、その空孔内を封止
材8にて封止を行った例である。
The constituent elements of the second embodiment are almost the same as those of the first embodiment, as shown in FIG. 2, except that holes are provided in the outer layer substrate 2 to mount the IC chip 6, and In this example, the inside of the hole is sealed with the sealing material 8.

【0012】第1の実施例では印刷配線板の製造工程中
においてICチップ6を実装する必要があるが、第2の
実施例の印刷配線板は空孔を表面に設けてある為、印刷
配線板の製造完了後に他の電子部品4と同様にICチッ
プ6を実装できるという利点がある。
In the first embodiment, it is necessary to mount the IC chip 6 during the manufacturing process of the printed wiring board, but in the printed wiring board of the second embodiment, holes are provided on the surface, so that the printed wiring board is provided. There is an advantage that the IC chip 6 can be mounted like other electronic components 4 after the manufacture of the plate is completed.

【0013】[0013]

【発明の効果】以上説明したように本発明の印刷配線板
は、内部にICチップを内蔵することにより、実装密度
を高めることができるという効果を有する。
As described above, the printed wiring board of the present invention has the effect that the mounting density can be increased by incorporating the IC chip therein.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

【図2】本発明の第2の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.

【図3】従来の印刷配線板の一例の断面図である。FIG. 3 is a cross-sectional view of an example of a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

1 内層基板 2 外層基板 3 回路配線層 4 電子部品 5 バンプ 6 ICチップ 7 空孔 8 封止材 1 Inner Layer Substrate 2 Outer Layer Substrate 3 Circuit Wiring Layer 4 Electronic Component 5 Bump 6 IC Chip 7 Hole 8 Sealant

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数の電子部品を表面と裏面とのうちの
少くともいずれか一方の面に実装する印刷配線板におい
て、内部に空孔を設け該空孔に半導体チップを内蔵する
ことを特徴とする印刷配線板。
1. A printed wiring board having a plurality of electronic components mounted on at least one of a front surface and a back surface, wherein a hole is provided inside and a semiconductor chip is built in the hole. And printed wiring board.
JP4195771A 1992-07-23 1992-07-23 Printed wiring board Withdrawn JPH0645763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4195771A JPH0645763A (en) 1992-07-23 1992-07-23 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4195771A JPH0645763A (en) 1992-07-23 1992-07-23 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH0645763A true JPH0645763A (en) 1994-02-18

Family

ID=16346694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4195771A Withdrawn JPH0645763A (en) 1992-07-23 1992-07-23 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH0645763A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321439A (en) * 1996-05-31 1997-12-12 Nec Corp Lamination circuit board
JP2004007006A (en) * 2003-09-16 2004-01-08 Kyocera Corp Multilayer wiring board
US7192801B2 (en) 2002-06-26 2007-03-20 Sony Corporation Printed circuit board and fabrication method thereof
JP2009147249A (en) * 2007-12-18 2009-07-02 Minami Kk Method of mounting electronic component on printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321439A (en) * 1996-05-31 1997-12-12 Nec Corp Lamination circuit board
US7192801B2 (en) 2002-06-26 2007-03-20 Sony Corporation Printed circuit board and fabrication method thereof
KR101016531B1 (en) * 2002-06-26 2011-02-24 소니 주식회사 Printed circuit board and fabrication method thereof
JP2004007006A (en) * 2003-09-16 2004-01-08 Kyocera Corp Multilayer wiring board
JP2009147249A (en) * 2007-12-18 2009-07-02 Minami Kk Method of mounting electronic component on printed wiring board

Similar Documents

Publication Publication Date Title
US6396136B2 (en) Ball grid package with multiple power/ground planes
US5784264A (en) MCM (Multi Chip Module) carrier with external connection teminals BGA (Ball Grid Array) type matrix array form
KR950012658B1 (en) Semiconductor chip mounting method and substrate structure
US6849945B2 (en) Multi-layered semiconductor device and method for producing the same
US20010002727A1 (en) Semiconductor device and module of the same
JPH11297889A (en) Semiconductor package, mounting board and mounting method by use of them
KR20010072583A (en) Laminated integrated circuit package
JPH09283695A (en) Semiconductor mounting structure
US6507118B1 (en) Multi-metal layer circuit
JP3063846B2 (en) Semiconductor device
US20020063331A1 (en) Film carrier semiconductor device
JPH07142283A (en) Capacitor and packaging structure using the same
JPH0645763A (en) Printed wiring board
JPH0917917A (en) Wiring board and semiconductor device
JPH05211256A (en) Semiconductor device
JP3024596B2 (en) BGA type semiconductor device using film carrier tape
JPH10107091A (en) Mounting structure of electronic component and manufacture thereof
KR20030046788A (en) Semiconductor Package and Manufacture Method The Same
JP2841825B2 (en) Hybrid integrated circuit
KR20020028473A (en) Stack package
JP3033541B2 (en) TAB tape, semiconductor device, and method of manufacturing semiconductor device
JP3149836B2 (en) Semiconductor device
JPH0629422A (en) Hybrid integrated circuit device
JP2836597B2 (en) Film carrier tape and semiconductor device using the same
JP2000332143A (en) Semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991005