JPH1167963A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1167963A JPH1167963A JP9229031A JP22903197A JPH1167963A JP H1167963 A JPH1167963 A JP H1167963A JP 9229031 A JP9229031 A JP 9229031A JP 22903197 A JP22903197 A JP 22903197A JP H1167963 A JPH1167963 A JP H1167963A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- circuit board
- dimensional circuit
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、樹脂成形によって
形成される立体回路基板（ＭＩＤ基板と称される）に半
導体を搭載し、この半導体と立体回路基板における回路
パターンとを配線接続して形成される半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional circuit board (referred to as an MID board) formed by resin molding, on which a semiconductor is mounted. Semiconductor device to be used.
【０００２】[0002]
【従来の技術】従来の半導体装置としては、特開平６−
１４０７３８号公報、特開平３−２９５２６６号公報ま
たは特開平６−３４２８７４号公報などに示されるよう
なものがある。2. Description of the Related Art A conventional semiconductor device is disclosed in
Japanese Patent Application Laid-Open Nos. 140738, 3-295266 and 6-342874.
【０００３】これらの半導体装置は、いずれも、回路基
板の片面に半導体を搭載し、この回路基板の半導体を搭
載した面における回路パターンに、ワイヤーボンディン
グなどによって配線接続して形成されている。[0003] All of these semiconductor devices are formed by mounting a semiconductor on one surface of a circuit board, and by wiring connection to a circuit pattern on the surface of the circuit board on which the semiconductor is mounted by wire bonding or the like.
【０００４】たとえば、特開平３−２９５２６６号公報
には、図21に示すような半導体装置が示されている。こ
の半導体装置は、平板状の回路基板40の片面に凹部２が
形成され、この凹部２に半導体10が搭載されている。そ
して、半導体10の周縁部にあるパッドから凹部２外側の
回路パターン３に配線接続されているものである。そし
て、このように形成された一単位の半導体装置を積層し
て、多層構成の半導体装置を形成しているものであり、
集積度の高い半導体装置になっている。For example, Japanese Patent Application Laid-Open No. 3-295266 discloses a semiconductor device as shown in FIG. In this semiconductor device, a recess 2 is formed on one surface of a flat circuit board 40, and a semiconductor 10 is mounted in the recess 2. The wiring is connected to the circuit pattern 3 outside the concave portion 2 from the pad on the peripheral portion of the semiconductor 10. Then, one unit of the semiconductor device thus formed is stacked to form a semiconductor device having a multilayer structure,
It has become a highly integrated semiconductor device.
【０００５】また、特開平６−３４２８７４号公報に
は、図22に示すような半導体装置が示されている。この
半導体装置では、スルーホールを半断してアウターリー
ド41を形成している。このようなアウターリード41によ
って、この半導体装置の上にさらに半導体装置を積層す
るときには、上下の半導体装置の電気的接続が確実かつ
容易に行われる結果、多層構成の半導体装置を容易に形
成できるものになっている。Japanese Patent Laid-Open Publication No. Hei 6-342874 discloses a semiconductor device as shown in FIG. In this semiconductor device, the outer lead 41 is formed by cutting the through hole in half. When the semiconductor device is further stacked on the semiconductor device by such outer leads 41, the electrical connection between the upper and lower semiconductor devices can be made reliably and easily, so that a semiconductor device having a multilayer structure can be easily formed. It has become.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記の
従来例にあっては、以下のような不都合が起こる場合が
ある。However, in the above conventional example, the following inconveniences may occur.
【０００７】すなわち、中央部に配線のパッドがあるセ
ンターパッド型の半導体を搭載しようとすると、配線を
半導体の中央部から外側に長く引き出さねばならないの
である。したがって、配線作業を行いにくく、接続信頼
性を確保するには注意深い配線作業が必要になるもので
ある。また、回路基板40を積層した高集積半導体装置と
なっているものの、場合によっては、各層の半導体装置
の配線を異ならせる必要があったり、位置ずれが発生し
やすかったり、煩雑な積層工程を取らざるを得ない場合
があったりして、実装信頼性が低いものになりやすいも
のである。In other words, if a center pad type semiconductor having a wiring pad at the center is to be mounted, the wiring must be extended outward from the center of the semiconductor for a long time. Therefore, it is difficult to perform a wiring operation, and a careful wiring operation is required to secure connection reliability. Although the semiconductor device is a highly integrated semiconductor device in which the circuit boards 40 are stacked, in some cases, the wiring of the semiconductor device in each layer needs to be different, misalignment is likely to occur, or a complicated stacking process is performed. In some cases, it is unavoidable that mounting reliability is low.
【０００８】また、スルーホールを半断してアウターリ
ード41を形成するものにあっては、切断時にスルーホー
ル部の導電層が剥がれたりしやすく、工程が複雑になる
などの問題がでてくることになる。In the case where the outer lead 41 is formed by half-cutting the through-hole, the conductive layer in the through-hole is easily peeled off at the time of cutting, which causes a problem that the process becomes complicated. Will be.
【０００９】本発明は、以上のような問題点を解決する
ためになされたものであり、その目的は、センターパッ
ド型の半導体であっても、容易に信頼性の高い実装がで
きるものであり、さらには、狭ピッチのアウターリード
を有する一単位の半導体装置を、位置ずれすることなく
精度よく多層化することができて、高信頼性で高集積度
に多層化され得るまたはされた半導体装置の提供にあ
る。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device of a center pad type which can be easily mounted with high reliability. Furthermore, a single unit semiconductor device having a narrow pitch outer lead can be accurately multilayered without displacement, and can be multilayered with high reliability and high integration. In the offer.
【００１０】[0010]
【課題を解決するための手段】上記課題を解決する請求
項１記載の発明は、少なくとも片面に凹部２を設けて、
樹脂成形による立体回路基板22を形成し、この立体回路
基板22の片面に半導体10を搭載し、この半導体10と立体
回路基板22に形成された回路パターン３とを配線接続し
て成る半導体装置において、表裏いずれか一方の面に半
導体10を固着し、立体回路基板22の表面から凹部２側の
裏面に接続孔20を貫通形成し、この接続孔20を半導体10
の配線用パッドの部分に位置させ、この配線用パッド
と、この半導体10を固着した面と反対側の面における回
路パターン３とを、接続孔20を通過させて配線接続して
成ることを特徴として構成している。According to the first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
In a semiconductor device formed by forming a three-dimensional circuit board 22 by resin molding, mounting the semiconductor 10 on one surface of the three-dimensional circuit board 22, and wiring-connecting the semiconductor 10 and the circuit pattern 3 formed on the three-dimensional circuit board 22 The semiconductor 10 is fixed to one of the front and back surfaces, and a connection hole 20 is formed through the surface of the three-dimensional circuit board 22 to the back surface on the concave portion 2 side.
The wiring pad and the circuit pattern 3 on the surface opposite to the surface to which the semiconductor 10 is fixed are connected by wiring through the connection hole 20. It is constituted as.
【００１１】このような半導体装置によれば、半導体10
を固着した面と反対側の面における回路パターン３と
を、半導体10の表面上にワイヤーボンディングなどの配
線を通過させるのではなく、接続孔20を通過させて、最
短距離で配線接続することができる。つまり、半導体10
の中央部に配線用パッドがある場合にあっても、この配
線用パッドと、回路パターン３とを、接続孔20を通過さ
せることによって、最短距離で接続することが可能にな
っている。According to such a semiconductor device, the semiconductor 10
It is possible to connect the circuit pattern 3 on the surface opposite to the surface where the is fixed to the semiconductor pattern 10 with the shortest distance by passing through the connection hole 20 instead of passing through wiring such as wire bonding on the surface of the semiconductor 10. it can. In other words, semiconductor 10
Even if there is a wiring pad at the center of the wiring pattern, the wiring pad and the circuit pattern 3 can be connected in the shortest distance by passing through the connection hole 20.
【００１２】請求項２記載の発明は、請求項１記載の発
明において、半導体10を凹部２側に設けて成ることを特
徴として構成している。According to a second aspect of the present invention, in the first aspect, the semiconductor 10 is provided on the concave portion 2 side.
【００１３】このような半導体装置によれば、半導体10
を凹部２内に保護することができる。According to such a semiconductor device, the semiconductor 10
Can be protected in the recess 2.
【００１４】請求項３記載の発明は、請求項１または２
のいずれかに記載の発明において、少なくとも接続孔20
を含んで、この接続孔20から半導体10にかけての部分を
樹脂封止して成ることを特徴として構成している。According to a third aspect of the present invention, there is provided the first or second aspect.
In the invention described in any one of the above, at least the connection hole 20
And a portion from the connection hole 20 to the semiconductor 10 is sealed with a resin.
【００１５】このような半導体装置によれば、樹脂封止
によって配線接続部を保護することができる。According to such a semiconductor device, the wiring connection portion can be protected by resin sealing.
【００１６】請求項４記載の発明は、請求項３記載の発
明において、樹脂封止枠23を立体回路基板22に一体に設
けて成ることを特徴として構成している。A fourth aspect of the present invention is characterized in that, in the third aspect of the invention, the resin sealing frame 23 is provided integrally with the three-dimensional circuit board 22.
【００１７】このような半導体装置によれば、樹脂封止
枠23によって、一定深さに樹脂封止を容易に行うことが
できる。According to such a semiconductor device, resin sealing can be easily performed to a certain depth by the resin sealing frame 23.
【００１８】請求項５記載の発明は、請求項１記載の発
明において、半導体10と立体回路基板22との固着による
密着部およびこの密着部周囲における立体回路基板22表
面に金属膜27を形成して成ることを特徴として構成して
いる。According to a fifth aspect of the present invention, in the first aspect of the present invention, a metal film 27 is formed on the surface of the three-dimensional circuit board 22 in the vicinity of the tight contact between the semiconductor 10 and the three-dimensional circuit board 22 and around the close contact. It is characterized by comprising.
【００１９】このような半導体装置によれば、金属膜27
によって、半導体10が発生する熱を放出させることがで
き、また、同金属膜27によって、電磁波をシールドする
ことができる。According to such a semiconductor device, the metal film 27
Accordingly, heat generated by the semiconductor 10 can be released, and the metal film 27 can shield electromagnetic waves.
【００２０】請求項６記載の発明は、請求項１記載の発
明において、半導体10をインサート形成して立体回路基
板22を形成することによって、半導体10を前記立体回路
基板22に搭載してなることを特徴として構成している。According to a sixth aspect of the present invention, in the first aspect of the present invention, the semiconductor 10 is mounted on the three-dimensional circuit board 22 by forming the three-dimensional circuit board 22 by insert-forming the semiconductor 10. The feature is constituted.
【００２１】このような半導体装置によれば、立体回路
基板22に後から半導体10を搭載する必要がなく、工程が
簡略なものになっている。According to such a semiconductor device, it is not necessary to mount the semiconductor 10 on the three-dimensional circuit board 22 later, and the process is simplified.
【００２２】請求項７記載の発明は、請求項１ないし６
のいずれかに記載の発明において、平板部の周囲に脚壁
24を垂設し、この脚壁24に囲まれた空間を凹部２とする
形状に立体回路基板22を形成し、この立体回路基板22を
積層して成ることを特徴として構成している。The invention according to claim 7 is the invention according to claims 1 to 6
In the invention described in any one of the above, the leg wall is provided around the flat plate portion.
The three-dimensional circuit board 22 is formed in a shape in which the space surrounded by the leg wall 24 is formed as the concave part 2, and the three-dimensional circuit board 22 is laminated.
【００２３】このような半導体装置によれば、封止樹脂
11または半導体10の部分を凹部２内に納めた状態で、立
体回路基板22を積層することができる。According to such a semiconductor device, the sealing resin
The three-dimensional circuit board 22 can be stacked with the portion of the semiconductor 11 or the semiconductor 10 placed in the recess 2.
【００２４】請求項８記載の発明は、請求項７記載の発
明において、立体回路基板22を積層する際に互いに嵌合
する嵌合凸部31および嵌合凹部32を、脚壁24の先端面と
平板周縁部とにそれぞれ設けて成ることを特徴として構
成している。According to an eighth aspect of the present invention, in the invention of the seventh aspect, when the three-dimensional circuit boards 22 are stacked, the fitting projections 31 and the fitting recesses 32 fitted to each other are formed on the front end surface of the leg wall 24. And at the periphery of the flat plate.
【００２５】このような半導体装置によれば、嵌合凸部
31と嵌合凹部32とを互いに嵌合させることによって、正
確な位置にずれることなく立体回路基板22が積層され
る。According to such a semiconductor device, the fitting convex portion
By fitting the fitting portions 31 and the fitting recesses 32 with each other, the three-dimensional circuit board 22 is stacked without being shifted to an accurate position.
【００２６】請求項９記載の発明は、請求項８記載の発
明において、嵌合凸部31および嵌合凹部32を、立体回路
基板22における回路パターン３のアウターリード部に形
成して成ることを特徴として構成している。According to a ninth aspect of the present invention, in the invention of the eighth aspect, the fitting projection 31 and the fitting recess 32 are formed on the outer lead portion of the circuit pattern 3 on the three-dimensional circuit board 22. It is configured as a feature.
【００２７】このような半導体装置によれば、嵌合凸部
31および嵌合凹部32の嵌合によって電気的な接続が確実
になされる。According to such a semiconductor device, the fitting convex portion
By the fitting of the fitting 31 and the fitting recess 32, the electrical connection is reliably made.
【００２８】請求項10記載の発明は、請求項７記載の発
明において、立体回路基板22の積層時に互いに重なる面
における回路パターン３のアウターリード部に接続凹部
25を設け、これらの接続凹部25の位置を積層した状態で
重ね合わされたそれぞれの面で一致させるとともに、こ
れらの接続凹部25内に導電性の接続材料26を充填して積
層して成ることを特徴として構成している。According to a tenth aspect of the present invention, in the invention of the seventh aspect, the connection recess is formed in the outer lead portion of the circuit pattern 3 on the surface overlapping each other when the three-dimensional circuit boards 22 are stacked.
25, the positions of these connection recesses 25 are made to coincide with each other on the superposed surfaces in a stacked state, and the connection recesses 25 are filled with a conductive connection material 26 and laminated. It is configured as a feature.
【００２９】このような半導体装置によれば、接続材料
26によって上下の立体回路基板22を、強固に接合すると
ともに、電気的にも接続することができる。According to such a semiconductor device, the connection material
26 allows the upper and lower three-dimensional circuit boards 22 to be firmly joined and also electrically connected.
【００３０】請求項11記載の発明は、請求項７記載の発
明において、立体回路基板22を積層する際に互いに嵌合
する嵌合凸部31および嵌合凹部32を、脚壁24外面の上部
と下部とにそれぞれ設けて成ることを特徴として構成し
ている。According to an eleventh aspect of the present invention, in the invention of the seventh aspect, when the three-dimensional circuit boards 22 are stacked, the fitting projections 31 and the fitting recesses 32 fitted to each other are formed on the outer surface of the leg wall 24. And a lower portion.
【００３１】このような半導体装置によれば、嵌合凸部
31と嵌合凹部32とを互いに嵌合させることによって、正
確な位置に、ずれることなく立体回路基板22が積層され
る。According to such a semiconductor device, the fitting convex portion
The three-dimensional circuit board 22 is stacked at an accurate position without displacement by fitting the fitting 31 and the fitting recess 32 to each other.
【００３２】[0032]
【発明の実施の形態】本発明の実施の形態を以下に添付
図を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００３３】図１ないし図11を参照して、この実施の形
態の一つの半導体装置を説明する。これらの図は異なる
一つの半導体装置をそれぞれ示す断面図である。One semiconductor device according to this embodiment will be described with reference to FIGS. These figures are cross-sectional views each showing one different semiconductor device.
【００３４】これらの半導体装置は、少なくとも片面に
凹部２を設けて、樹脂成形による立体回路基板22を形成
し、この立体回路基板22の片面に半導体10を搭載し、こ
の半導体10と立体回路基板22に形成された回路パターン
３とを配線接続して成るものである。そして、いずれの
半導体装置においても、表裏いずれか一方の面に半導体
10を固着し、立体回路基板22の表面から凹部２側の裏面
に接続孔20を貫通形成し、この接続孔20を半導体10の配
線用パッドの部分に位置させ、この配線用パッドと、こ
の半導体10を固着した面と反対側の面における回路パタ
ーン３とを、接続孔20を通過させて配線接続して形成さ
れている。In these semiconductor devices, a three-dimensional circuit board 22 is formed by resin molding by providing a recess 2 on at least one side, and a semiconductor 10 is mounted on one side of the three-dimensional circuit board 22. The circuit pattern is formed by wiring-connecting the circuit pattern 3 formed on the substrate 22. And, in any semiconductor device, the semiconductor
The connection hole 20 is formed through the surface of the three-dimensional circuit board 22 from the front surface of the three-dimensional circuit board 22 to the back surface on the side of the concave portion 2, and the connection hole 20 is located at the portion of the wiring pad of the semiconductor 10. The circuit pattern 3 on the surface opposite to the surface to which the semiconductor 10 is fixed is connected to the circuit pattern 3 through the connection hole 20 to form a wiring connection.
【００３５】また、立体回路基板22は、平板部の周囲に
脚壁24を垂設し、この脚壁24に囲まれた空間を凹部２と
する形状に形成されている。また、回路パターン３は
銅、ニッケル、金の三層のめっき膜となっている。この
回路パターン３は平板部の表面、脚壁22の外側面および
凹部２の内面に形成されている。The three-dimensional circuit board 22 is formed in a shape in which a leg wall 24 is vertically provided around a flat plate portion, and a space surrounded by the leg wall 24 is defined as the concave portion 2. The circuit pattern 3 is a three-layer plating film of copper, nickel and gold. The circuit pattern 3 is formed on the surface of the flat plate portion, the outer surface of the leg wall 22, and the inner surface of the recess 2.
【００３６】また、このような半導体装置は、立体回路
基板22における凹部２を下方に向けて、マザーボード１
上に回路パターン３の一部である電極をはんだ14にて接
合して取り付けられて使用される。Also, in such a semiconductor device, the concave portion 2 of the three-dimensional circuit board 22 faces downward,
An electrode, which is a part of the circuit pattern 3, is used by being joined thereto with solder 14 and attached thereto.
【００３７】以上のような半導体装置によれば、半導体
10を固着した面と反対側の面における回路パターン３と
を、半導体10の表面上にワイヤーボンディングなどの配
線を通過させるのではなく、接続孔20を通過させて、最
短距離で配線接続することができる。つまり、半導体10
の中央部に配線用パッドがある場合にあっても、この配
線用パッドと、回路パターン３とを、接続孔20を通過さ
せることによって、最短距離で接続することが可能にな
っている。したがって、半導体10の中央部に配線用パッ
ドがある場合にあっても、この配線用パッドと回路パタ
ーン３とを最短距離で接続することが可能になってい
る。このため、配線作業が容易になっているとともに、
配線接続を確実に行うことができるので、信頼性の高い
半導体装置になっている。According to the semiconductor device described above,
The circuit pattern 3 on the surface opposite to the surface where the 10 is fixed is connected to the surface of the semiconductor 10 through the connection hole 20 instead of passing through wiring such as wire bonding, and is connected in the shortest distance. Can be. In other words, semiconductor 10
Even if there is a wiring pad at the center of the wiring pattern, the wiring pad and the circuit pattern 3 can be connected in the shortest distance by passing through the connection hole 20. Therefore, even when there is a wiring pad in the center of the semiconductor 10, the wiring pad and the circuit pattern 3 can be connected with the shortest distance. This facilitates wiring work,
Since the wiring connection can be reliably performed, the semiconductor device has high reliability.
【００３８】以下、各図に基づいて説明する。図１の半
導体装置は、平板部の中央部に接続孔20が形成されてお
り、半導体10は凹部２の反対面に接着剤13によって固定
して設けられている。また、この半導体10としては、中
央部に配線用パッドがあるセンターパッド型のものが用
いられ、この配線用パッドの部分を接続孔20の部分に位
置させて、立体回路基板22に設けられている。そして、
この配線用パッドから凹部２側の平面部裏面側に形成さ
れてた回路パターン３に、金線ワイヤー12によるワイヤ
ーボンディングによって配線接続し、このような配線部
分を樹脂封止して保護している。また、接続孔20内の封
止樹脂11によって、半導体10はさらに強固に立体回路基
板22に固定され、保護されている。Hereinafter, description will be made with reference to the drawings. In the semiconductor device of FIG. 1, a connection hole 20 is formed in the center of the flat plate portion, and the semiconductor 10 is provided on the opposite surface of the recess 2 with an adhesive 13. As the semiconductor 10, a center pad type having a wiring pad in the center is used, and the wiring pad portion is provided on the connection hole 20 and provided on the three-dimensional circuit board 22. I have. And
The wiring pad is connected to the circuit pattern 3 formed on the rear surface side of the flat portion on the concave portion 2 side by wire bonding with the gold wire 12 from the wiring pad, and such a wiring portion is protected by resin sealing. . The semiconductor 10 is further firmly fixed to the three-dimensional circuit board 22 and protected by the sealing resin 11 in the connection hole 20.
【００３９】また、図２に示す半導体装置では、エッジ
部に配線用パッドがある半導体10を搭載している。した
がって、この場合は、周辺部の配線用パッドに配線接続
するために、平板部の周辺部に接続孔20が形成され、凹
部２内における接続孔20外側の配線パターン３に、ワイ
ヤーボンディングによって配線接続されている。In the semiconductor device shown in FIG. 2, a semiconductor 10 having a wiring pad at an edge portion is mounted. Therefore, in this case, a connection hole 20 is formed in the peripheral portion of the flat plate portion for wiring connection to the wiring pad in the peripheral portion, and the wiring pattern 3 outside the connection hole 20 in the concave portion 2 is wired by wire bonding. It is connected.
【００４０】また、図３および図４に示す半導体装置で
は、それぞれ図１または図２のものと異なり、半導体10
は凹部２内に設けられて保護されている。そして、平板
部の表面側における中央部または周辺部に形成されてた
回路パターン３に、金線ワイヤー12によるワイヤーボン
ディングによって配線接続されている。In the semiconductor device shown in FIGS. 3 and 4, unlike the semiconductor device shown in FIGS.
Are provided in the recess 2 and protected. The wiring is connected to the circuit pattern 3 formed in the central portion or the peripheral portion on the front surface side of the flat plate portion by wire bonding with the gold wire 12.
【００４１】また、図５の半導体装置は、樹脂封止枠23
を立体回路基板22に一体に設けており、この樹脂封止枠
23によって、一定深さに樹脂封止を容易に行うことがで
きるようになっている。より具体的には、図３に示した
半導体装置において、脚壁24を上方に延設し、この延設
された部分を樹脂封止枠23としているものである。ま
た、この半導体装置では、半導体10の部分をも樹脂封止
して、しっかりと保護するようにしている。The semiconductor device shown in FIG.
Are integrally provided on the three-dimensional circuit board 22, and this resin sealing frame is provided.
23 makes it possible to easily perform resin sealing to a certain depth. More specifically, in the semiconductor device shown in FIG. 3, the leg wall 24 is extended upward, and the extended portion is used as the resin sealing frame 23. Further, in this semiconductor device, the portion of the semiconductor 10 is also resin-sealed so as to be protected firmly.
【００４２】また、図６の半導体装置は、図３に示した
半導体装置において、半導体10の部分をも樹脂封止し
て、しっかりと保護するようにしている。In the semiconductor device shown in FIG. 6, in the semiconductor device shown in FIG. 3, a portion of the semiconductor 10 is also sealed with a resin so as to be firmly protected.
【００４３】また、図７の半導体装置は、図５に示した
半導体装置において、樹脂封止枠23を接続孔20の周囲に
近接する位置に設け、封止樹脂11の使用量を節約するよ
うにしている。さらに、この場合、半導体10側の樹脂封
止を省略している。The semiconductor device of FIG. 7 is different from the semiconductor device of FIG. 5 in that the resin sealing frame 23 is provided at a position close to the periphery of the connection hole 20 so that the amount of the sealing resin 11 used can be reduced. I have to. Further, in this case, resin sealing on the semiconductor 10 side is omitted.
【００４４】また、図８の半導体装置は、図１に示した
半導体装置において、凹部２の形状を二段階に落ち込む
ような形状とするように脚壁24を形成している。つま
り、脚壁24の内側に樹脂封止枠11が一体に形成されてい
るのである。そして、落ち込んだ部分にのみ封止樹脂11
を供給するようにして、封止樹脂11の使用量を節約する
ようにしている。In the semiconductor device shown in FIG. 8, the leg wall 24 is formed so that the shape of the concave portion 2 in the semiconductor device shown in FIG. That is, the resin sealing frame 11 is integrally formed inside the leg wall 24. Then, the sealing resin 11 is applied only to the depressed portion.
Is supplied to save the amount of the sealing resin 11 used.
【００４５】また、図９の半導体装置は、上記図８の半
導体装置おいて、樹脂封止枠11を半導体10の外周部に近
接する位置にも設けており、半導体10を保護するととも
に、封止樹脂11の使用量も節約するようにしている。The semiconductor device shown in FIG. 9 is different from the semiconductor device shown in FIG. 8 in that the resin sealing frame 11 is also provided at a position close to the outer peripheral portion of the semiconductor 10, so that the semiconductor 10 is protected and sealed. The use amount of the sealing resin 11 is also reduced.
【００４６】また、図10の半導体装置は、特に、半導体
10と立体回路基板22との固着による密着部およびこの密
着部周囲における立体回路基板22表面に金属膜27を形成
している。つまり、この金属膜27によって、半導体10が
発生する熱を放出させることができ、また、同金属膜27
によって、電磁波をシールドすることができるものであ
る。したがって、この半導体装置は放熱性が向上したも
のになっており、また、半導体10自身から電磁波を放出
することがないとともに、外部からの電磁波をこの半導
体10自身が受けることがなく、耐ノイズ性に優れたもの
になっているのである。The semiconductor device shown in FIG.
A metal film 27 is formed on the adhered portion formed by the adhesion between 10 and the three-dimensional circuit board 22, and on the surface of the three-dimensional circuit board 22 around the adhered portion. That is, the heat generated by the semiconductor 10 can be released by the metal film 27, and the metal film 27
Thus, electromagnetic waves can be shielded. Therefore, this semiconductor device has an improved heat radiation property, does not emit electromagnetic waves from the semiconductor 10 itself, and does not receive external electromagnetic waves from the semiconductor 10 itself. It has become excellent.
【００４７】また、図11の半導体装置は、特に、（Ａ)
に示すように、半導体10をインサート成形することによ
って半導体10を前記立体回路基板22に搭載し、（Ｂ) に
示すように、回路パターン３を形成することによって立
体回路基板22を形成している。そして、（Ｃ) にしめす
ように、このようにして半導体10が搭載された立体回路
基板10に、金線ワイヤー12によるワイヤーボンディング
（配線接続）を行い、（Ｄ) に示すように、樹脂封止し
て半導体装置を得ている。Further, the semiconductor device of FIG.
As shown in FIG. 3, the semiconductor 10 is mounted on the three-dimensional circuit board 22 by insert molding the semiconductor 10, and the three-dimensional circuit board 22 is formed by forming the circuit pattern 3 as shown in FIG. . Then, as shown in (C), wire bonding (wiring connection) using gold wire 12 is performed on the three-dimensional circuit board 10 on which the semiconductor 10 is mounted as described above, and as shown in (D), resin sealing is performed. Stopped to obtain a semiconductor device.
【００４８】つまり、立体回路基板22に後から半導体10
を搭載する必要がなくなっており、工程が簡略で製造容
易なものになっている。That is, the semiconductor 10 is later placed on the three-dimensional circuit board 22.
Is no longer necessary, and the process is simple and easy to manufacture.
【００４９】図12ないし図16を参照して、さらに異なる
半導体装置を以下に説明する。これらの図は異なる一つ
の半導体装置をそれぞれ示す断面図である。A further different semiconductor device will be described below with reference to FIGS. These figures are cross-sectional views each showing one different semiconductor device.
【００５０】以上の図に示すように、これらの半導体装
置は、図１ないし図11を参照して説明したような半導体
装置を一つの単位とし、このような単位の半導体装置を
構成する立体回路基板22を積層して形成されている多層
構成のものである。As shown in the above figures, these semiconductor devices have the three-dimensional circuit constituting the semiconductor device of such a unit as a single unit of the semiconductor device described with reference to FIGS. It has a multilayer structure formed by laminating substrates 22.
【００５１】そして、以上のような半導体装置によれ
ば、封止樹脂11または半導体10の部分を凹部２内に納め
た状態で、立体回路基板22を積層することができるので
ある。つまり、一方の立体回路基板22における脚壁24の
先端部を他方の立体回路基板22に当接させることができ
る。したがって、封止樹脂11の部分ないし半導体10の部
分を凹部２内に納めて保護した状態で、立体回路基板22
を積層することができるのである。また、積層工程にお
ける上下の立体回路基板22の位置決めや電気的な接続が
容易になるので、接続信頼性が高く、多層であって高集
積の半導体装置になっている。According to the semiconductor device described above, the three-dimensional circuit board 22 can be stacked with the sealing resin 11 or the semiconductor 10 in the recess 2. That is, the tip of the leg wall 24 on one three-dimensional circuit board 22 can be brought into contact with the other three-dimensional circuit board 22. Therefore, while the portion of the sealing resin 11 or the portion of the semiconductor 10 is housed in the recess 2 and protected, the three-dimensional circuit board 22
Can be laminated. In addition, since the positioning and electrical connection of the upper and lower three-dimensional circuit boards 22 in the laminating step are facilitated, the connection reliability is high, and a multi-layered and highly integrated semiconductor device is obtained.
【００５２】より具体的には、図12または図13に示す半
導体装置は、図１または図３に示した半導体装置をそれ
ぞれ上下に二段に積層したものである。More specifically, the semiconductor device shown in FIG. 12 or FIG. 13 has the semiconductor device shown in FIG. 1 or FIG.
【００５３】また、図14または図15の半導体装置は、図
１および図３示した半導体装置を組み合わせて積層した
ものであって、図14のものは上方の立体回路基板22の凹
部２内に、両方の単位の配線部分における樹脂封止部を
納めて積層しており、図15のものでは上方の立体回路基
板22の凹部２内に、両方の単位の半導体20を納めて積層
している。The semiconductor device shown in FIG. 14 or FIG. 15 is obtained by combining and stacking the semiconductor devices shown in FIG. 1 and FIG. 3, and the semiconductor device shown in FIG. In FIG. 15, both units of the semiconductor 20 are placed and laminated in the concave portion 2 of the three-dimensional circuit board 22 above. .
【００５４】また、図16の半導体装置は、図５に示す半
導体装置を上下二段に積層しているものである。The semiconductor device shown in FIG. 16 has the semiconductor device shown in FIG. 5 stacked vertically in two stages.
【００５５】図17ないし図20を参照して、さらに異なる
半導体装置を以下に説明する。これらの図はそれぞれ異
なる半導体装置を示す図であって、それぞれ積層される
単位の半導体装置を積層するための構成を説明する斜視
図または断面図である。Referring to FIGS. 17 to 20, a further different semiconductor device will be described below. These figures are views showing different semiconductor devices, and are perspective views or cross-sectional views for explaining a structure for stacking semiconductor devices in units to be stacked.
【００５６】図17に示す半導体装置は、上記図12ないし
図16の半導体装置において、立体回路基板22を積層する
際に互いに嵌合する嵌合凸部31および嵌合凹部32を、脚
壁24の先端面と平板周縁部とにそれぞれ設けたものを示
している。なお、この図には平板周縁部に設けられた嵌
合凸部31のみを示している。つまり、この図に表れない
脚壁24の先端面には、前記嵌合凸部31に嵌合する嵌合凹
部32が設けられている。The semiconductor device shown in FIG. 17 is different from the semiconductor device shown in FIGS. 12 to 16 in that a fitting projection 31 and a fitting recess 32 which are fitted to each other when the three-dimensional circuit boards 22 are stacked are combined with the leg walls 24. Are provided on the tip end surface and the peripheral edge of the flat plate, respectively. In this figure, only the fitting projection 31 provided on the periphery of the flat plate is shown. That is, a fitting concave portion 32 that fits into the fitting convex portion 31 is provided on the tip end surface of the leg wall 24 that is not shown in this figure.
【００５７】このような半同装置では、嵌合凸部31と嵌
合凹部32とを互いに嵌合させることによって、正確な位
置にずれることなく立体回路基板22が積層される。した
がって、狭ピッチの回路パターン３を有する半導体装置
をも多層化することができ、高集積度で信頼性の高い半
導体装置になっている。In such a semi-semiconductor device, the fitting projection 31 and the fitting recess 32 are fitted to each other, so that the three-dimensional circuit boards 22 are stacked without being shifted to an accurate position. Therefore, the semiconductor device having the circuit pattern 3 having a narrow pitch can be formed into a multilayer, and the semiconductor device has high integration and high reliability.
【００５８】また、図18は半導体装置の要部を示し、
（Ａ) は積層された状態の断面図であり、（Ｂ) は積層
する前の一方の単位の斜視図である。FIG. 18 shows a main part of the semiconductor device.
(A) is a cross-sectional view of a stacked state, and (B) is a perspective view of one unit before being stacked.
【００５９】この半導体装置では、立体回路基板22の積
層時に互いに重なる面における回路パターン３のアウタ
ーリード部に接続凹部25を設けている。そして、これら
の接続凹部25の位置を積層した状態で重ね合わされたそ
れぞれの面で一致させるとともに、これらの接続凹部25
内に導電性の接続材料26を充填して積層しているのであ
る。このような接続材料26としては、はんだボールなど
を例示することができる。In this semiconductor device, the connection concave portion 25 is provided in the outer lead portion of the circuit pattern 3 on the surface overlapping each other when the three-dimensional circuit boards 22 are stacked. Then, the positions of these connection recesses 25 are made to coincide with each other on the superposed surfaces in a stacked state, and these connection recesses 25 are formed.
The inside is filled with a conductive connection material 26 and laminated. Examples of such a connection material 26 include a solder ball and the like.
【００６０】このような半導体装置によれば、接続材料
26によって上下の立体回路基板22を、強固に接合すると
ともに、電気的にも接続することができるものになって
いる。According to such a semiconductor device, the connection material
26 allows the upper and lower three-dimensional circuit boards 22 to be firmly joined and also electrically connected.
【００６１】また、図19は半導体装置の要部を示し、
（Ａ) は積層された状態の断面図であり、（Ｂ) は積層
する前のそれぞれの単位の斜視図である。FIG. 19 shows a main part of the semiconductor device.
(A) is a cross-sectional view of a stacked state, and (B) is a perspective view of each unit before being stacked.
【００６２】この半導体装置は、図12ないし図16の半導
体装置において、積層時に互いに嵌合する嵌合凸部31お
よび嵌合凹部32を、立体回路基板22における回路パター
ン３のアウターリード部に形成しているものである。This semiconductor device is different from the semiconductor device shown in FIGS. 12 to 16 in that a fitting convex portion 31 and a fitting concave portion 32 that are fitted to each other at the time of lamination are formed in the outer lead portion of the circuit pattern 3 on the three-dimensional circuit board 22. Is what you are doing.
【００６３】したがって、このような半導体装置によれ
ば、嵌合凸部31および嵌合凹部32の嵌合によって、はん
だ接合することなしに、電気的な接続が確実になされる
ものになっている。Therefore, according to such a semiconductor device, by the fitting of the fitting projections 31 and the fitting recesses 32, electrical connection can be reliably made without soldering. .
【００６４】また、図20は半導体装置の要部を示し、積
層された状態の断面図である。この半導体装置は、図12
ないし図16の半導体装置において、立体回路基板22を積
層する際に互いに嵌合する嵌合凸部31および嵌合凹部32
を、脚壁24外面の上部と下部とにおけるアウターリード
部にそれぞれ設けている。FIG. 20 is a cross-sectional view showing a main part of the semiconductor device in a stacked state. This semiconductor device is shown in FIG.
In the semiconductor device of FIG. 16, the fitting convex portion 31 and the fitting concave portion 32 fitted to each other when the three-dimensional circuit boards 22 are stacked.
Are provided on the outer lead portions at the upper and lower portions of the outer surface of the leg wall 24, respectively.
【００６５】このような半導体装置によれば、嵌合凸部
31と嵌合凹部32とを互いに嵌合させることによって、正
確な位置に、ずれることなく立体回路基板22が積層され
るので、狭ピッチの回路パターン３を有する半導体装置
を多層化することができ、高集積度で信頼性の高い半導
体装置になっている。According to such a semiconductor device, the fitting convex portion
Since the three-dimensional circuit board 22 is stacked at the correct position without displacement by fitting the fitting recess 32 to the fitting recess 32, the semiconductor device having the narrow-pitch circuit pattern 3 can be multilayered. The semiconductor device has a high degree of integration and high reliability.
【００６６】[0066]
【発明の効果】請求項１記載の発明では、回路パターン
と半導体とを接続孔を通して、最短距離でワイヤーボン
ディングなどによる配線接続することができる。したが
って、半導体の中央部に配線用パッドがある場合にあっ
ても、この配線用パッドと回路パターンとを最短距離で
接続することが可能になっている。このため、配線作業
が容易になっているとともに、この配線接続を確実に行
うことができるので、信頼性の高い接続がなされる半導
体装置になっている。According to the first aspect of the present invention, the circuit pattern and the semiconductor can be connected to each other by wire bonding or the like at the shortest distance through the connection hole. Therefore, even when there is a wiring pad in the center of the semiconductor, it is possible to connect the wiring pad and the circuit pattern with the shortest distance. For this reason, the wiring operation is facilitated, and the wiring connection can be reliably performed, so that the semiconductor device has a highly reliable connection.
【００６７】請求項２記載の発明では、半導体を凹部内
に保護することができるので、信頼性を向上させること
ができる。According to the second aspect of the present invention, since the semiconductor can be protected in the concave portion, the reliability can be improved.
【００６８】請求項３記載の発明では、樹脂封止によっ
て配線接続部を保護することができるので、信頼性を向
上させることができる。According to the third aspect of the present invention, since the wiring connection portion can be protected by resin sealing, the reliability can be improved.
【００６９】請求項４記載の発明では、樹脂封止枠によ
って、一定深さに樹脂封止を容易に行うことができるの
で、製造容易で高信頼性のものになっている。According to the fourth aspect of the present invention, the resin sealing can be easily performed at a predetermined depth by the resin sealing frame, so that the manufacturing is easy and the reliability is high.
【００７０】請求項５記載の発明では、金属膜によっ
て、半導体が発生する熱を放出させることができ、半導
体装置の放熱性が向上している。また、この金属膜によ
って、電磁波をシールドすることもでき、半導体の耐ノ
イズ性が向上しているとともに、半導体からもノイズを
出すことがなくなっている。According to the fifth aspect of the present invention, the heat generated by the semiconductor can be released by the metal film, and the heat dissipation of the semiconductor device is improved. In addition, the metal film can also shield electromagnetic waves, improving the noise resistance of the semiconductor and eliminating noise from the semiconductor.
【００７１】請求項６記載の発明では、立体回路基板に
後から半導体を搭載する必要がなく、工程が簡略なもの
になって、製造容易な半導体装置になっている。According to the sixth aspect of the present invention, it is not necessary to mount a semiconductor on the three-dimensional circuit board later, so that the process is simplified and the semiconductor device is easy to manufacture.
【００７２】請求項７記載の発明では、積層した状態に
おいて、一方の立体回路基板における脚壁の先端部を他
方の立体回路基板に当接させることができる。したがっ
て、封止樹脂の部分ないし半導体の部分を凹部内に納め
て保護した状態で、立体回路基板を積層することができ
る。また、積層工程における上下の立体回路基板の位置
決めや電気的な接続が容易になるので、接続信頼性が高
い多層の半導体装置になっている。According to the seventh aspect of the present invention, in a stacked state, the tip of the leg wall of one three-dimensional circuit board can be brought into contact with the other three-dimensional circuit board. Therefore, the three-dimensional circuit board can be laminated while the sealing resin portion or the semiconductor portion is housed in the recess and protected. In addition, since the positioning and electrical connection of the upper and lower three-dimensional circuit boards in the laminating process are facilitated, a multi-layer semiconductor device having high connection reliability is provided.
【００７３】請求項８記載の発明では、嵌合凸部と嵌合
凹部とを互いに嵌合させることによって、正確な位置に
立体回路基板が積層されている。したがって、狭ピッチ
の回路パターンを有する半導体装置を多層化することが
でき、高集積度で信頼性の高い半導体装置になってい
る。According to the eighth aspect of the present invention, the three-dimensional circuit board is laminated at an accurate position by fitting the fitting projection and the fitting recess to each other. Therefore, a semiconductor device having a circuit pattern with a narrow pitch can be multilayered, and a highly integrated and highly reliable semiconductor device is obtained.
【００７４】請求項９記載の発明では、アウターリード
部における嵌合凸部および嵌合凹部の嵌合によって電気
的な接続が確実になされている。According to the ninth aspect of the present invention, the electrical connection is ensured by the fitting of the fitting projection and the fitting recess in the outer lead portion.
【００７５】請求項10記載の発明では、接続材料によっ
て上下の立体回路基板の強固な接合がなされるととも
に、電気的な接続も確実に行われている。According to the tenth aspect of the present invention, the upper and lower three-dimensional circuit boards are firmly joined by the connecting material, and the electrical connection is reliably performed.
【００７６】請求項11記載の発明では、嵌合凸部と嵌合
凹部とを互いに嵌合させることによって、正確な位置に
立体回路基板が積層されている。したがって、狭ピッチ
の回路パターンを有する半導体装置を多層化することが
でき、高集積度で信頼性の高い半導体装置になってい
る。According to the eleventh aspect of the present invention, the three-dimensional circuit board is laminated at an accurate position by fitting the fitting projection and the fitting recess to each other. Therefore, a semiconductor device having a circuit pattern with a narrow pitch can be multilayered, and a highly integrated and highly reliable semiconductor device is obtained.
【図１】本発明の実施の形態の一つの半導体装置を示す
断面図である。FIG. 1 is a cross-sectional view showing one semiconductor device according to an embodiment of the present invention.
【図２】同上の異なる一つの半導体装置を示す断面図で
ある。FIG. 2 is a cross-sectional view showing one different semiconductor device according to the first embodiment;
【図３】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 3 is a cross-sectional view showing another different semiconductor device according to the first embodiment;
【図４】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 4 is a cross-sectional view showing another different semiconductor device according to the first embodiment;
【図５】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 5 is a cross-sectional view showing another different semiconductor device according to the first embodiment;
【図６】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 6 is a cross-sectional view showing another different semiconductor device according to the first embodiment;
【図７】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 7 is a cross-sectional view showing another different semiconductor device of the above.
【図８】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 8 is a cross-sectional view showing another different semiconductor device of the above.
【図９】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 9 is a cross-sectional view showing another different semiconductor device of the above.
【図10】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 10 is a cross-sectional view showing another different semiconductor device of the above.
【図11】同上のさらに異なる一つの半導体装置を示す断
面図であり、（Ａ) 〜（Ｃ) に製造工程途中の状態を順
に示し、（Ｄ) に完成状態を示している。FIGS. 11A to 11C are cross-sectional views showing another different semiconductor device according to the first embodiment, in which (A) to (C) show states in the course of the manufacturing process in order, and (D) shows a completed state.
【図12】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 12 is a cross-sectional view showing another different semiconductor device of the above.
【図13】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 13 is a cross-sectional view showing another different semiconductor device of the above.
【図14】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 14 is a cross-sectional view showing another different semiconductor device of the above.
【図15】同上のさらに異なる一つの半導体装置を示す斜
視図である。FIG. 15 is a perspective view showing another different semiconductor device of the above.
【図16】同上のさらに異なる一つの半導体装置を示す断
面図である。FIG. 16 is a cross-sectional view showing another different semiconductor device of the above.
【図17】同上のさらに異なる一つの半導体装置を示す斜
視図である。FIG. 17 is a perspective view showing another different semiconductor device of the above.
【図18】同上のさらに異なる一つの半導体装置を示し、
（Ａ) に要部の断面図を、（Ｂ) に要部の斜視図を示し
ている。FIG. 18 shows a further different semiconductor device according to the above.
(A) is a cross-sectional view of the main part, and (B) is a perspective view of the main part.
【図19】同上のさらに異なる一つの半導体装置を示し、
（Ａ) に要部の断面図を、（Ｂ) に要部の斜視図を示し
ている。FIG. 19 shows a further different semiconductor device according to the above;
(A) is a cross-sectional view of the main part, and (B) is a perspective view of the main part.
【図20】同上のさらに異なる一つの半導体装置を示して
いる。FIG. 20 shows another different semiconductor device of the above.
【図21】従来例を示す断面図である。FIG. 21 is a cross-sectional view illustrating a conventional example.
【図22】従来例を示す斜視図である。FIG. 22 is a perspective view showing a conventional example.
１ マザーボード ２ 凹部 ３ 回路パターン 10 半導体 11 封止樹脂 12 金線ワイヤー 13 接着剤 14 はんだ 20 接続孔 22 立体回路基板 23 樹脂封止枠 24 脚壁 25 接続凹部 26 接続材料 27 金属膜 31 嵌合凸部 32 嵌合凹部 DESCRIPTION OF SYMBOLS 1 Motherboard 2 Concave part 3 Circuit pattern 10 Semiconductor 11 Sealing resin 12 Gold wire 13 Adhesive 14 Solder 20 Connection hole 22 Three-dimensional circuit board 23 Resin sealing frame 24 Leg wall 25 Connection concave part 26 Connection material 27 Metal film 31 Fitting convex Part 32 mating recess
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 25/11 (72)発明者 平田 勲夫 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 中谷 卓也 大阪府門真市大字門真1048番地松下電工株 式会社内──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification symbol FI H01L 25/11 (72) Inventor Isao Hirata 1048 Odomo Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Takuya Nakatani 1048 Kadoma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd.
Claims (11)
形による立体回路基板を形成し、この立体回路基板の片
面に半導体を搭載し、この半導体と立体回路基板に形成
された回路パターンとを配線接続して成る半導体装置に
おいて、表裏いずれか一方の面に半導体を固着し、立体
回路基板の表面から凹部側の裏面に接続孔を貫通形成
し、この接続孔を半導体の配線用パッドの部分に位置さ
せ、この配線用パッドと、この半導体を固着した面と反
対側の面における回路パターンとを、接続孔を通過させ
て配線接続して成ることを特徴とする半導体装置。1. A three-dimensional circuit board is formed by resin molding by providing a concave portion on at least one side, a semiconductor is mounted on one side of the three-dimensional circuit board, and wiring is performed between the semiconductor and a circuit pattern formed on the three-dimensional circuit board. In a semiconductor device that is connected, a semiconductor is fixed to one of the front and back surfaces, and a connection hole is formed through the surface of the three-dimensional circuit board from the front surface to the concave surface, and the connection hole is formed in a portion of a semiconductor wiring pad. A semiconductor device, wherein the wiring pad and a circuit pattern on a surface opposite to a surface to which the semiconductor is fixed are connected by wiring through a connection hole.
とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor is provided on the concave side.
から半導体にかけての部分を樹脂封止して成ることを特
徴とする請求項１または２のいずれかに記載の半導体装
置。3. The semiconductor device according to claim 1, wherein the semiconductor device includes at least a connection hole, and a portion from the connection hole to the semiconductor is sealed with a resin.
て成ることを特徴とする請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein the resin sealing frame is provided integrally with the three-dimensional circuit board.
着部およびこの密着部周囲における立体回路基板表面に
金属膜を形成して成ることを特徴とする請求項１記載の
半導体装置。5. The semiconductor device according to claim 1, wherein a metal film is formed on a contact portion between the semiconductor and the three-dimensional circuit board and a surface of the three-dimensional circuit board around the close contact portion.
板を形成することによって、半導体を前記立体回路基板
に搭載してなることを特徴とする請求項１記載の半導体
装置。6. The semiconductor device according to claim 1, wherein the semiconductor is mounted on the three-dimensional circuit board by forming a three-dimensional circuit board by insert-forming a semiconductor.
囲まれた空間を凹部とする形状に立体回路基板を形成
し、この立体回路基板を積層して成ることを特徴とする
請求項１ないし６のいずれかに記載の半導体装置。7. A three-dimensional circuit board is formed by suspending a leg wall around a flat plate, forming a three-dimensional circuit board in a shape having a space surrounded by the leg wall as a recess, and laminating the three-dimensional circuit board. The semiconductor device according to claim 1, wherein:
する嵌合凸部および嵌合凹部を、脚壁の端面と平板周縁
部とにそれぞれ設けて成ることを特徴とする請求項７記
載の半導体装置。8. The method according to claim 7, wherein a fitting projection and a fitting recess which are fitted to each other when the three-dimensional circuit boards are stacked are provided on an end face of the leg wall and a peripheral edge of the flat plate. Semiconductor device.
板におけるアウターリード部に形成して成ることを特徴
とする請求項８記載の半導体装置。9. The semiconductor device according to claim 8, wherein the fitting protrusion and the fitting recess are formed on an outer lead portion of the three-dimensional circuit board.
におけるアウターリード部に接続凹部を設け、これらの
接続凹部の位置を積層した状態で重ね合わされたそれぞ
れの面で一致させるとともに、これらの接続凹部内に導
電性の接続材料を充填して積層して成ることを特徴とす
る請求項７記載の半導体装置。10. A connecting recess is provided in an outer lead portion on a surface overlapping each other when a three-dimensional circuit board is laminated, and the positions of these connecting recesses are made to coincide with each other in a stacked state, and these connecting recesses are formed. 8. The semiconductor device according to claim 7, wherein the semiconductor device is formed by filling and laminating a conductive connection material therein.
する嵌合凸部および嵌合凹部を、脚壁の上部と下部とに
それぞれ設けて成ることを特徴とする請求項７に記載の
半導体装置。11. The method according to claim 7, wherein a fitting projection and a fitting recess that fit with each other when the three-dimensional circuit boards are stacked are provided on an upper portion and a lower portion of the leg wall, respectively. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9229031A JPH1167963A (en) | 1997-08-26 | 1997-08-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9229031A JPH1167963A (en) | 1997-08-26 | 1997-08-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1167963A true JPH1167963A (en) | 1999-03-09 |
Family
ID=16885670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9229031A Pending JPH1167963A (en) | 1997-08-26 | 1997-08-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1167963A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007214583A (en) * | 1999-07-22 | 2007-08-23 | Seiko Epson Corp | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
| US7613010B2 (en) | 2004-02-02 | 2009-11-03 | Panasonic Corporation | Stereoscopic electronic circuit device, and relay board and relay frame used therein |
| JP2010521818A (en) * | 2007-03-12 | 2010-06-24 | マイクロン テクノロジー， インク． | Semiconductor device packaging apparatus, packaged semiconductor component, manufacturing method of semiconductor device packaging apparatus, and manufacturing method of semiconductor component |
| US8368230B2 (en) | 2009-08-20 | 2013-02-05 | Fujitsu Limited | Electronic part and method of manufacturing the same |
| US8546187B2 (en) | 2009-08-20 | 2013-10-01 | Fujitsu Limited | Electronic part and method of manufacturing the same |
| JP2016051710A (en) * | 2014-08-28 | 2016-04-11 | 京セラ株式会社 | Wiring board, electronic device and multilayer electronic device |
| CN111373517A (en) * | 2018-03-01 | 2020-07-03 | 新电元工业株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN112687631A (en) * | 2020-12-25 | 2021-04-20 | 杭州耀芯科技有限公司 | SIP packaging device and preparation method |
-
1997
- 1997-08-26 JP JP9229031A patent/JPH1167963A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007214583A (en) * | 1999-07-22 | 2007-08-23 | Seiko Epson Corp | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
| JP4562006B2 (en) * | 1999-07-22 | 2010-10-13 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| US7613010B2 (en) | 2004-02-02 | 2009-11-03 | Panasonic Corporation | Stereoscopic electronic circuit device, and relay board and relay frame used therein |
| JP2010521818A (en) * | 2007-03-12 | 2010-06-24 | マイクロン テクノロジー， インク． | Semiconductor device packaging apparatus, packaged semiconductor component, manufacturing method of semiconductor device packaging apparatus, and manufacturing method of semiconductor component |
| US8368230B2 (en) | 2009-08-20 | 2013-02-05 | Fujitsu Limited | Electronic part and method of manufacturing the same |
| US8546187B2 (en) | 2009-08-20 | 2013-10-01 | Fujitsu Limited | Electronic part and method of manufacturing the same |
| JP2016051710A (en) * | 2014-08-28 | 2016-04-11 | 京セラ株式会社 | Wiring board, electronic device and multilayer electronic device |
| CN111373517A (en) * | 2018-03-01 | 2020-07-03 | 新电元工业株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN111373517B (en) * | 2018-03-01 | 2024-03-19 | 新电元工业株式会社 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
| CN112687631A (en) * | 2020-12-25 | 2021-04-20 | 杭州耀芯科技有限公司 | SIP packaging device and preparation method |
| CN112687631B (en) * | 2020-12-25 | 2024-04-26 | 杭州耀芯科技有限公司 | SIP packaging device and preparation method |
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