JP2016051710A - Wiring board, electronic device and multilayer electronic device - Google Patents

Wiring board, electronic device and multilayer electronic device Download PDF

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JP2016051710A
JP2016051710A JP2014174097A JP2014174097A JP2016051710A JP 2016051710 A JP2016051710 A JP 2016051710A JP 2014174097 A JP2014174097 A JP 2014174097A JP 2014174097 A JP2014174097 A JP 2014174097A JP 2016051710 A JP2016051710 A JP 2016051710A
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frame
main surface
terminal
electronic device
wiring board
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JP6336858B2 (en
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武士 吉元
Takeshi Yoshimoto
武士 吉元
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board, and the like, effective for compaction and thinning.SOLUTION: A wiring board, and the like, includes a first frame-like plate 1 having a first principal surface and a second principal surface, and a first opening in the central part, a second frame-like plate 2 laminated on the second principal surface side of the first frame-like plate 1, and having a third principal surface and a fourth principal surface, and a second opening larger than the first opening in the central part, a first terminal 4 provided on the first principal surface, and a second terminal 5 provided on the second principal surface exposed on the inside of the second frame-like plate 2. An electronic component 11 is housed in the opening, and since the upper and lower electrodes 12a, 13a of the electronic component 11 are connected electrically with the first and second terminals 4, 5, a wiring board 10, and the like, effective for thinning can be provided.SELECTED DRAWING: Figure 1

Description

本発明は、電子部品が実装される配線基板、その配線基板を含む電子装置および積層型電子装置に関するものである。   The present invention relates to a wiring board on which electronic components are mounted, an electronic device including the wiring board, and a stacked electronic device.

半導体素子および容量素子等の電子部品が収容される配線基板として、上面に電子部品の搭載部を有する絶縁基板と、絶縁基板の搭載部から下面にかけて設けられた配線導体とを含むものが知られている。また、絶縁基板の上面に搭載部を囲むように絶縁枠体が積層される場合がある。この場合、絶縁基板の上面と絶縁枠体とによって電子部品を収容するための凹部が形成される。また、近年、電子装置の薄型化等のために、複数の電子部品が互いに上下に積層されて配線基板の搭載部に搭載される場合がある。   2. Description of the Related Art As a wiring board that accommodates electronic components such as semiconductor elements and capacitive elements, a wiring board that includes an insulating substrate having an electronic component mounting portion on an upper surface and a wiring conductor provided from the insulating substrate mounting portion to the lower surface is known. ing. In some cases, an insulating frame is stacked on the upper surface of the insulating substrate so as to surround the mounting portion. In this case, a recess for accommodating an electronic component is formed by the upper surface of the insulating substrate and the insulating frame. In recent years, in order to reduce the thickness of electronic devices, a plurality of electronic components may be stacked one above the other and mounted on a mounting portion of a wiring board.

配線導体のうち搭載部に設けられた部分と電子部品とが電気的に接続され、絶縁基板の下面に設けられた部分と外部電気回路とが電気的に接続される。これにより、搭載部に搭載される電子部品と外部電気回路とが電気的に接続される。   Of the wiring conductor, the portion provided on the mounting portion and the electronic component are electrically connected, and the portion provided on the lower surface of the insulating substrate and the external electric circuit are electrically connected. Thereby, the electronic component mounted in the mounting part and the external electric circuit are electrically connected.

特開2003−243636号公報Japanese Patent Laid-Open No. 2003-243636

上記従来の技術においては、電子装置として、少なくとも電子部品（複数が互いに積層されたものを含む）の厚みと絶縁基板の厚みとを合計した厚みが必要であるため、さらなる薄型化が難しいという問題点があった。   In the above-described conventional technology, the electronic device needs to have at least the total thickness of the electronic components (including a plurality of stacked ones) and the thickness of the insulating substrate. There was a point.

本発明の実施形態の配線基板は、第１主面および該第１主面と反対側の第２主面を有しているとともに中央部に第１開口部を有する第１枠状板と、該第１枠状板の前記第２主面側に積層されており、前記第２主面に対向している第３主面と該第３主面と反対側の第４主面を有しているとともに、中央部に前記第１開口部よりも大きい第２開口部を有する第２枠状板と、前記第１主面に設けられた第１端子と、前記第２枠状板の内側で露出している前記第２主面に設けられた第２端子とを備えている。第１電極を有する第１電子部品と第２電極を有する第２電子部品とを含む積層部品が、前記第１電極と前記第１端子とが接続されるとともに、前記第２電極と前記第２端子とが接続されるように実装される。   A wiring board according to an embodiment of the present invention includes a first frame-like plate having a first main surface and a second main surface opposite to the first main surface and having a first opening at the center, The first frame-shaped plate is laminated on the second main surface side, and has a third main surface facing the second main surface and a fourth main surface opposite to the third main surface. And a second frame-shaped plate having a second opening larger than the first opening at the center, a first terminal provided on the first main surface, and an inner side of the second frame-shaped plate And a second terminal provided on the second main surface exposed at. A laminated component including a first electronic component having a first electrode and a second electronic component having a second electrode is connected to the first electrode and the first terminal, and the second electrode and the second electrode. It is mounted so that the terminal is connected.

本発明の実施形態の電子装置は、上記構成の配線基板と、第１電極を有する第１電子部品と第２電極を有する第２電子部品とが互いに積層されてなる積層部品とを備えている。平面透視において前記第２電子部品が前記第１開口内に位置しているとともに、前記第１電極の少なくとも一部が前記第１開口よりも外側に位置しており、前記第１端子と前記第１電極とが互いに対向し合って接続されており、前記第２端子と前記第２電極とが導電性接続材を介して接続されているとともに、該導電性接続材の全体が前記第４主面よりも前記第３主面側に位置している。   An electronic device according to an embodiment of the present invention includes a wiring board configured as described above, and a laminated component in which a first electronic component having a first electrode and a second electronic component having a second electrode are laminated with each other. . In plan view, the second electronic component is located in the first opening, and at least a part of the first electrode is located outside the first opening, and the first terminal and the first electrode One electrode is connected to face each other, the second terminal and the second electrode are connected via a conductive connecting material, and the entire conductive connecting material is the fourth main electrode. It is located closer to the third main surface than the surface.

本発明の実施形態の積層型電子装置は、上記構成の複数の電子装置が、互いに上下に積層されて形成されている。   A stacked electronic device according to an embodiment of the present invention is formed by stacking a plurality of electronic devices having the above-described configuration one above the other.

本発明の一つの態様の配線基板によれば、第１枠状板および第２枠状板の枠部分に積層部品が収容されるとともに、その枠部分の上下に位置する第１端子および第２端子に積層部品の第１電極および第２電極が接続される。そのため、この配線基板を用いて作製される電子装置は、積層部品と同じ程度の厚みまでの薄型化が可能である。したがって、本発明の配線基板によれば、電子装置の薄型化が容易な配線基板を提供することができる。   According to the wiring board of one aspect of the present invention, the laminated component is accommodated in the frame portions of the first frame-shaped plate and the second frame-shaped plate, and the first terminal and the second terminal positioned above and below the frame portion are accommodated. The first electrode and the second electrode of the laminated component are connected to the terminal. Therefore, an electronic device manufactured using this wiring board can be thinned to the same thickness as a laminated component. Therefore, according to the wiring board of the present invention, it is possible to provide a wiring board in which the electronic device can be easily thinned.

本発明の一つの態様の電子装置によれば、上記構成の配線基板に積層部品が収容および接続されてなることから、薄型化が容易な電子装置を提供することができる。   According to the electronic device of one aspect of the present invention, since the multilayer component is accommodated and connected to the wiring board having the above-described configuration, an electronic device that can be easily reduced in thickness can be provided.

本発明の一つの態様の積層型電子装置によれば、上記構成の複数の電子装置が互いに上下に積層されてなることから、より一層の高集積化における薄型化について有利な積層型電子装置を提供することができる。   According to the multilayer electronic device of one aspect of the present invention, since the plurality of electronic devices having the above-described configuration are stacked one above the other, it is possible to provide a multilayer electronic device that is advantageous for further thinning in higher integration. Can be provided.

（ａ）は本発明の第１の実施形態の配線基板および電子装置を示す断面図であり、（ｂ）はその下面の一例を示す下面図である。(A) is sectional drawing which shows the wiring board and electronic device of the 1st Embodiment of this invention, (b) is a bottom view which shows an example of the lower surface. （ａ）〜（ｃ）はそれぞれ図１に示す配線基板および電子装置の変形例を示す断面図である。(A)-(c) is sectional drawing which shows the modification of the wiring board and electronic device which are respectively shown in FIG. （ａ）は本発明の第２の実施形態の配線基板および電子装置を示す断面図であり、（ｂ）はその下面の一例を示す下面図である。(A) is sectional drawing which shows the wiring board and electronic device of the 2nd Embodiment of this invention, (b) is a bottom view which shows an example of the lower surface. 本発明の第３の実施形態の電子装置を示す断面図である。It is sectional drawing which shows the electronic device of the 3rd Embodiment of this invention. 本発明の実施形態の積層型電子装置を示す断面図である。1 is a cross-sectional view illustrating a stacked electronic device according to an embodiment of the present invention.

本発明の実施形態の配線基板およびを、添付の図面を参照して説明する。   A wiring board and an embodiment of the present invention will be described with reference to the accompanying drawings.

（第１の実施形態）
図１（ａ）は本発明の第１の実施形態の配線基板および電子装置を示す断面図であり、図１（ｂ）は図１（ａ）の下面を示す下面図である。第１枠状板１と、第１枠状板に積層された第２枠状板２とによって絶縁基体３が形成され、絶縁基体３に第１端子４および第２端子５が設けられて配線基板10が基本的に形成されている。また、配線基板10に電子部品11が実装されて電子装置20が形成されている。 (First embodiment)
FIG. 1A is a cross-sectional view showing a wiring board and an electronic device according to a first embodiment of the present invention, and FIG. 1B is a bottom view showing a lower surface of FIG. An insulating base 3 is formed by the first frame-like plate 1 and the second frame-like plate 2 laminated on the first frame-like plate, and the first base 4 and the second terminal 5 are provided on the insulating base 3 to provide wiring. A substrate 10 is basically formed. Further, the electronic device 11 is formed by mounting the electronic component 11 on the wiring board 10.

第１および第２枠状板１、２は、電子部品11を収容して保持するための部分である。第１枠状板１は、その中央部に貫通部である第１開口部を有している。第２枠状板２は、その中央部に貫通部である第２開口部を有している。第１および第２開口部内に電子部品11が収容される。すなわち、第１枠状板１の開口部と第２枠状板２の開口部とが上下につながって、電子部品11が収容される一つの収納用開口部を形成している。開口部内に収容された電子部品は、後述する導電性接続材等の接合手段によって絶縁基体３に固定される。   The first and second frame-like plates 1 and 2 are portions for accommodating and holding the electronic component 11. The 1st frame-shaped board 1 has the 1st opening part which is a penetration part in the center part. The 2nd frame-shaped board 2 has the 2nd opening part which is a penetration part in the center part. The electronic component 11 is accommodated in the first and second openings. In other words, the opening of the first frame-like plate 1 and the opening of the second frame-like plate 2 are connected in the vertical direction to form one housing opening for housing the electronic component 11. The electronic component accommodated in the opening is fixed to the insulating base 3 by a joining means such as a conductive connecting material described later.

電子部品11としては、例えば、ＩＣやＬＳＩ等の半導体集積回路素子、およびＬＥＤ（発光ダイオード）やＰＤ（フォトダイオード），ＣＣＤ（電荷結合素子）等の光半導体素子、半導体基板の表面に微小な電子機械機構が形成されてなるマイクロマシン（いわゆるＭＥＭＳ素子）等の種々の半導体素子が挙げられる。また、電子部品11は、圧電素子や容量素子、抵抗器等であってもよい。電子部品11は、例えば半導体素子の場合であれば、シリコン等からなる板状の本体（符号なし）に所定の電子回路（図示せず）と、電子回路と電気的に接続された複数の電極（図示せず）とを有している。   Examples of the electronic component 11 include semiconductor integrated circuit elements such as ICs and LSIs, optical semiconductor elements such as LEDs (light emitting diodes), PDs (photodiodes), and CCDs (charge coupled devices), and minute amounts on the surface of a semiconductor substrate. Various semiconductor elements such as a micromachine (so-called MEMS element) in which an electromechanical mechanism is formed may be mentioned. Further, the electronic component 11 may be a piezoelectric element, a capacitive element, a resistor, or the like. For example, in the case of a semiconductor element, the electronic component 11 is a plate-like main body (not shown) made of silicon or the like, a predetermined electronic circuit (not shown), and a plurality of electrodes electrically connected to the electronic circuit. (Not shown).

実施形態の配線基板10において、第１枠状板１は、第１主面および第１主面と反対側の
第２主面を有しているとともに中央部に上記開口部として第１開口部を有している。また、第２枠状板２は、第３主面および第３主面と反対側の第４主面を有しているとともに中央部に上記開口部として第２開口部を有している。第２開口部は、第１開口部よりも大きい。この第２枠状板２は第１枠状板１の第２主面側に積層されている。すなわち、第２枠状板２の第３主面と第１枠状板の第２主面に対向している。この場合、第１開口部よりも第２開口部の方が大きいため、この大きさの差に応じて第２枠状板２の内側で第２主面の内周部が露出している。 In the wiring board 10 of the embodiment, the first frame-like plate 1 has a first main surface and a second main surface opposite to the first main surface, and a first opening as the opening at the center. have. The second frame-like plate 2 has a third main surface and a fourth main surface opposite to the third main surface, and has a second opening as the opening at the center. The second opening is larger than the first opening. The second frame plate 2 is stacked on the second main surface side of the first frame plate 1. That is, it opposes the 3rd main surface of the 2nd frame-shaped board 2, and the 2nd main surface of the 1st frame-shaped board. In this case, since the second opening is larger than the first opening, the inner peripheral portion of the second main surface is exposed inside the second frame-like plate 2 according to the difference in size.

これらの第１枠状板１および第２枠状板２を含む絶縁基体３は、上記電子部品11の電極が電気的に接続される端子（符号なし）を有している。この端子は、第１枠状板１の第１主面に設けられた第１端子４と、第２枠状板２の内側で露出している第２主面に設けられた第２端子５とを含んでいる。   The insulating base 3 including the first frame-like plate 1 and the second frame-like plate 2 has a terminal (no symbol) to which the electrode of the electronic component 11 is electrically connected. This terminal includes a first terminal 4 provided on the first main surface of the first frame-like plate 1 and a second terminal 5 provided on the second main surface exposed inside the second frame-like plate 2. Including.

すなわち、絶縁基体３は、電子部品11が収容される上記収納用開口部の内側面に段状の部分を有し、この段状の部分を挟んだ上下に、電子部品11が電気的に接続される第１端子４および第２端子５を有している。これにより、電子部品11が上下両面に電極を有している場合であっても、それらの電極を第１および第２端子４、５に容易に電気的に接続させることができる。   In other words, the insulating base 3 has a stepped portion on the inner surface of the housing opening for accommodating the electronic component 11, and the electronic component 11 is electrically connected to the upper and lower sides of the stepped portion. The first terminal 4 and the second terminal 5 are provided. Thereby, even when the electronic component 11 has electrodes on both the upper and lower surfaces, these electrodes can be easily electrically connected to the first and second terminals 4 and 5.

実施形態の電子装置20において、配線基板10に実装される電子部品11は、第１電極12ａを有する第１電子部品12と、第２電極13ａを有する第２電子部品13とを含む積層部品（符号なし）である。第１電極12ａと第１端子４とが接続されるとともに、第２電極13ａと第２端子５とが接続されている。なお、平面視における外形の寸法は、第１電子部品12の方が第２電子部品13よりも大きく、第１電子部品12の中央部に第２電子部品13が積層されている。第１および第２電子部品12、13の上記大きさの差に応じて、電子部品11の外周側面が上記のように段状になっている。   In the electronic device 20 according to the embodiment, the electronic component 11 mounted on the wiring board 10 is a laminated component including a first electronic component 12 having a first electrode 12a and a second electronic component 13 having a second electrode 13a ( Unsigned). The first electrode 12a and the first terminal 4 are connected, and the second electrode 13a and the second terminal 5 are connected. Note that the dimensions of the outer shape in plan view are larger for the first electronic component 12 than for the second electronic component 13, and the second electronic component 13 is laminated at the center of the first electronic component 12. Depending on the difference in size between the first and second electronic components 12 and 13, the outer peripheral side surface of the electronic component 11 is stepped as described above.

このような電子部品11は、前述したように上下両面に電極を有しているものの一例である。また、電子部品11は、互いに積層された第１および第２電子部品12、13という二つの電子部品を含んでいるため、その厚みが比較的厚い。このような電子部品11であっても、第１枠状板１および第２枠状板２を含む絶縁基体３が上記のような構成であるため、絶縁基体３に対する電子部品11の実装が容易である。   Such an electronic component 11 is an example of one having electrodes on both upper and lower surfaces as described above. Further, since the electronic component 11 includes two electronic components, the first and second electronic components 12 and 13 stacked on each other, the thickness thereof is relatively large. Even in such an electronic component 11, since the insulating base 3 including the first frame-like plate 1 and the second frame-like plate 2 has the above-described configuration, the electronic component 11 can be easily mounted on the insulating base 3. It is.

電子部品11は、第１および第２電子部品12、13が互いに積層されているため、電子装置20の薄型化に対して有効である。また、電子装置20について、第１および第２電子部品12、13が互いに積層されているため、例えば二つの個片の電子部品（図示せず）が横方向に並べられて絶縁基体３に実装された電子装置（図示せず）に比べて平面視における小型化について有効である。   The electronic component 11 is effective for reducing the thickness of the electronic device 20 because the first and second electronic components 12 and 13 are laminated together. In addition, since the first and second electronic components 12 and 13 are stacked on each other in the electronic device 20, for example, two pieces of electronic components (not shown) are arranged in the horizontal direction and mounted on the insulating base 3. Compared to an electronic device (not shown), it is more effective in miniaturization in plan view.

前述したように、配線基板10は、上記構成の電子部品11の実装が容易であるため、電子装置20の薄型化および小型化を容易とすることが可能な配線基板の提供が可能になる。また、薄型化および小型化に対して有効な電子装置20を提供することができる。   As described above, since the wiring board 10 can be easily mounted with the electronic component 11 having the above configuration, it is possible to provide a wiring board capable of easily reducing the thickness and size of the electronic device 20. Further, it is possible to provide an electronic device 20 that is effective for reducing the thickness and size.

第１および第２枠状板１、２は、例えば酸化アルミニウム質焼結体、窒化アルミニウム質焼結体、ムライト質焼結体またはガラスセラミック焼結体等のセラミック焼結体によって形成されている。第１および第２枠状板１、２は、例えば酸化アルミニウム質焼結体からなる場合であれば、次のようにして製作することができる。すなわち、まず酸化アルミニウムおよび酸化ケイ素等の原料粉末を適当な有機バインダおよび有機溶剤とともにシート状に成形して四角シート状の複数のセラミックグリーンシートを作製する。次にこれらのセラミックグリーンシートを所定の外形寸法に切断するとともに、その中央部を打ち抜
いて枠状に加工する。この打ち抜き加工は、例えば金型を用いた機械的な打ち抜き加工によって行なうことができる。また、この打ち抜き時には、第１および第２開口部に応じた、打ち抜きの開口寸法が異なるような（２種類の）枠状のセラミックグリーンシートを作製する。その後、これらの枠状のセラミックグリーンシートを積層して積層体を作製する。積層時には、開口寸法がより小さいものの上に、開口寸法がより大きいものを積層する。その後、この積層体を1300〜1600℃の温度で焼成することによって絶縁基体３を製作することができる。 The first and second frame-like plates 1 and 2 are formed of a ceramic sintered body such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, or a glass ceramic sintered body. . If the first and second frame-like plates 1 and 2 are made of, for example, an aluminum oxide sintered body, they can be manufactured as follows. That is, first, raw material powders such as aluminum oxide and silicon oxide are formed into a sheet shape together with an appropriate organic binder and an organic solvent to produce a plurality of square sheet-like ceramic green sheets. Next, these ceramic green sheets are cut into predetermined outer dimensions, and the central portion thereof is punched and processed into a frame shape. This punching can be performed, for example, by mechanical punching using a mold. Further, at the time of punching, (two types) frame-shaped ceramic green sheets having different opening dimensions are prepared according to the first and second openings. Thereafter, these frame-shaped ceramic green sheets are laminated to produce a laminate. At the time of lamination, a material having a larger opening size is laminated on a material having a smaller opening size. Then, the insulating substrate 3 can be manufactured by firing this laminate at a temperature of 1300 to 1600 ° C.

第１および第２端子４、５は、例えば、タングステン、モリブデン、マンガン、銅、銀、パラジウム、金、白金、ニッケルまたはコバルト等の金属材料、またはこれらの金属材料を含む合金材料等によって形成されている。このような金属材料等は、メタライズ層またはめっき層等の金属層として第１枠状板１の第１および第２主面に設けられている。なお、この金属層は、１層でもよく、複数層でもよい。   The first and second terminals 4 and 5 are formed of, for example, a metal material such as tungsten, molybdenum, manganese, copper, silver, palladium, gold, platinum, nickel, or cobalt, or an alloy material containing these metal materials. ing. Such a metal material or the like is provided on the first and second main surfaces of the first frame-like plate 1 as a metal layer such as a metallized layer or a plating layer. The metal layer may be a single layer or a plurality of layers.

第１および第２端子４、５は、例えば、タングステンのメタライズ層である場合には、タングステンの粉末を有機溶剤および有機バインダと混合して作製した金属ペーストを絶縁基体３となるセラミックグリーンシートの所定位置にスクリーン印刷法等の方法で印刷して焼成する方法で形成することができる。また、このメタライズ層の露出表面に、電解めっき法または無電解めっき法等のめっき法でニッケルおよび金等のめっき層をさらに被着させてもよい。   For example, when the first and second terminals 4 and 5 are tungsten metallized layers, a ceramic paste made of a metal paste prepared by mixing tungsten powder with an organic solvent and an organic binder is used as the insulating base 3. It can be formed by a method of printing and baking at a predetermined position by a method such as a screen printing method. Further, a plating layer such as nickel and gold may be further deposited on the exposed surface of the metallized layer by a plating method such as an electrolytic plating method or an electroless plating method.

第１および第２端子４、５と、電子部品11の第１および第２電極12ａ、13ａとの電気的な接続は、例えばボンディングワイヤまたははんだバンプ等の導電性接続材６によって行なわれる。導電性接続材６として用いる材料は、第１および第２端子４、５と、電子部品の第１および第２電極12ａ、13ａとの位置関係、それぞれの大きさ、間隔（いわゆるピッチ等）、作業性および経済性等に応じて、適宜選定される。ボンディングワイヤは、例えばアルミニウムまたは金等の金属材料によって作製されている。はんだバンプは、例えばスズ−銀、スズ−銀−銅、スズ−銀−ビスマスまたはスズ−鉛等のはんだ材料によって作製されている。   Electrical connection between the first and second terminals 4 and 5 and the first and second electrodes 12a and 13a of the electronic component 11 is performed by a conductive connecting material 6 such as a bonding wire or a solder bump. The material used as the conductive connecting material 6 is the positional relationship between the first and second terminals 4 and 5 and the first and second electrodes 12a and 13a of the electronic component, their respective sizes, intervals (so-called pitch, etc.), It is appropriately selected according to workability and economic efficiency. The bonding wire is made of a metal material such as aluminum or gold. The solder bump is made of a solder material such as tin-silver, tin-silver-copper, tin-silver-bismuth, or tin-lead.

図１の例では、第１端子４と第１電極12ａとが互いに対向し合い、導電性接続材６であるはんだバンプを介して接続されている。第２端子５および第２電極13ａは、導電性接続材６であるボンディングワイヤによって互いに電気的に接続されている。この場合、互いに対向し合う位置に配置される第１端子４と第１電極12ａとの電気的な接続、および横方向に並び合う第２端子５と第２電極13ａとの電気的な接続が、いずれも容易である。そのため、電子装置20としての生産性等を高める上でも有利である。   In the example of FIG. 1, the first terminal 4 and the first electrode 12 a face each other and are connected via solder bumps that are conductive connection members 6. The second terminal 5 and the second electrode 13a are electrically connected to each other by a bonding wire that is the conductive connecting member 6. In this case, the electrical connection between the first terminal 4 and the first electrode 12a arranged at positions facing each other, and the electrical connection between the second terminal 5 and the second electrode 13a arranged in the lateral direction are performed. Both are easy. Therefore, it is advantageous also in improving the productivity as the electronic device 20.

なお、第１および第２端子４、５は、それぞれに接続される導電性接続材６の形態（種類）および材料等の条件に応じて適宜設定される。導電性接続材６がはんだバンプの場合であれば、第１および第２端子４、５は、例えば円形状、楕円形状、または正方形状を含む四角形状等のパターンで形成される。また、導電性接続材６がボンディングワイヤの場合であれば、第１および第２端子４、５は、例えば長方形状等の四角形状、または楕円形状等のパターンで形成される。   In addition, the 1st and 2nd terminals 4 and 5 are suitably set according to conditions, such as a form (kind) and material of the conductive connection material 6 connected to each. When the conductive connecting material 6 is a solder bump, the first and second terminals 4 and 5 are formed in a pattern such as a circular shape, an elliptical shape, or a square shape including a square shape, for example. If the conductive connecting material 6 is a bonding wire, the first and second terminals 4 and 5 are formed in a square shape such as a rectangular shape or an elliptical pattern, for example.

なお、上記第１および第２枠状板を含む絶縁基体３は、このような絶縁基体３となる複数の領域を含む母基板（図示せず）を製作した後、この母基板を上記領域毎に分割して製作することもできる。この場合には、各領域の境界に沿って、母基板を厚み方向に破断させて個片に分割するための分割溝が設けられていてもよい。   The insulating base 3 including the first and second frame-like plates is manufactured by manufacturing a mother board (not shown) including a plurality of regions to be the insulating base 3 and then, for each area. It is also possible to divide and manufacture. In this case, dividing grooves for breaking the mother substrate in the thickness direction and dividing it into individual pieces may be provided along the boundaries of the respective regions.

また、第２枠状板の第４主面は、絶縁基体３全体としての下面であり、例えばこの第４
主面が外部回路基板（図示せず）に対向するように配置されて、電子装置20と外部回路基板とが互いに電気的および機械的に接続される。この接続のため、第４主面には接続パッド７が設けられている。接続パッド７は、配線基板10および電子装置20の外部接続用の端子であり、例えば枠状の第４主面の外周に沿って複数が配列されている。接続パッド７と外部回路基板との接続は、例えば接続パッド７と外部回路基板の所定の接続部とが互いに対向し合うように配置された状態で、はんだ等の接続材を介して行なわれる。 The fourth main surface of the second frame-shaped plate is the lower surface of the insulating base 3 as a whole.
The main surface is disposed to face an external circuit board (not shown), and electronic device 20 and external circuit board are electrically and mechanically connected to each other. For this connection, a connection pad 7 is provided on the fourth main surface. The connection pads 7 are terminals for external connection of the wiring board 10 and the electronic device 20. For example, a plurality of connection pads 7 are arranged along the outer periphery of the frame-shaped fourth main surface. The connection pad 7 and the external circuit board are connected, for example, via a connecting material such as solder in a state where the connection pad 7 and a predetermined connection portion of the external circuit board are arranged to face each other.

これらの接続パッド７は、例えば絶縁基体３の内部または外表面に設けられた接続用の配線導体（図示せず）によって第１および第２端子４、５と電気的に接続されている。接続パッド７が外部回路基板の所定の接続部と電気的に接続されれば、第１および第２端子４、５と電気的に接続された電子部品11と外部回路基板との電気的な接続が行なわれる。   These connection pads 7 are electrically connected to the first and second terminals 4 and 5 by, for example, connection wiring conductors (not shown) provided on the inside or the outer surface of the insulating base 3. If the connection pad 7 is electrically connected to a predetermined connection portion of the external circuit board, the electronic component 11 electrically connected to the first and second terminals 4 and 5 and the external circuit board are electrically connected. Is done.

接続パッド７は、第１および第２端子４、５と同様の金属材料を用い、同様の方法で形成することができる。また、接続パッド７は、第１および第２端子４、５と同様に、外部回路基板に対する接続材の形態および材料等に応じて、適宜その形状および大きさ等が設定される。   The connection pad 7 can be formed by the same method using the same metal material as the first and second terminals 4 and 5. Similarly to the first and second terminals 4 and 5, the shape and size of the connection pad 7 are appropriately set according to the form and material of the connection material with respect to the external circuit board.

図２（ａ）〜（ｃ）は、それぞれ図１に示す配線基板10および電子装置20の変形例を示す断面図である。図２において図１と同様の部位には同様の符号を付している。   2A to 2C are cross-sectional views showing modifications of the wiring board 10 and the electronic device 20 shown in FIG. In FIG. 2, the same parts as those in FIG.

図２（ａ）の例では、第１枠状板１の第１主面の外周部に第３枠状板８が積層されている。第３枠状板８は、その中央部に第１開口部よりも大きい第３開口部を有している。この第３枠状板８よりも内側に第１端子４が配置されている。すなわち、より大きな第３開口部の内側で露出した、第１開口部の周囲の第１主面に第１端子４が露出して配置されている。この場合には、例えば第１電子部品12が誤って外部（搬送または加工用の各種部材等）に接する可能性がより効果的に低減される。そのため、電子装置20としての信頼性の向上についてより有利である。   In the example of FIG. 2A, the third frame plate 8 is laminated on the outer peripheral portion of the first main surface of the first frame plate 1. The 3rd frame-shaped board 8 has a 3rd opening part larger than a 1st opening part in the center part. The first terminals 4 are arranged inside the third frame-shaped plate 8. In other words, the first terminal 4 is disposed so as to be exposed on the first main surface around the first opening that is exposed inside the larger third opening. In this case, for example, the possibility that the first electronic component 12 mistakenly contacts the outside (various members for conveyance or processing) is more effectively reduced. Therefore, it is more advantageous for improving the reliability of the electronic device 20.

第３枠状板８は、第１および第２枠状板１，２と同様の材料を用い、同様の方法で作製することができる。また、第２枠状板２と同様の方法で第１枠状板１に積層することができる。   The third frame-like plate 8 can be produced by the same method using the same material as the first and second frame-like plates 1 and 2. Further, it can be laminated on the first frame-like plate 1 in the same manner as the second frame-like plate 2.

図２（ｂ）の例は、図２（ａ）に示した電子部品11を形成している第１および第２電子部品12、13の上下の位置関係が上下逆になっている。つまり、図２（ａ）の電子部品11が上下ひっくり返されて絶縁基体３に接続されている。また第１端子４と第１電極12ａとがボンディングワイヤ（導電性接続材６）によって電気的に接続されるとともに、第２端子５と第２電極13ａとがはんだバンプ（導電性接続材６）によって電気的に接続される例である。また、この例でも上記第３枠状板８が設けられている。図２（ｂ）の例では、積層部品（電子部品11）が厚み方向の全域にわたって収納用開口部内に収まっている。そのため、この場合には、低背化に対してより有利な電子装置20の提供が可能である。   In the example of FIG. 2B, the vertical positional relationship of the first and second electronic components 12 and 13 forming the electronic component 11 shown in FIG. That is, the electronic component 11 in FIG. 2A is turned upside down and connected to the insulating base 3. The first terminal 4 and the first electrode 12a are electrically connected by a bonding wire (conductive connection material 6), and the second terminal 5 and the second electrode 13a are solder bumps (conductive connection material 6). It is an example electrically connected by. Also in this example, the third frame plate 8 is provided. In the example of FIG. 2B, the laminated component (electronic component 11) is accommodated in the storage opening over the entire region in the thickness direction. Therefore, in this case, it is possible to provide the electronic device 20 that is more advantageous for reducing the height.

図２（ｃ）の例は、電子部品11について、第２電子部品13の下面にさらに第３電子部品14が積層されている。この場合には、より一層の高機能化および高集積化等が容易な電子部品11を含む、高機能化および高集積化等に対して有利な電子装置20を提供することができる。また、そのような高機能化等に有利な電子部品11の実装が容易な配線基板10を提供することができる。   In the example of FIG. 2C, the third electronic component 14 is further laminated on the lower surface of the second electronic component 13 for the electronic component 11. In this case, it is possible to provide an electronic device 20 that is advantageous for higher functionality and higher integration, including the electronic component 11 that can be easily further enhanced in functionality and integration. In addition, it is possible to provide the wiring board 10 on which the electronic component 11 that is advantageous for such high functionality can be easily mounted.

また、図２（ｃ）の例では、第２および第３電子部品13、14の両方が収納用開口部内に収まっているため、高機能化等を容易としながら、さらに低背化に対してもより有利な配線基板10および電子装置20の提供が可能である。   Further, in the example of FIG. 2C, since both the second and third electronic components 13 and 14 are accommodated in the opening for storage, it is easy to achieve high functionality while further reducing the height. In addition, it is possible to provide a more advantageous wiring board 10 and electronic device 20.

（第２の実施形態）
図３（ａ）は、本発明の第２の実施形態の配線基板10および電子装置20を示す断面図であり、図３（ｂ）は図３（ａ）の下面の一例を示す下面図である。図３において図１と同様の部位には同様の符号を付している。図３の例では、第４主面に複数の接続パッド７が設けられている。これらの接続パッド７も、例えば第１枠状板１の第１主面および第２主面から第４主面にかけて設けられた接続用の配線導体を介して第１端子４または第２端子５とそれぞれに電気的に接続されている。 (Second Embodiment)
FIG. 3A is a cross-sectional view showing the wiring board 10 and the electronic device 20 according to the second embodiment of the present invention, and FIG. 3B is a bottom view showing an example of the bottom surface of FIG. is there. In FIG. 3, the same parts as those in FIG. In the example of FIG. 3, a plurality of connection pads 7 are provided on the fourth main surface. These connection pads 7 are also connected to the first terminal 4 or the second terminal 5 via connection wiring conductors provided from the first main surface and the second main surface to the fourth main surface of the first frame-like plate 1, for example. Are electrically connected to each other.

また、この例における複数の接続パッド７は、第４主面の外周および内周に、二列に配列されている。これにより、第１および第２電子部品12、13を含み、外部に接続される電極（第１および第２電極12ａ、13ａ）の数に対応させて、多数の接続パッド７を第４主面に配置させることが容易になっている。すなわち、この場合には、高機能化および高機能化に応じた外部接続等を容易としながら、さらに低背化に対してもより有利な配線基板10および電子装置20の提供が可能である。   The plurality of connection pads 7 in this example are arranged in two rows on the outer periphery and the inner periphery of the fourth main surface. Accordingly, the number of connection pads 7 including the first and second electronic components 12 and 13 and the number of connection pads 7 corresponding to the number of externally connected electrodes (first and second electrodes 12a and 13a) is changed to the fourth main surface. It is easy to arrange them. That is, in this case, it is possible to provide the wiring board 10 and the electronic device 20 that are more advantageous for lowering the height while facilitating external connection and the like according to higher functionality and higher functionality.

なお、複数の接続パッド７は、枠状の第４主面の外周部および内周部に沿って配列されていれば、すなわち、その位置がわかりやすいように規則的に配列されていれば、配線基板10および電子装置20としての外部接続が容易であり、接続信頼性の向上もより容易である。   If the plurality of connection pads 7 are arranged along the outer peripheral portion and the inner peripheral portion of the frame-shaped fourth main surface, that is, if they are regularly arranged so that the positions thereof are easily understood, External connection as the substrate 10 and the electronic device 20 is easy, and connection reliability can be improved more easily.

ただし、複数の接続パッド７は、必ずしも枠状の第４主面の外周部および内周部に沿って配列されているものである必要はなく、例えば、第４主面の幅、接続パッド７の第１端子４または第２端子５との配線導体による接続の容易さ、または接続パッド７の形状等に応じて、適宜、異なった規則で配列されている部分、または不規則に配置された部分等を含んでいてもよい。   However, the plurality of connection pads 7 do not necessarily have to be arranged along the outer peripheral portion and the inner peripheral portion of the frame-shaped fourth main surface. For example, the width of the fourth main surface, the connection pad 7 Depending on the ease of connection to the first terminal 4 or the second terminal 5 by the wiring conductor, the shape of the connection pad 7 or the like, portions arranged in different rules or irregularly arranged as appropriate A part etc. may be included.

なお、第１枠状板１および第２枠状板２は、それぞれの厚さを合わせた合計の厚さが、積層部品である電子部品11の厚さ以上である場合には、例えば図２（ｂ）の例のように電子部品11の全体を収納用開口部内に収めることができる。これにより、電子部品11の全体を絶縁基体３によって保護することができる。そのため、低背化および小型化を容易としながら、信頼性の向上についてもより有利な電子装置20、およびそのような電子装置20の製作が容易な配線基板10を提供することができる。   When the total thickness of the first frame-like plate 1 and the second frame-like plate 2 is equal to or greater than the thickness of the electronic component 11 that is a laminated component, for example, FIG. As in the example of (b), the entire electronic component 11 can be stored in the storage opening. As a result, the entire electronic component 11 can be protected by the insulating base 3. Therefore, it is possible to provide an electronic device 20 that is more advantageous in terms of improving reliability while facilitating a reduction in height and size, and a wiring board 10 in which such an electronic device 20 can be easily manufactured.

前述したように、実施形態の配線基板に電子部品11が実装されて電子装置20が作製されている。この電子装置20は、例えば上記各例のように、平面透視において第２電子部品13が第１開口内に位置している。また、この電子装置20において、第１電極12ａの少なくとも一部が第１開口よりも外側に位置しており、第１端子４と第１電極12ａとが互いに対向し合って接続されている。この接続は、導電性接続材６としてはんだバンプが使用されたものであり、いわゆるフリップチップ実装である。また、第２端子５と第２電極13ａとが導電性接続材６としてボンディングワイヤを介して接続されている。電子部品11に含まれる第１および第２電子部品12、13のそれぞれの電極（第１電極12ａ、第２電極13ａ）が、互いに異なる接続の形態で、第１端子４または第２端子５に接続されているため、低背化に適した形態の電子装置20とすることがより容易である。また、導電性接続材６であるボンディングワイヤの全体が第４主面よりも第３主面側に位置している。これによって導電性接続材６の全体が第２枠状板で保護されている。そのため、例えば誤ってボンディングワイヤが切れるような可能性が低減された、より信頼性の高い電子装置20が形成されている。   As described above, the electronic device 11 is manufactured by mounting the electronic component 11 on the wiring board of the embodiment. In the electronic device 20, for example, as in the above examples, the second electronic component 13 is located in the first opening in plan perspective. In the electronic device 20, at least a part of the first electrode 12a is positioned outside the first opening, and the first terminal 4 and the first electrode 12a are connected to face each other. This connection uses solder bumps as the conductive connection material 6 and is so-called flip chip mounting. Further, the second terminal 5 and the second electrode 13a are connected as a conductive connecting material 6 via a bonding wire. The respective electrodes (first electrode 12a and second electrode 13a) of the first and second electronic components 12 and 13 included in the electronic component 11 are connected to the first terminal 4 or the second terminal 5 in a different connection form. Since it is connected, it is easier to form the electronic device 20 in a form suitable for reducing the height. Further, the entire bonding wire which is the conductive connecting material 6 is located on the third main surface side with respect to the fourth main surface. As a result, the entire conductive connecting member 6 is protected by the second frame plate. Therefore, for example, a more reliable electronic device 20 is formed in which the possibility that the bonding wire is accidentally cut is reduced.

なお、図３の例では、第２枠状板２について、第４主面と外側面との間の角部分が平面
上に面取りされ、この面取りされた部分まで接続パッド７が設けられている。この場合には、例えば下面視における絶縁基体３の大きさがより大きくなることを抑制しながら、接続パッド７の表面の面積をより大きくすることができる。また、これらの接続パッド７が外部回路基板にはんだ等の接続材を介して接続されたときに、その接続材の外周部に効果的にフィレットを形成することもできる。そのため、小型化を図りながら、高機能化および外部接続の信頼性の向上においても有効な配線基板10および電子装置20を提供することができる。 In the example of FIG. 3, the corner portion between the fourth main surface and the outer surface of the second frame-like plate 2 is chamfered on a plane, and the connection pads 7 are provided up to the chamfered portion. . In this case, for example, the area of the surface of the connection pad 7 can be increased while suppressing an increase in the size of the insulating base 3 in a bottom view. Further, when these connection pads 7 are connected to an external circuit board via a connection material such as solder, a fillet can be effectively formed on the outer peripheral portion of the connection material. Therefore, it is possible to provide the wiring board 10 and the electronic device 20 that are effective in improving functionality and improving the reliability of external connection while achieving downsizing.

（第３の実施形態）
図４は、本発明の第３の実施形態の電子装置20を示す断面図である。図４において図１と同様の部位には同様の符号を付している。図４の例では、第１電子部品12の第１電極12ａが、第１電子部品12の本体（符号なし）に横方向に突出して接合されたリード端子12ｂを含んでいる。このリード端子12ｂの端部が第１端子４と対向して接続されている。リード端子12ｂと第１端子４との接続も、はんだ等の導電性の接続材（図示せず）を介して行なうことができる。 (Third embodiment)
FIG. 4 is a sectional view showing an electronic device 20 according to the third embodiment of the present invention. 4, parts similar to those in FIG. 1 are denoted by the same reference numerals. In the example of FIG. 4, the first electrode 12 a of the first electronic component 12 includes a lead terminal 12 b that protrudes in the lateral direction and is joined to the main body (not indicated) of the first electronic component 12. The end of the lead terminal 12b is connected to face the first terminal 4. The lead terminal 12b and the first terminal 4 can also be connected via a conductive connecting material (not shown) such as solder.

図４の例では、リード端子12ｂの変形等によって、電子部品11と絶縁基体３との熱膨張係数の差に起因した熱応力を緩和することも容易である。そのため、電子部品11の第１端子４等に対する電気的な接続の信頼性の向上についてより有利な電子装置20を提供することができる。   In the example of FIG. 4, it is easy to relieve the thermal stress caused by the difference in thermal expansion coefficient between the electronic component 11 and the insulating base 3 due to deformation of the lead terminal 12b or the like. Therefore, it is possible to provide an electronic device 20 that is more advantageous for improving the reliability of electrical connection to the first terminal 4 of the electronic component 11 and the like.

リード端子12ｂは、例えば鉄−ニッケル合金、鉄−コバルト−ニッケル合金、銅、銅を主成分とする合金、アルミニウムまたはアルミニウムを主成分とする合金等の金属材料からなり、これらの金属材料に機械的な切断、またはエッチング等の加工が施されて作製されている。   The lead terminal 12b is made of a metal material such as an iron-nickel alloy, an iron-cobalt-nickel alloy, copper, an alloy containing copper as a main component, aluminum, or an alloy containing aluminum as a main component. It is manufactured by performing a process such as a general cutting or etching.

図５は、本発明の実施形態の積層型電子装置30を示す断面図である。図５において図１と同様の部位には同様の符号を付している。このような積層型電子装置30は、例えば上記構成の複数の電子装置20が、互いに上下に積層されて作製されている。   FIG. 5 is a cross-sectional view showing the multilayer electronic device 30 according to the embodiment of the present invention. 5, parts similar to those in FIG. 1 are denoted by the same reference numerals. Such a multilayer electronic device 30 is produced, for example, by stacking a plurality of electronic devices 20 having the above-described configuration one above the other.

このような積層型電子装置30は、例えば外部回路基板に対する個々の電子部品（第１および第２電子部品12、13等）の実装密度を向上させることがより容易である。   In such a stacked electronic device 30, it is easier to improve the mounting density of individual electronic components (first and second electronic components 12, 13, etc.) on an external circuit board, for example.

なお、図５の例では、図１および図４に示された電子装置20（二つの電子装置20）が下から順次積層された積層型電子装置の例が示されているが、他の形態の電子装置が積層されていてもよい。また、三つ以上の電子装置が積層されてなるもの（図示せず）でもよい。   The example of FIG. 5 shows an example of a stacked electronic device in which the electronic devices 20 (two electronic devices 20) shown in FIGS. 1 and 4 are sequentially stacked from the bottom. These electronic devices may be stacked. Alternatively, a structure in which three or more electronic devices are stacked (not shown) may be used.

また、複数の電子装置20のそれぞれの絶縁基体３および第１、第２端子４、５がまとめて、例えば一体的な同時焼成によって作製されていてもよい。この場合、複数の絶縁基体３等が作製された後、順次複数の個々の電子部品（第１および第２電子部品12、13等）が実装されて、積層型電子装置30が製作される。   Further, the insulating base 3 and the first and second terminals 4 and 5 of each of the plurality of electronic devices 20 may be collectively manufactured, for example, by integral simultaneous firing. In this case, after the plurality of insulating bases 3 and the like are manufactured, a plurality of individual electronic components (first and second electronic components 12 and 13 and the like) are sequentially mounted, and the stacked electronic device 30 is manufactured.

１・・・第１枠状板
２・・・第２枠状板
３・・・絶縁基体
４・・・第１端子
５・・・第２端子
６・・・導電性接続材
７・・・接続パッド
８・・・第３枠状板
10・・・配線基板
11・・・電子部品（積層部品）
12・・・第１電子部品
12ａ・・・第１電極
12ｂ・・・リード端子
13・・・第２電子部品
13ａ・・・第２電極
20・・・電子装置
30・・・積層型電子装置
DESCRIPTION OF SYMBOLS 1 ... 1st frame-shaped board 2 ... 2nd frame-shaped board 3 ... Insulation base | substrate 4 ... 1st terminal 5 ... 2nd terminal 6 ... Conductive connection material 7 ... Connection pad 8 ... 3rd frame plate
10 ... wiring board
11 ... Electronic components (laminated components)
12 ... 1st electronic component
12a ... 1st electrode
12b ... Lead terminal
13 ... Second electronic component
13a ... second electrode
20 ... Electronic device
30 ... Stacked electronic devices

Claims (9)

複数の電子部品を含む積層部品が実装される配線基板であって、
第１主面および該第１主面と反対側の第２主面を有しているとともに中央部に第１開口部を有する第１枠状板と、
該第１枠状板の前記第２主面側に積層されており、前記第２主面に対向している第３主面と該第３主面と反対側の第４主面を有しているとともに、中央部に前記第１開口部よりも大きい第２開口部を有する第２枠状板と、
前記第１主面に設けられた第１端子と、
前記第２枠状板の内側で露出している前記第２主面に設けられた第２端子とを備えており、
前記第１端子および前記第２端子に対して、前記複数の電子部品がそれぞれ接続されることを特徴とする配線基板。 A wiring board on which a multilayer component including a plurality of electronic components is mounted,
A first frame-shaped plate having a first main surface and a second main surface opposite to the first main surface and having a first opening in the center;
The first frame-shaped plate is laminated on the second main surface side, and has a third main surface facing the second main surface and a fourth main surface opposite to the third main surface. And a second frame-like plate having a second opening larger than the first opening at the center,
A first terminal provided on the first main surface;
A second terminal provided on the second main surface exposed inside the second frame-shaped plate,
The wiring board, wherein the plurality of electronic components are connected to the first terminal and the second terminal, respectively. 前記第１端子および前記第２端子と電気的に接続された複数の接続パッドが、前記第４主面に複数の列状に配列されていることを特徴とする請求項１記載の配線基板。 The wiring board according to claim 1, wherein a plurality of connection pads electrically connected to the first terminal and the second terminal are arranged in a plurality of rows on the fourth main surface. 前記複数の接続パッドが、枠状の前記第４主面の外周部および内周部に沿って配列されていることを特徴とする請求項２記載の配線基板。 The wiring board according to claim 2, wherein the plurality of connection pads are arranged along an outer peripheral portion and an inner peripheral portion of the frame-shaped fourth main surface. 中央部に前記第１開口部よりも大きい第３開口部を有しているとともに、前記第１枠状板の前記第１主面側に積層された第３枠状板をさらに備えており、
該第３枠状板よりも内側に前記第１端子が配置されていることを特徴とする請求項１〜請求項３のいずれかに記載の配線基板。 A third opening having a third opening larger than the first opening at the center, and a third frame-like plate laminated on the first main surface side of the first frame-like plate;
The wiring board according to claim 1, wherein the first terminal is disposed inside the third frame-like plate. 請求項１〜請求項４のいずれかに記載の配線基板と、
第１電極を有する第１電子部品と第２電極を有する第２電子部品とが互いに積層されてなる積層部品とを備えており、
前記第１および前記第２端子に対して、前記第１電極および前記第２電極がそれぞれ接続されていることを特徴とする電子装置。 The wiring board according to any one of claims 1 to 4,
A first electronic component having a first electrode and a second electronic component having a second electrode are laminated to each other;
The electronic device, wherein the first electrode and the second electrode are connected to the first and second terminals, respectively. 前記第１端子と前記第１電極とが互いに対向し合って接続されているとともに、前記第２端子と前記第２電極とが導電性接続材を介して接続されており、該導電性接続材の全体が前記第４主面よりも前記第３主面側に位置していることを特徴とする請求項５記載の電子装置。 The first terminal and the first electrode are connected to face each other, and the second terminal and the second electrode are connected via a conductive connecting material, and the conductive connecting material 6. The electronic device according to claim 5, wherein the entirety of the electronic device is located closer to the third main surface than the fourth main surface. 前記第１電子部品の前記第１電極が、前記第１電子部品の本体に横方向に突出して接合されたリード端子を含んでおり、該リード端子の端部が前記第１端子と対向して接続されていることを特徴とする請求項５または請求項６記載の電子装置。 The first electrode of the first electronic component includes a lead terminal that protrudes and is joined to the main body of the first electronic component in a lateral direction, and an end portion of the lead terminal faces the first terminal. The electronic device according to claim 5, wherein the electronic device is connected. 前記第１枠状板と前記第２枠状板とを合わせた厚さが、前記積層部品の厚さ以上であることを特徴とする請求項５〜請求項７のいずれかに記載の電子装置。 8. The electronic device according to claim 5, wherein a total thickness of the first frame-shaped plate and the second frame-shaped plate is equal to or greater than a thickness of the laminated component. 9. . 請求項５〜請求項７のいずれかに記載の複数の電子装置が、互いに上下に積層されてなることを特徴とする積層型電子装置。
8. A stacked electronic device comprising a plurality of electronic devices according to claim 5 stacked one above the other.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112017000469T5 (en) 2016-01-21 2018-09-27 Futaba Industrial Co., Ltd. silencer
US11261768B2 (en) 2018-01-26 2022-03-01 Futaba Industrial Co., Ltd. Muffler

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5867057A (en) * 1981-10-16 1983-04-21 Nec Corp Semiconductor device
JPH09107067A (en) * 1995-10-09 1997-04-22 Hitachi Ltd Semiconductor device
JPH09162216A (en) * 1995-12-09 1997-06-20 Sony Corp Semiconductor device
JPH1167963A (en) * 1997-08-26 1999-03-09 Matsushita Electric Works Ltd Semiconductor device
JP2002076183A (en) * 2000-08-30 2002-03-15 Kyocera Corp Semiconductor element storing package
JP2005274219A (en) * 2004-03-23 2005-10-06 Matsushita Electric Works Ltd Semiconductor acceleration sensor device and its manufacturing method
JP2006165333A (en) * 2004-12-08 2006-06-22 Sony Corp Device and method for mounting semiconductor element
JP2007305740A (en) * 2006-04-10 2007-11-22 Murata Mfg Co Ltd Ceramic multilayer board, and its manufacturing method
US20080111248A1 (en) * 2004-12-14 2008-05-15 Chee Seng Foong Flip Chip And Wire Bond Semiconductor Package

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5867057A (en) * 1981-10-16 1983-04-21 Nec Corp Semiconductor device
JPH09107067A (en) * 1995-10-09 1997-04-22 Hitachi Ltd Semiconductor device
JPH09162216A (en) * 1995-12-09 1997-06-20 Sony Corp Semiconductor device
JPH1167963A (en) * 1997-08-26 1999-03-09 Matsushita Electric Works Ltd Semiconductor device
JP2002076183A (en) * 2000-08-30 2002-03-15 Kyocera Corp Semiconductor element storing package
JP2005274219A (en) * 2004-03-23 2005-10-06 Matsushita Electric Works Ltd Semiconductor acceleration sensor device and its manufacturing method
JP2006165333A (en) * 2004-12-08 2006-06-22 Sony Corp Device and method for mounting semiconductor element
US20080111248A1 (en) * 2004-12-14 2008-05-15 Chee Seng Foong Flip Chip And Wire Bond Semiconductor Package
JP2007305740A (en) * 2006-04-10 2007-11-22 Murata Mfg Co Ltd Ceramic multilayer board, and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112017000469T5 (en) 2016-01-21 2018-09-27 Futaba Industrial Co., Ltd. silencer
US11261768B2 (en) 2018-01-26 2022-03-01 Futaba Industrial Co., Ltd. Muffler

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