JP2000261152A - Printed wiring board assembly - Google Patents
Printed wiring board assemblyInfo
- Publication number
- JP2000261152A JP2000261152A JP11064686A JP6468699A JP2000261152A JP 2000261152 A JP2000261152 A JP 2000261152A JP 11064686 A JP11064686 A JP 11064686A JP 6468699 A JP6468699 A JP 6468699A JP 2000261152 A JP2000261152 A JP 2000261152A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor element
- printed wiring
- wiring assembly
- core substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プリント配線組立
体に関し、特に、プリント基板に半導体素子を内蔵する
ことにより高密度実装を可能にするプリント配線組立体
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring assembly, and more particularly, to a printed wiring assembly which enables high-density mounting by incorporating a semiconductor element in a printed circuit board.
【０００２】[0002]
【従来の技術】図９は、半導体素子を内蔵した従来のプ
リント配線組立体の断面図である。同図において、予め
段彫り加工が施されたプリント基板１上に接着剤で半導
体素子２が固定されている。半導体素子２は、その接続
端子つまり電極２ａ，２ｂが基板１のパッド１ａ，１ｂ
に対してワイヤボンディング４で接続されており、か
つ、モールド樹脂の絶縁層５によって全体が覆われてい
る。2. Description of the Related Art FIG. 9 is a sectional view of a conventional printed wiring assembly incorporating a semiconductor element. In the figure, a semiconductor element 2 is fixed with an adhesive on a printed circuit board 1 which has been subjected to a step carving process in advance. The semiconductor element 2 has its connection terminals, ie, the electrodes 2a and 2b,
Are connected by wire bonding 4 and are entirely covered with an insulating layer 5 of a mold resin.
【０００３】特開平５−２９５３３号公報には、半導体
素子の実装密度を高めるため、半導体素子を覆う絶縁層
の上にさらに配線層（基板）を配置して半導体素子を搭
載し、各配線層間を貫通孔によって接続した積層モジュ
ールが開示されている。Japanese Patent Application Laid-Open No. 5-29533 discloses that in order to increase the mounting density of a semiconductor element, a wiring layer (substrate) is further disposed on an insulating layer covering the semiconductor element, and the semiconductor element is mounted. Are connected by a through hole.
【０００４】[0004]
【発明が解決しようとする課題】上記従来のプリント配
線組立体を積層して実装密度を高めようとした場合、絶
縁層５の表面を平滑にする必要があり、そのためには、
高い精度でプリント基板の段彫り加工をしなければなら
ない。また、ワイヤボンディングを使用した場合には、
プリント基板の表面層にしか半導体素子を配置できない
ため、積層構造を取りにくいし、占有空間が大きくなる
ため実装密度を高めることができない。特に、近年は半
導体素子の電極数の増加傾向が著しいことから、電極ピ
ッチは極小化しており、ワイヤボンディングによる接続
も困難になってきている。In order to increase the mounting density by stacking the above-mentioned conventional printed wiring assemblies, it is necessary to smooth the surface of the insulating layer 5, and for that purpose,
The printed circuit board must be carved with high precision. Also, when using wire bonding,
Since the semiconductor element can be arranged only on the surface layer of the printed circuit board, it is difficult to form a laminated structure, and the occupied space becomes large, so that the mounting density cannot be increased. In particular, in recent years, the number of electrodes of a semiconductor element has been increasing remarkably, so that the electrode pitch has been minimized, and connection by wire bonding has become difficult.
【０００５】本発明は、上述の問題点を解消し、半導体
素子の高密度実装が可能なプリント配線組立体を提供す
ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a printed wiring assembly capable of mounting semiconductor elements at high density.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、コア基材と、前記コア基材に積層された
絶縁層と、前記コア基材および前記絶縁層間に内蔵され
た半導体素子と、前記絶縁層上に形成された配線パター
ンとを具備し、前記半導体素子に形成された接続端子お
よび前記絶縁層上の配線パターンを接続するために導電
性の接続孔を形成した点に第１の特徴があり、前記接続
孔がレーザまたはエッチングによる穿孔工程と、前記穿
孔行程で形成された孔内壁のメッキ工程とによって形成
された点に第２の特徴がある。In order to achieve the above object, the present invention provides a core substrate, an insulating layer laminated on the core substrate, and a semiconductor embedded between the core substrate and the insulating layer. Device, comprising a wiring pattern formed on the insulating layer, and having a conductive connection hole for connecting a connection terminal formed on the semiconductor device and a wiring pattern on the insulating layer. There is a first characteristic, and a second characteristic is that the connection hole is formed by a drilling step by laser or etching and a plating step of an inner wall of the hole formed in the drilling step.
【０００７】また、本発明は、絶縁層の上にさらに絶縁
層を積層し、両絶縁層間に半導体素子を内蔵した点に第
３の特徴があり、前記コア基材または絶縁層の表層にバ
ンプ電極を配置した点に第４の特徴がある。さらに、本
発明は、前記半導体素子に当接させて配置した熱伝導性
部材にヒートシンクを接続した点に第５の特徴がある。Further, the present invention has a third feature in that an insulating layer is further laminated on the insulating layer and a semiconductor element is built in between the two insulating layers, and a bump is formed on the surface of the core base material or the insulating layer. There is a fourth feature in that the electrodes are arranged. Further, the present invention has a fifth feature in that a heat sink is connected to a heat conductive member arranged in contact with the semiconductor element.
【０００８】上記第１〜第２の特徴によれば、絶縁層に
覆われた半導体素子と絶縁層に形成された配線パターン
とが接続孔を通じて接続される。また、第３の特徴によ
れば複数の半導体素子を層状に高密度に実装可能であ
る。また、第４の特徴によれば、バンプ電極を通じて他
のプリント配線組立体等に接続することができる。さら
に、第５の特徴によれば当該プリント配線組立体にヒー
トシンクを保持して半導体素子の温度上昇を防止するこ
とができる。According to the first and second features, the semiconductor element covered with the insulating layer is connected to the wiring pattern formed on the insulating layer through the connection hole. Further, according to the third feature, it is possible to mount a plurality of semiconductor elements in a layer at a high density. Further, according to the fourth feature, it is possible to connect to another printed wiring assembly or the like through the bump electrode. Further, according to the fifth feature, it is possible to prevent a temperature rise of the semiconductor element by holding a heat sink in the printed wiring assembly.
【０００９】[0009]
【発明の実施の形態】以下、図面を参照して本発明を説
明する。以下の説明では同一または同等部分は同符号を
もって示す。図１は、本発明の一実施形態に係るプリン
ト配線組立体の断面図である。同図において、プリント
基板のコア基材６には半導体素子７が実装され、コア基
材６および半導体素子７の上には絶縁層８が積層されて
いる。絶縁層８の上には配線パターン９が形成されてい
て、半導体素子７上に設けられた接続端子つまり電極７
ａ，７ｂは接続孔１０を介して配線パターン９に接続さ
れている。なお、配線パターン９は半導体素子７だけで
なく、接続孔１１を介してコア基材６やその下層の基材
１２の配線パターン１３にも接続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. In the following description, the same or equivalent parts are denoted by the same reference numerals. FIG. 1 is a sectional view of a printed wiring assembly according to one embodiment of the present invention. In the figure, a semiconductor element 7 is mounted on a core base 6 of a printed circuit board, and an insulating layer 8 is laminated on the core base 6 and the semiconductor element 7. A wiring pattern 9 is formed on the insulating layer 8, and a connection terminal, that is, an electrode 7 provided on the semiconductor element 7 is provided.
a and 7b are connected to the wiring pattern 9 via the connection holes 10. The wiring pattern 9 is connected not only to the semiconductor element 7 but also to the wiring pattern 13 of the core base material 6 and the base material 12 therebelow via the connection holes 11.
【００１０】次に、前記プリント配線組立体の製造プロ
セスを説明する。図２は製造プロセスを示す図である。
まず、同図（ａ）において、コア基材６の上に接着剤で
半導体素子７を固定する。このとき、半導体素子７は、
その電極（図１参照）が表側（図中上側）になるように
配置される。コア基材６の両面には配線パターン１４が
形成され、これらの配線パターン１４は予めメッキを施
した接続孔１１Ａによって接続されている。Next, a manufacturing process of the printed wiring assembly will be described. FIG. 2 is a diagram showing a manufacturing process.
First, in FIG. 1A, a semiconductor element 7 is fixed on a core base material 6 with an adhesive. At this time, the semiconductor element 7
The electrodes (see FIG. 1) are arranged such that the electrodes are on the front side (upper side in the figure). Wiring patterns 14 are formed on both surfaces of the core base material 6, and these wiring patterns 14 are connected by connection holes 11A that have been plated in advance.
【００１１】半導体素子７を固定したならば絶縁層８を
形成する（図２（ｂ））。絶縁層８の形成方法は図３等
に関して後述する。さらに、絶縁層８上部と半導体素子
７の電極や配線パターン１４をつなぐ接続孔１０，１１
を、レーザ加工またはフォトエッチング等によって形成
する（図２（ｃ））。最後に、配線パターン９が配置さ
れる部分を除いて絶縁層８の表面にレジストを印刷した
後、電子回路としての配線パターン９をメッキ処理によ
って形成する（図２（ｄ））。このメッキ処理により接
続孔１０，１１も同時にメッキされ、配線パターン９と
半導体素子７の電極、ならびに配線パターン９と他の配
線パターン１４とが接続される。After fixing the semiconductor element 7, an insulating layer 8 is formed (FIG. 2B). The method for forming the insulating layer 8 will be described later with reference to FIG. Further, connection holes 10 and 11 for connecting the upper part of the insulating layer 8 to the electrodes and the wiring patterns 14 of the semiconductor element 7.
Is formed by laser processing or photoetching (FIG. 2C). Finally, after a resist is printed on the surface of the insulating layer 8 except for the portion where the wiring pattern 9 is arranged, the wiring pattern 9 as an electronic circuit is formed by plating (FIG. 2D). By this plating process, the connection holes 10 and 11 are also plated at the same time, and the wiring pattern 9 and the electrodes of the semiconductor element 7 and the wiring pattern 9 and the other wiring patterns 14 are connected.
【００１２】次に、図３〜図５を参照して前記絶縁層８
の形成方法を説明する。第１の方法を図３に示す。この
方法では、半導体素子７の外形に適合した凹部１５を有
する絶縁材８ａを、接着剤１６を使ってコア基材６の表
面に貼り付ける。この絶縁材８ａが絶縁層８となる。こ
こで、半導体素子７と絶縁材８ａとの隙間を埋めるよう
に樹脂１７を介在させておくのが好ましい。Next, referring to FIG. 3 to FIG.
The method for forming the film will be described. The first method is shown in FIG. In this method, an insulating material 8 a having a concave portion 15 conforming to the outer shape of the semiconductor element 7 is attached to the surface of the core base material 6 using an adhesive 16. This insulating material 8a becomes the insulating layer 8. Here, it is preferable that the resin 17 is interposed so as to fill the gap between the semiconductor element 7 and the insulating material 8a.
【００１３】第２の方法を図４に示す。この方法では絶
縁性の樹脂８ｂをコア基材６および半導体素子７の上に
塗布する。この樹脂８ｂが固着して絶縁層８となる。な
お、印刷材料としての樹脂８ｂはスキージ２４を矢印２
５の方向に移動させることで塗布される。FIG. 4 shows a second method. In this method, an insulating resin 8b is applied on the core substrate 6 and the semiconductor element 7. The resin 8b is fixed to form the insulating layer 8. The squeegee 24 is indicated by an arrow 2 on the resin 8b as a printing material.
It is applied by moving in the direction of 5.
【００１４】第３の方法を図５に示す。この方法では軟
性の絶縁シート８ｃを、接着剤１６を使ってコア基材６
の表面に貼り付ける。この絶縁材８ｃが絶縁層８とな
る。特に、半導体素子７として薄型のもの（０．４ｍｍ
以下のもの）を使用した場合に、この軟性の絶縁シート
８ｃは好適に適用できる。FIG. 5 shows a third method. In this method, the soft insulating sheet 8c is bonded to the core substrate 6 using an adhesive 16.
Paste on the surface of. This insulating material 8c becomes the insulating layer 8. In particular, a thin semiconductor device 7 (0.4 mm
When the following is used, the soft insulating sheet 8c can be suitably applied.
【００１５】続いて、本発明の他の実施形態を説明す
る。図６は、半導体素子をコア基材の両面に配置した例
を示す断面図である。コア基材６０の両面に半導体素子
７０，７１を接着にて固定し、それぞれの半導体素子７
０，７１の上に絶縁層８０，８１をそれぞれ配置してい
る。Next, another embodiment of the present invention will be described. FIG. 6 is a cross-sectional view showing an example in which semiconductor elements are arranged on both surfaces of a core base material. The semiconductor elements 70 and 71 are fixed to both surfaces of the core substrate 60 by bonding, and the respective semiconductor elements 7
Insulating layers 80 and 81 are arranged on 0 and 71, respectively.
【００１６】図７は、半導体素子をさらに増やした配置
例を示す断面図である。図７において、コア基材６０の
両面に半導体素子７０，７１を接着にて固定し、それぞ
れの半導体素子７０，７１の上に絶縁層８０，８１を配
置する。さらに、絶縁層８１の上に半導体素子７２を接
着・固定し、その上を絶縁層８２で覆う。そして、さら
に絶縁層８２の上に半導体素子７３，７４を接着・固定
している。また、絶縁層８０の下面、つまり該プリント
配線組立体の最下層には、他のプリント配線組立体等と
の接続用にバンプ１８が形成されてる。各半導体素子７
０，７１，７２，７３，７４間ならびにこれらとバンプ
１８間は接続孔１９や配線パターン２０で接続されてい
る。なお、バンプ１８はこのような多数の半導体素子を
層状に配置したものに限らず、図１や図６のものにも同
様に形成することができる。FIG. 7 is a sectional view showing an arrangement example in which the number of semiconductor elements is further increased. In FIG. 7, semiconductor elements 70 and 71 are fixed to both surfaces of a core base material 60 by bonding, and insulating layers 80 and 81 are arranged on the respective semiconductor elements 70 and 71. Further, a semiconductor element 72 is bonded and fixed on the insulating layer 81, and the semiconductor element 72 is covered with the insulating layer 82. The semiconductor elements 73 and 74 are further adhered and fixed on the insulating layer 82. On the lower surface of the insulating layer 80, that is, on the lowermost layer of the printed wiring assembly, bumps 18 are formed for connection with another printed wiring assembly and the like. Each semiconductor element 7
The connection holes 19 and the wiring patterns 20 connect between 0, 71, 72, 73, 74 and between these and the bumps 18. The bumps 18 are not limited to those having a large number of semiconductor elements arranged in layers, but may be formed in the same manner as those shown in FIGS.
【００１７】図８は、図６のものにおいて、ヒートシン
クを設けた例を示す断面図である。同図において、半導
体素子７１とコア基材６０との間に、アルミニウム等の
熱伝導率の高い材料からなるプレート２１を設け、この
プレート２１から垂直にポスト２２を立ち上げ、さらに
ポスト２２にヒートシンク２３を接続している。FIG. 8 is a sectional view showing an example in which a heat sink is provided in FIG. In the figure, a plate 21 made of a material having high thermal conductivity such as aluminum is provided between a semiconductor element 71 and a core base material 60, a post 22 is vertically set up from the plate 21, and a heat sink is mounted on the post 22. 23 are connected.
【００１８】[0018]
【発明の効果】以上の説明から明らかなように、請求項
１〜請求項５の発明によれば、接続孔を通じて半導体素
子と配線パターンとを接続できるのでプリント配線組立
体内に半導体素子を高密度に配置することができる。特
に、請求項３の発明によれば、多層構造により一層高密
度な配置が可能であり、請求項４の発明によれば、バン
プ電極により他のプリント配線組立体との接続も容易で
ある。As is apparent from the above description, according to the first to fifth aspects of the present invention, the semiconductor element and the wiring pattern can be connected through the connection hole, so that the semiconductor element can be mounted in the printed wiring assembly at a high density. Can be arranged. In particular, according to the third aspect of the present invention, a higher density arrangement can be achieved by the multilayer structure, and according to the fourth aspect of the present invention, connection with other printed wiring assemblies by bump electrodes is easy.
【図１】 本発明の第１の実施形態に係るプリント配線
組立体の要部断面図である。FIG. 1 is a cross-sectional view of a main part of a printed wiring assembly according to a first embodiment of the present invention.
【図２】 本発明の第１の実施形態に係るプリント配線
組立体の製造工程の説明図である。FIG. 2 is an explanatory diagram of a manufacturing process of the printed wiring assembly according to the first embodiment of the present invention.
【図３】 絶縁層の形成方法の第１の例を示す断面図で
ある。FIG. 3 is a cross-sectional view illustrating a first example of a method for forming an insulating layer.
【図４】 絶縁層の形成方法の第２の例を示す断面図で
ある。FIG. 4 is a cross-sectional view illustrating a second example of a method for forming an insulating layer.
【図５】 絶縁層の形成方法の第３の例を示す断面図で
ある。FIG. 5 is a cross-sectional view illustrating a third example of a method for forming an insulating layer.
【図６】 本発明の第２の実施形態に係るプリント配線
組立体の要部断面図である。FIG. 6 is a sectional view of a main part of a printed wiring assembly according to a second embodiment of the present invention.
【図７】 本発明の第３の実施形態に係るプリント配線
組立体の要部断面図である。FIG. 7 is a sectional view of a principal part of a printed wiring assembly according to a third embodiment of the present invention.
【図８】 本発明の第４の実施形態に係るプリント配線
組立体の要部断面図である。FIG. 8 is a sectional view of a main part of a printed wiring assembly according to a fourth embodiment of the present invention.
【図９】 従来のプリント配線組立体の要部断面図であ
る。FIG. 9 is a sectional view of a main part of a conventional printed wiring assembly.
６…コア基材、 ７…半導体素子、 ８…絶縁層、 ９
…配線パターン、 １０…接続孔、 １８…バンプ、
２３…ヒートシンク6: core substrate, 7: semiconductor element, 8: insulating layer, 9
... wiring pattern, 10 ... connection hole, 18 ... bump,
23 ... heat sink
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/07 25/18 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 25/07 25/18
Claims (5)
子と、 前記絶縁層上に形成された配線パターンとを具備し、 前記半導体素子に形成された接続端子および前記絶縁層
上の配線パターンを接続するため、前記絶縁層に導電性
の接続孔を形成したことを特徴とする請求項１記載のプ
リント配線組立体。1. A core substrate, an insulating layer laminated on the core substrate, a semiconductor element embedded between the core substrate and the insulating layer, and a wiring pattern formed on the insulating layer. The printed wiring set according to claim 1, wherein a conductive connection hole is formed in the insulating layer for connecting a connection terminal formed on the semiconductor element and a wiring pattern on the insulating layer. Three-dimensional.
よる穿孔工程と、前記穿孔行程で形成された孔内壁のメ
ッキ工程とによって形成されたことを特徴とする請求項
１記載のプリント配線組立体。2. The printed wiring assembly according to claim 1, wherein said connection hole is formed by a drilling step by laser or etching and a plating step of an inner wall of the hole formed in said drilling step.
し、両絶縁層間に半導体素子を内蔵して多層構造を形成
したことを特徴とする請求項１または２記載のプリント
配線組立体。3. The printed wiring assembly according to claim 1, wherein an insulating layer is further laminated on the insulating layer, and a semiconductor element is built in between the two insulating layers to form a multilayer structure.
されたバンプ電極を具備したことを特徴とする請求項１
〜３のいずれかに記載のプリント配線組立体。4. The semiconductor device according to claim 1, further comprising a bump electrode disposed on a surface of said core substrate or said insulating layer.
A printed wiring assembly according to any one of claims 1 to 3.
伝導性部材と、前記熱伝導性部材に接続されたヒートシ
ンクとをさらに具備したことを特徴とする請求項１〜請
求項４のいずれかに記載のプリント配線組立体。5. The semiconductor device according to claim 1, further comprising: a heat conductive member arranged in contact with said semiconductor element; and a heat sink connected to said heat conductive member. A printed wiring assembly according to any one of the claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11064686A JP2000261152A (en) | 1999-03-11 | 1999-03-11 | Printed wiring board assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11064686A JP2000261152A (en) | 1999-03-11 | 1999-03-11 | Printed wiring board assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000261152A true JP2000261152A (en) | 2000-09-22 |
Family
ID=13265297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11064686A Pending JP2000261152A (en) | 1999-03-11 | 1999-03-11 | Printed wiring board assembly |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000261152A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003218319A (en) * | 2002-01-18 | 2003-07-31 | Ibiden Co Ltd | Multichip semiconductor device |
| JP2005294724A (en) * | 2004-04-05 | 2005-10-20 | Sony Corp | Semiconductor device and method for manufacturing the same |
| JP2005310946A (en) * | 2004-04-20 | 2005-11-04 | Shinko Electric Ind Co Ltd | Semiconductor device |
| JP2007250608A (en) * | 2006-03-14 | 2007-09-27 | Element Denshi:Kk | Circuit board including hollow part, method for manufacturing the same, method for manufacturing circuit device using the same |
| KR101003437B1 (en) * | 2002-11-11 | 2010-12-27 | 신꼬오덴기 고교 가부시키가이샤 | Electronic parts packaging structure and method of manufacturing the same |
| WO2013035716A1 (en) * | 2011-09-07 | 2013-03-14 | 株式会社村田製作所 | Method for producing module |
| WO2013035717A1 (en) * | 2011-09-07 | 2013-03-14 | 株式会社村田製作所 | Module, and manufacturing method for module |
| WO2013099360A1 (en) * | 2011-12-26 | 2013-07-04 | 株式会社村田製作所 | Module and component equipped with module |
-
1999
- 1999-03-11 JP JP11064686A patent/JP2000261152A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003218319A (en) * | 2002-01-18 | 2003-07-31 | Ibiden Co Ltd | Multichip semiconductor device |
| KR101003437B1 (en) * | 2002-11-11 | 2010-12-27 | 신꼬오덴기 고교 가부시키가이샤 | Electronic parts packaging structure and method of manufacturing the same |
| JP2005294724A (en) * | 2004-04-05 | 2005-10-20 | Sony Corp | Semiconductor device and method for manufacturing the same |
| JP4496825B2 (en) * | 2004-04-05 | 2010-07-07 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| JP2005310946A (en) * | 2004-04-20 | 2005-11-04 | Shinko Electric Ind Co Ltd | Semiconductor device |
| JP2007250608A (en) * | 2006-03-14 | 2007-09-27 | Element Denshi:Kk | Circuit board including hollow part, method for manufacturing the same, method for manufacturing circuit device using the same |
| WO2013035716A1 (en) * | 2011-09-07 | 2013-03-14 | 株式会社村田製作所 | Method for producing module |
| WO2013035717A1 (en) * | 2011-09-07 | 2013-03-14 | 株式会社村田製作所 | Module, and manufacturing method for module |
| JPWO2013035716A1 (en) * | 2011-09-07 | 2015-03-23 | 株式会社村田製作所 | Module manufacturing method |
| WO2013099360A1 (en) * | 2011-12-26 | 2013-07-04 | 株式会社村田製作所 | Module and component equipped with module |
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