JP3777687B2 - Chip carrier - Google Patents

Chip carrier Download PDF

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Publication number
JP3777687B2
JP3777687B2 JP33222996A JP33222996A JP3777687B2 JP 3777687 B2 JP3777687 B2 JP 3777687B2 JP 33222996 A JP33222996 A JP 33222996A JP 33222996 A JP33222996 A JP 33222996A JP 3777687 B2 JP3777687 B2 JP 3777687B2
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Prior art keywords
conductor
layer
chip carrier
chip
wiring board
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JPH10173090A (en
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健人 塚本
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Toppan Inc
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Toppan Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

【０００１】
【発明の属する技術分野】
本発明は半導体集積回路素子（以下、チップと称する）を一つ、あるいは、複数個搭載し、プリント配線板に接続するために用いるチップキャリア、特に、プリント配線基板との接続端子を面上に配置したＢＧＡ（ボール・グリッド・アレイ）構造を有するチップキャリアに関する。
【０００２】
【従来の技術】
電子機器の小型化の要求に対応するため、チップを搭載した半導体装置をプリント配線板表面上に実装する方式がとられてきた。従来、代表的な表面実装型チップキャリアとして、ＱＦＰ（クワッド・フラット・パッケージ）があげられる。
【０００３】
ＱＦＰは、パッケージの内部でチップ５１とリードフレームのインナーリード５２とを金ワイヤ５４にてワイヤーボンディング等により接続し、チップ５１を含む領域を樹脂５５にてモールドしてパッケージとし、その四辺からリードフレームのアウターリード５３を引き出し、前記リードをガルウイング状に形成し、外部回路と接続する方法の半導体パッケージであり、最も広く普及している（図６参照）。
【０００４】
近年、ゲートアレイ等ＡＳＩＣの分野ではチップの端子数が増加の傾向にあるが、パッケージサイズは現状レベルか縮小の要求が高い。このため、アウターリードのピッチは０．５ｍｍから０．３ｍｍへ狭まる方向にある。アウターリードピッチが０．３ｍｍのＱＦＰでは、半田ブリッジ等の問題が発生し、プリント配線板等の外部接続端子への実装が困難になると言われている。
【０００５】
この問題点に対し、最近はボール状外部接続用端子を基板の面内にマトリックス状に配置させたＢＧＡ型半導体装置が考案されている。
【０００６】
一般的なＢＧＡ型のチップキャリアは、図５に示すように、プリント配線板用の銅張積層板（ビスマレイミド・トリアジン系樹脂、いわゆる、ＢＴレジン系樹脂等からなる絶縁性基板３１の両面に、銅箔を貼り合わせたもの）をベース基板とし、片面には導体配線層３２、薄膜絶縁層３５、導体配線層３２からなる配線回路が形成され、最上層にはチップ３８を搭載し金ワイヤ３９によりそれぞれの電極パッドにワイヤーボンディングにて接続されている。また、ベース基板反対面には半田ボール４２が形成されている。
【０００７】
特に、薄膜多層配線層部の形成方法をより詳細に説明する。絶縁性基板３１の両面に形成された導体層をフォトエッチング法によりパターニング処理して導体配線層３２及び半田パッド３３を形成した後、導体配線層３２面に感光性樹脂をコーティングし感光性絶縁層を形成し、露光、現像工程を行って、上下間の導体層を導通させるためのビアホール形成孔を有する薄膜絶縁層３５を形成する。次に、めっきによって、薄膜絶縁層３５上に導体層とビアホール３７を形成し、導体層をパターニング処理して第２導体配線層３６を形成する。さらに、多層化が必要な場合は、同様の工程を繰り返す。
【０００８】
次に、上記の方法で得られたチップキャリアにチップを搭載して、半導体装置とする工程を説明する。まず、チップ３８を搭載し、金ワイヤ３９にてワイヤーボンディング接合を行った後、モールド樹脂４０にて、チップキャリア上面部を封止する。下面においては、半田パッド３３上に半田ボールを配し、リフロー炉によって半田ボール４２を形成する。
【０００９】
【発明が解決しようとする課題】
近年、搭載するチップの動作速度が向上し、インダクタンスの低減を目的に、図４に示すように、多層配線板上に形成されたチップキャリア電極２３とチップ２４上のチップ電極２５を直接接触させて絶縁層２１上の接着層２２とチップ２４上の保護層２６とで接着、固定して電気的接続を行うフリップチップ実装が行われている。
【００１０】
ところが、フリップチップ実装を行う際、チップキャリア電極の高さのばらつきがあると、安定接続できる電極と安定接続の劣る電極、あるは、接続できない電極がでてくるため、チップ電極との電気的接続信頼性を著しく低下してしまうといった問題が発生する。
【００１１】
本発明は、上記問題を解決しようとするものであり、チップキャリアにおけるフリップチップ実装時のチップキャリア電極とチップ電極との電気的接続信頼性を向上させることを目的とする。
【００１２】
【課題を解決するための手段】
本発明において上記課題を達成するために、まず請求項１においては、絶縁樹脂層と導体配線パターンを交互に積層してなる多層配線板の片面に半導体集積回路素子が搭載され、該多層配線板の反対面には、外部回路に接続するための半田ボールが面状に形成されたチップキャリアにおいて、前記半導体集積回路素子の搭載面は、接着剤層（９）と電極部（１０）からなり、前記電極部（１０）から水平方向へ、少なくとも１本以上の導体層（７）が延伸し、その端部より下部導体配線パターン（３）へ電気的導通をとるようにしたものである。
【００１３】
さらに、請求項１においては、前記水平方向へ延伸した導体層（７）が、異種金属の２層の導体層（７ａ、７ｂ）からなり、半導体集積回路素子搭載側の導体層（７ｂ）の線膨張係数がもう一方の導体層（７ａ）のそれと比較して大きくしたものである。
【００１４】
さらにまた、請求項２においては、前記水平方向へ延伸した導体層（７）の下部絶縁樹脂層（９）の弾性率を常温で１０６〜１０８Ｐａとしたものである。
【００１５】
【発明の実施の形態】
本発明のチップキャリアについて、図１、図２及び図３を用いて詳細に説明する。
チップ電極と接続するチップキャリア電極部近傍の構造は、電極部１０の下部から水平方向へ導体層７が延伸し、その端部にてさらに下部の導体配線パターン３とビアホール８にて接続されている。また、この水平方向へ延伸した導体層７の下部の絶縁樹脂層５はその他の絶縁樹脂層１よりゴム弾性を有し、詳しくは、弾性率が常温で１０6 〜１０8 Ｐａであることが望ましい。
【００１６】
この構造をとることにより、チップ電極との接続の際、導体層７の端部を支点にして導体層７がバネとして働くため、チップ電極を電極部１０で絶えず押し上げる力として働き、電極部１０の高さにばらつきがあっても、チップの全電極との電気的接続信頼性を向上させるとができる。
【００１７】
この導体層７は、図２に示すように１方向へ延伸すると限るものでなく、２方向、４方向、あるいは、それ以上と設けることが可能である。２方向以上の場合、各端部に接続したバイアホールの下部導体配線パターンに各々接続される。これにより、２方向以上に延伸した各導体層の端部をそれぞれ支点としてバネとして働くため、チップ電極との接触圧が増強され、電気的接続信頼性を向上させることができる。
【００１８】
また、チップの固定はチップキャリア表面層の接着剤層９で行う。接着剤としては熱可塑性接着剤を用いることにより、搭載したチップのリペアが容易になる。また、前記導体層７は、異種金属の２層の導体層（７ａ、７ｂ）からなり、２層の導体層（７ａ、７ｂ）のうちチップ搭載側の導体層７ａの線膨張係数が反対側の導体層７ｂのそれと比較して大きいものを用いる。この構成をとると、チップを固定する際の加熱により、チップ搭載面と反対側に反る力が加わり、より安定にチップの固定を行える。さらに、常温にもどした際、逆の力が加わるため、高さのばらつきを持った電極とチップの電極の接続をより安定化させることが可能となる。
【００１９】
導体層７はめっきで形成することができるので、めっきの可能な金属を選ぶことができる。上層と下層の金属の組み合わせとしては、亜鉛と銅、亜鉛とニッケルなどが最適である。
【００２０】
【実施例】
以下、本発明を実施例により具体的に説明する。
厚さ１００μｍの両面銅貼りポリイミドフィルム１に、金型で２００μｍの貫通孔を形成し、無電解銅めっき、電解銅めっきを施してスルーホール４を形成し上下銅箔の導通をとった。さらに、両面にフォトレジストＰＭＥＲを約５μｍ塗布し、所定の温度でプリベークを行った。表側には内部配線層、裏側には半田ボールと接続するパッドパターンを有するフォトマスクを介し、５００ｍＪ／ｃｍ2 の露光量で露光し、専用の現像液にて現像を行い、レジストパターンを形成した。所定の温度でポストベークを行った後、５０℃の塩化第２鉄液にてレジストパターン以外の部分の銅箔をエッチングして、半田パッド２及び導体配線パターン３を形成した（図３（ａ）参照）。
【００２１】
前記基板の上面に、あらかじめ、ゴム成分を添加して弾性率を常温で１０8 Ｐａに調整した熱硬化エポキシ樹脂液をコーティングし、所定の温度で硬化させ、絶縁樹脂層５を形成した（図３（ｂ）参照）。
【００２２】
さらに、絶縁樹脂層５の所定の位置にエキシマレーザ加工機にて５０μｍφのビアホール形成孔６を形成した（図３（ｃ））参照。
【００２３】
次に、前記基板を過マンガン酸カリウム７０ｇ／ｌと水酸化ナトリウム４０ｇ／ｌとを含有する酸化剤液に浸漬して絶縁樹脂層５表面を粗面化した。さらに、無電解めっきを施したた後、電解銅めっきにて約１０μｍ厚の導体層７ａを形成した。さらに、導体層７ａ上に亜鉛めっきを行い約１０μｍ厚の導体層７ｂを形成し、導体配線パターン３とビアホール８にて導通接続を行った。その後、フォトエッチング加工にてパターニング処理して導体層７を形成した（図３（ｄ）参照）。
【００２４】
さらに、上面に耐熱性熱可塑接着剤ハイマル（日立化成工業製）をコーティングし、約３０μｍ厚の接着剤層９を形成した。さらに、所定の位置にエキシマレーザ加工機にて５０μｍφの開口部を形成した。その後、半田パッド２をめっき電極にして開口部に電解銅めっきを行い電極部１０を形成した（図３（ｅ））。
【００２５】
【発明の効果】
以上のように、本発明によれば、チップキャリア電極部に通じる水平方向の導体層を異種金属からなる２層の導体層にすることにより、チップ電極を電極部１０で絶えず押し上げる力として働き、電極部１０の高さにばらつきがあっても、チップ電極とチップキャリア電極との電気的接触が行われ、チップの全電極との電気的接続信頼性を向上させることができる。
【図面の簡単な説明】
【図１】本発明のチップキャリアの一実施例の構成を示す部分断面図である。
【図２】（ａ）は、本発明のチップキャリアの一実施例の電極部１０と導体層７を示す上面図である。（ｂ）〜（ｃ）は、本発明のチップキャリアの他の実施例の電極部１０と導体層を示す上面図である。
【図３】（ａ）〜（ｅ）は、本発明のチップキャリアの一実施例の製造方法を示す部分断面図である。
【図４】従来のチップキャリア（フリップチップ）の構成を示す部分断面図である。
【図５】従来のチップキャリア（ＢＧＡ）の構成を示す部分断面図である。
【図６】従来のチップキャリア（ＱＦＰ）の構成を示す断面図である。
【符号の説明】
１……絶縁樹脂層
２……半田パッド
３……導体配線パターン
４……スルーホール
５……絶縁樹脂層
６……ビアホール形成孔
７……導体層
７ａ……線膨張係数が大きい導体層
７ｂ……線膨張係数が小さい導体層
８……ビアホール
９……接着剤層
１０……電極部
２１……絶縁樹脂層
２２……接着剤層
２３……チップキャリア電極
２４……チップ
２５……チップ電極
２６……保護層
３１……絶縁性基板
３２……導体配線層
３３……半田パッド
３４……スルーホール
３５……薄膜絶縁層
３６……第２導体配線層
３７……ビアホール
３８……チップ
３９……金ワイヤ
４０……モールド樹脂
４１……半田パッド周辺部の絶縁部
４２……半田ボール
５１……チップ
５２……インナーリード
５３……アウターリード
５４……金ワイヤ
５５……樹脂[0001]
BACKGROUND OF THE INVENTION
In the present invention, one or a plurality of semiconductor integrated circuit elements (hereinafter referred to as chips) are mounted, and a chip carrier used for connecting to a printed wiring board, in particular, a connection terminal to the printed wiring board is provided on the surface. The present invention relates to a chip carrier having an arranged BGA (ball grid array) structure.
[0002]
[Prior art]
In order to meet the demand for miniaturization of electronic equipment, a method of mounting a semiconductor device on which a chip is mounted on the surface of a printed wiring board has been adopted. Conventionally, QFP (quad flat package) is mentioned as a typical surface mount chip carrier.
[0003]
In the QFP, a chip 51 and an inner lead 52 of a lead frame are connected to each other by a wire bonding or the like with a gold wire 54 inside the package, and a region including the chip 51 is molded with a resin 55 to form a package, and leads from four sides thereof This is a semiconductor package in which the outer lead 53 of the frame is pulled out, the lead is formed in a gull wing shape, and connected to an external circuit, and is most widely used (see FIG. 6).
[0004]
In recent years, in the field of ASICs such as gate arrays, the number of chip terminals tends to increase, but there is a high demand for package size at the current level or reduction. For this reason, the pitch of the outer leads is in a direction narrowing from 0.5 mm to 0.3 mm. With QFP having an outer lead pitch of 0.3 mm, it is said that problems such as solder bridges occur and mounting on external connection terminals such as a printed wiring board becomes difficult.
[0005]
Recently, a BGA type semiconductor device has been devised in which ball-like external connection terminals are arranged in a matrix in the plane of the substrate.
[0006]
As shown in FIG. 5, a general BGA type chip carrier has a copper-clad laminate (bismaleimide / triazine resin, so-called BT resin resin, etc.) on both surfaces of a printed circuit board. , Copper foil bonded together) is used as a base substrate, and a wiring circuit comprising a conductor wiring layer 32, a thin film insulating layer 35, and a conductor wiring layer 32 is formed on one side, and a chip 38 is mounted on the top layer and a gold wire. 39 is connected to each electrode pad by wire bonding. Solder balls 42 are formed on the opposite surface of the base substrate.
[0007]
In particular, a method for forming a thin film multilayer wiring layer portion will be described in more detail. A conductive layer formed on both surfaces of the insulating substrate 31 is patterned by a photo-etching method to form a conductive wiring layer 32 and a solder pad 33, and then a photosensitive resin is coated on the conductive wiring layer 32 to coat the photosensitive insulating layer. The thin film insulating layer 35 having via hole formation holes for conducting the conductive layer between the upper and lower sides is formed by performing exposure and development processes. Next, a conductor layer and a via hole 37 are formed on the thin film insulating layer 35 by plating, and the conductor layer is patterned to form a second conductor wiring layer 36. Further, when multilayering is necessary, the same process is repeated.
[0008]
Next, a process of mounting a chip on the chip carrier obtained by the above method to obtain a semiconductor device will be described. First, after the chip 38 is mounted and wire bonding is performed with the gold wire 39, the chip carrier upper surface portion is sealed with the mold resin 40. On the lower surface, solder balls are arranged on the solder pads 33, and the solder balls 42 are formed by a reflow furnace.
[0009]
[Problems to be solved by the invention]
In recent years, the operating speed of the chip to be mounted has been improved, and for the purpose of reducing inductance, the chip carrier electrode 23 formed on the multilayer wiring board and the chip electrode 25 on the chip 24 are brought into direct contact as shown in FIG. Thus, flip-chip mounting is performed in which the adhesive layer 22 on the insulating layer 21 and the protective layer 26 on the chip 24 are bonded and fixed for electrical connection.
[0010]
However, when flip chip mounting is performed, if there are variations in the height of the chip carrier electrode, an electrode that can be stably connected and an electrode that cannot be connected stably, or an electrode that cannot be connected, will appear. There arises a problem that the connection reliability is significantly lowered.
[0011]
The present invention is intended to solve the above-described problem, and an object of the present invention is to improve electrical connection reliability between a chip carrier electrode and a chip electrode at the time of flip chip mounting in a chip carrier.
[0012]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, first, in claim 1, a semiconductor integrated circuit element is mounted on one side of a multilayer wiring board formed by alternately laminating insulating resin layers and conductor wiring patterns, and the multilayer wiring board. In the chip carrier in which solder balls for connecting to an external circuit are formed on the opposite surface, the mounting surface of the semiconductor integrated circuit element is composed of an adhesive layer (9) and an electrode portion (10). The at least one conductor layer (7) extends in the horizontal direction from the electrode part (10) and is electrically connected from the end part to the lower conductor wiring pattern (3).
[0013]
Furthermore, in claim 1 , the conductor layer (7) extending in the horizontal direction is composed of two conductor layers (7a, 7b) of different metals, and the conductor layer (7b) on the semiconductor integrated circuit element mounting side is formed. The linear expansion coefficient is larger than that of the other conductor layer (7a).
[0014]
Furthermore, in claim 2 , the elastic modulus of the lower insulating resin layer (9) of the conductor layer (7) extending in the horizontal direction is set to 10 6 to 10 8 Pa at room temperature.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The chip carrier of the present invention will be described in detail with reference to FIG. 1, FIG. 2, and FIG.
In the structure in the vicinity of the chip carrier electrode part connected to the chip electrode, the conductor layer 7 extends in the horizontal direction from the lower part of the electrode part 10, and is further connected to the lower conductor wiring pattern 3 and the via hole 8 at the end part. Yes. Further, the insulating resin layer 5 below the conductor layer 7 extending in the horizontal direction has rubber elasticity as compared with the other insulating resin layers 1. More specifically, the elastic modulus is 10 6 to 10 8 Pa at room temperature. desirable.
[0016]
By adopting this structure, when connecting to the chip electrode, the conductor layer 7 acts as a spring with the end of the conductor layer 7 as a fulcrum, so that it acts as a force that constantly pushes up the chip electrode at the electrode portion 10. Even if there is a variation in the height, the reliability of electrical connection with all the electrodes of the chip can be improved.
[0017]
The conductor layer 7 is not limited to extending in one direction as shown in FIG. 2, and can be provided in two directions, four directions, or more. In the case of two or more directions, each is connected to a lower conductor wiring pattern of a via hole connected to each end. As a result, the end portions of the respective conductor layers extending in two or more directions serve as springs, so that the contact pressure with the chip electrode is increased and the electrical connection reliability can be improved.
[0018]
The chip is fixed by the adhesive layer 9 on the chip carrier surface layer. By using a thermoplastic adhesive as the adhesive, the mounted chip can be easily repaired. The conductor layer 7 is composed of two conductor layers (7a, 7b) of dissimilar metals, and the coefficient of linear expansion of the conductor layer 7a on the chip mounting side of the two conductor layers (7a, 7b) is opposite. The larger conductor layer 7b is used. If this structure is taken, the force which warps to the opposite side to a chip mounting surface will be added by the heating at the time of fixing a chip | tip, and it can fix a chip | tip more stably. Furthermore, since a reverse force is applied when the temperature is returned to room temperature, it becomes possible to further stabilize the connection between the electrode having a variation in height and the electrode of the chip.
[0019]
Since the conductor layer 7 can be formed by plating, a metal that can be plated can be selected. As the combination of the upper layer and lower layer metals, zinc and copper, zinc and nickel, etc. are optimal.
[0020]
【Example】
Hereinafter, the present invention will be specifically described by way of examples.
A 200 μm through hole was formed in a 100 μm thick double-sided copper-coated polyimide film 1 with a mold, and electroless copper plating and electrolytic copper plating were applied to form a through hole 4 to establish conduction between the upper and lower copper foils. Furthermore, about 5 μm of photoresist PMER was applied to both sides, and prebaked at a predetermined temperature. Through a photomask having a pad pattern connected to the inner wiring layer on the front side and solder balls on the back side, exposure was performed at an exposure amount of 500 mJ / cm 2 and development was performed with a dedicated developer to form a resist pattern. . After the post-baking at a predetermined temperature, the copper foil at portions other than the resist pattern was etched with a ferric chloride solution at 50 ° C. to form the solder pad 2 and the conductor wiring pattern 3 (FIG. 3A )reference).
[0021]
On the upper surface of the substrate, a thermosetting epoxy resin liquid in which a rubber component was previously added and an elastic modulus was adjusted to 10 8 Pa at room temperature was coated and cured at a predetermined temperature to form an insulating resin layer 5 (see FIG. 3 (b)).
[0022]
Further, a via hole forming hole 6 of 50 μmφ was formed at a predetermined position of the insulating resin layer 5 with an excimer laser processing machine (see FIG. 3C).
[0023]
Next, the surface of the insulating resin layer 5 was roughened by immersing the substrate in an oxidizing agent solution containing 70 g / l of potassium permanganate and 40 g / l of sodium hydroxide. Furthermore, after applying electroless plating, a conductor layer 7a having a thickness of about 10 μm was formed by electrolytic copper plating. Further, galvanization was performed on the conductor layer 7 a to form a conductor layer 7 b having a thickness of about 10 μm, and the conductor wiring pattern 3 and the via hole 8 were electrically connected. Thereafter, patterning was performed by photoetching to form a conductor layer 7 (see FIG. 3D).
[0024]
Furthermore, the upper surface was coated with a heat-resistant thermoplastic adhesive HIMARU (manufactured by Hitachi Chemical Co., Ltd.) to form an adhesive layer 9 having a thickness of about 30 μm. Further, an opening of 50 μmφ was formed at a predetermined position by an excimer laser processing machine. Thereafter, the electrode part 10 was formed by performing electrolytic copper plating on the opening using the solder pad 2 as a plating electrode (FIG. 3E).
[0025]
【The invention's effect】
As described above, according to the present invention, the horizontal conductor layer leading to the chip carrier electrode portion is formed as a two-layer conductor layer made of a dissimilar metal, thereby acting as a force for constantly pushing up the chip electrode at the electrode portion 10, Even if the height of the electrode part 10 varies, electrical contact between the chip electrode and the chip carrier electrode is performed, and electrical connection reliability with all the electrodes of the chip can be improved.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view showing a configuration of an embodiment of a chip carrier of the present invention.
FIG. 2A is a top view showing an electrode portion 10 and a conductor layer 7 of an embodiment of a chip carrier of the present invention. (B)-(c) is a top view which shows the electrode part 10 and conductor layer of the other Example of the chip carrier of this invention.
FIGS. 3A to 3E are partial cross-sectional views showing a manufacturing method of an embodiment of a chip carrier of the present invention. FIGS.
FIG. 4 is a partial cross-sectional view showing a configuration of a conventional chip carrier (flip chip).
FIG. 5 is a partial cross-sectional view showing a configuration of a conventional chip carrier (BGA).
FIG. 6 is a cross-sectional view showing a configuration of a conventional chip carrier (QFP).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulating resin layer 2 ... Solder pad 3 ... Conductor wiring pattern 4 ... Through hole 5 ... Insulating resin layer 6 ... Via-hole formation hole 7 ... Conductor layer 7a ... Conductor layer 7b with a large linear expansion coefficient …… Conductor layer 8 with small linear expansion coefficient ...... Via hole 9 ...... Adhesive layer 10 ...... Electrode part 21 ...... Insulating resin layer 22 ...... Adhesive layer 23 ...... Chip carrier electrode 24 ...... Chip 25 …… Chip Electrode 26 ... Protective layer 31 ... Insulating substrate 32 ... Conductor wiring layer 33 ... Solder pad 34 ... Through hole 35 ... Thin film insulating layer 36 ... Second conductor wiring layer 37 ... Via hole 38 ... Chip 39 ... Gold wire 40 ... Mold resin 41 ... Insulating part 42 around solder pad ... Solder ball 51 ... Chip 52 ... Inner lead 53 ... Outer lead 54 ... Gold wire 55 ... Resin

Claims (2)

絶縁樹脂層と導体配線パターンを交互に積層してなる多層配線板の片面に半導体集積回路素子が搭載され、該多層配線板の反対面には、外部回路に接続するための半田ボールが面状に形成されたチップキャリアにおいて、前記多層配線板の半導体集積回路素子の搭載面は、接着剤層（９）と接着剤層を貫通する電極部（１０）からなり、該電極部（１０）の下部から前記接着剤層下面に沿って水平方向へ、少なくとも１本以上の導体層（７）が延伸し、前記導体層が水平方向へ延伸した先の端部より下部導体配線パターン（３）へ電気的導通がとられ、前記水平方向へ延伸した導体層（７）が、異種金属の２層の導体層（７ａ、７ｂ）からなり、当該異種金属の２層からなる導体層のうち半導体集積回路素子搭載側の導体層（７ｂ）の線膨張係数がもう一方の導体層（７ａ）のそれと比較して大きいことを特徴とするチップキャリア。A semiconductor integrated circuit element is mounted on one side of a multilayer wiring board formed by alternately laminating insulating resin layers and conductor wiring patterns. On the opposite side of the multilayer wiring board, a solder ball for connecting to an external circuit is planar. In the chip carrier formed on the semiconductor integrated circuit device, the mounting surface of the multilayer wiring board of the semiconductor integrated circuit element includes an adhesive layer (9) and an electrode portion (10) penetrating the adhesive layer . At least one or more conductor layers (7) extend in the horizontal direction along the lower surface of the adhesive layer from the lower part, and from the end where the conductor layers extend in the horizontal direction to the lower conductor wiring pattern (3). The conductor layer (7) that is electrically conductive and extends in the horizontal direction is composed of two conductor layers (7a, 7b) made of different metals, and the semiconductor integration of the two conductor layers made of different metals. Linear expansion of the conductor layer (7b) on the circuit element mounting side Chip carrier, wherein the number is large compared with that of the other conductor layer (7a). 前記多層配線板は、前記水平方向へ延伸した導体層（７）の下部に前記接着剤層と隣接する絶縁樹脂層をさらに有し、当該絶縁樹脂層の弾性率を常温で１０６〜１０８Ｐａとすることを特徴とする請求項１記載のチップキャリア。 The multilayer wiring board further includes an insulating resin layer adjacent to the adhesive layer below the conductor layer (7) extending in the horizontal direction, and the elastic modulus of the insulating resin layer is 10 6 to 10 8 at room temperature. The chip carrier according to claim 1, wherein the chip carrier is Pa.
JP33222996A 1996-12-12 1996-12-12 Chip carrier Expired - Fee Related JP3777687B2 (en)

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