JPH10321750A - Semiconductor device and manufacture of wiring board having semiconductor chip mounted thereon - Google Patents

Semiconductor device and manufacture of wiring board having semiconductor chip mounted thereon

Info

Publication number
JPH10321750A
JPH10321750A JP9126762A JP12676297A JPH10321750A JP H10321750 A JPH10321750 A JP H10321750A JP 9126762 A JP9126762 A JP 9126762A JP 12676297 A JP12676297 A JP 12676297A JP H10321750 A JPH10321750 A JP H10321750A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor chip
electrode
solder
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9126762A
Other languages
Japanese (ja)
Other versions
JP3795628B2 (en
Inventor
Atsushi Komura
敦 小村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP12676297A priority Critical patent/JP3795628B2/en
Publication of JPH10321750A publication Critical patent/JPH10321750A/en
Application granted granted Critical
Publication of JP3795628B2 publication Critical patent/JP3795628B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof

Abstract

PROBLEM TO BE SOLVED: To enable suppression of stresses to a connection part caused by connecting a semiconductor chip to an external wiring board, even when a volume of projected terminals of a semiconductor device is decreased with an increased number of output terminals of the semiconductor chip, to thereby secure a connection reliability. SOLUTION: A wiring board 17 is provided on its solder ball mounting side with a base material 6, made of a BT resin glass cloth or an epoxy resin glass cloth. Formed on the base material is a buffer layer 7 having an elastic modulus of 0.5-5 kgf/mm<2> . Formed on the buffer layer is a pad electrode 10, on which wiring and solder balls 11 are formed. The solder balls 11 are made of a composition with Sn and Pb in an Sn/Pb ratio of 6:4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップを配
線基板に搭載し半導体チップと配線基板とを電気的な接
続を行い、その接続部を覆うように樹脂で封止し、配線
基板上に外部の配線基板と接続を行うためのハンダ突起
端子を設けた半導体装置の構造と、半導体チップを搭載
する配線基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor chip on a wiring board, electrically connecting the semiconductor chip to the wiring board, sealing the connection portion with a resin, and mounting the semiconductor chip on the wiring board. The present invention relates to a structure of a semiconductor device provided with solder projection terminals for connection to an external wiring board, and a method of manufacturing a wiring board on which a semiconductor chip is mounted.

【０００２】[0002]

【従来の技術】近年、半導体装置の高機能化にともな
い、半導体装置の外部端子の数は増大する傾向にあり、
側面に外部端子を設けいているＱＦＰのような半導体装
置は外部端子の端子ピッチを狭くしたとしても、外形サ
イズが大きくなってしまう傾向にある。これにたいし
て、ＢＧＡあるいはＣＳＰのような電極端子をアレイ上
に配置できる半導体装置は、外部端子の増加ができ、且
つＱＦＰよりも外形サイズを小さくする事が可能であ
る。このような半導体装置の例としては配線基板を使用
した半導体装置として、たとえば特開平６−３４９９７
３号公報や、配線基板を使用しない半導体装置として特
開平２−４９４６０号公報があげられる。2. Description of the Related Art In recent years, the number of external terminals of a semiconductor device has been increasing with the advancement of functions of the semiconductor device.
Semiconductor devices such as QFPs provided with external terminals on the side surface tend to have a large external size even if the terminal pitch of the external terminals is reduced. On the other hand, a semiconductor device such as BGA or CSP in which electrode terminals such as CSP can be arranged on an array can increase the number of external terminals and can have a smaller external size than QFP. As an example of such a semiconductor device, a semiconductor device using a wiring board is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-34997.
Japanese Patent Laid-Open No. 2-49460 discloses a semiconductor device that does not use a wiring substrate.

【０００３】配線基板を使用した電極端子をアレイ上に
形成した半導体装置の構造について図２３を用いて説明
する。図２３は、前述の特開平６−３４９９７３号公報
に開示された半導体装置を示す断面図である。The structure of a semiconductor device in which electrode terminals using a wiring substrate are formed on an array will be described with reference to FIG. FIG. 23 is a sectional view showing a semiconductor device disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-349973.

【０００４】半導体チップ１２０上には合金系の突起電
極１２２が形成されている。配線基板１２６には半導体
チップ１２０の突起電極１２２の配置に対応するように
形成された電極１２３が形成され、他面には外部の配線
基板との接続するようにパッド電極１２４が形成されて
いる。半導体チップ１２０と配線基板１２６とは、半導
体チップ１２０に形成した突起電極１２２で電気的接続
を行い、半導体チップ１２０を覆うように樹脂１２１で
封止されている。配線基板１２６の他面のパッド電極上
には合金系の突起端子１２５が形成されている。On the semiconductor chip 120, an alloy-based projecting electrode 122 is formed. An electrode 123 formed so as to correspond to the arrangement of the protruding electrodes 122 of the semiconductor chip 120 is formed on the wiring substrate 126, and a pad electrode 124 is formed on the other surface so as to be connected to an external wiring substrate. . The semiconductor chip 120 and the wiring board 126 are electrically connected by the protruding electrodes 122 formed on the semiconductor chip 120, and are sealed with a resin 121 so as to cover the semiconductor chip 120. An alloy-based projection terminal 125 is formed on the pad electrode on the other surface of the wiring board 126.

【０００５】配線基板を使用しない電極端子をアレイ上
に形成した半導体装置の構造について、図２４を用いて
説明する。図２４は前述の特開平２−４９４６０号公報
に開示された半導体装置を示す断面図である。The structure of a semiconductor device in which electrode terminals without using a wiring substrate are formed on an array will be described with reference to FIG. FIG. 24 is a sectional view showing a semiconductor device disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2-49460.

【０００６】半導体チップ１３０の主表面上には電極１
３１が形成されていて、この電極は外部の配線基板との
接続するための突起端子１３５の一部として機能してい
る。電極１３１の一部表面の露出させるように、半導体
チップ１３０の表面にパッシベーション膜が形成されて
いる。電極１３１の一部表面上に外部の配線基板との接
続するための突起端子１３５が形成されている。この突
起端子１３５の一部を露出させ、かつ半導体チップ全体
を覆うように樹脂１３２で封止されている。[0006] The electrode 1 is formed on the main surface of the semiconductor chip 130.
The electrode 31 functions as a part of a protruding terminal 135 for connection to an external wiring board. A passivation film is formed on the surface of the semiconductor chip 130 so that a part of the surface of the electrode 131 is exposed. Projection terminals 135 for connection to an external wiring board are formed on a partial surface of the electrode 131. The protruding terminal 135 is sealed with a resin 132 so as to expose a part of the protruding terminal 135 and cover the entire semiconductor chip.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、半導体
チップの出力端子が増加すると、アレイ状に形成してい
る突起端子の間隔を狭めなければならなくなり、これに
よって突起端子の体積が小さくなってしまう。これによ
って配線基板あるいは半導体装置に直接突起端子に形成
した前述のような半導体装置では、外部の配線基板と接
続したとき、外部の配線基板と半導体装置との間隔が狭
くなり、さらに温度サイクル試験等の環境試験に投入す
ることによって発生する接続部への応力が増大し、半導
体装置の熱疲労寿命が低下してしまう。接続不良になっ
た半導体装置は突起端子の根本で破断を起こしている。However, when the number of output terminals of the semiconductor chip increases, the interval between the protruding terminals formed in an array has to be reduced, thereby reducing the volume of the protruding terminals. As a result, in the above-described semiconductor device formed directly on the wiring substrate or the semiconductor device on the protruding terminal, when the semiconductor device is connected to an external wiring substrate, the distance between the external wiring substrate and the semiconductor device is reduced, and furthermore, a temperature cycle test or the like is performed. The stress applied to the connection part due to the application to the environmental test described above increases, and the thermal fatigue life of the semiconductor device decreases. The semiconductor device having a poor connection is broken at the root of the protruding terminal.

【０００８】また、図２３にしめすような半導体チップ
を配線基板にフェイスダウンで搭載する半導体装置の構
造においては、半導体チップと配線基板に電気的な接続
を半導体チップに形成した合金系の突起電極で行うの
で、前述のように半導体チップの出力端子が増加する
と、突起電極の間隔も狭めなければならなくなり、よっ
て突起電極の体積が小さくなってしまう。これによって
半導体チップを配線基板に搭載したとき、半導体チップ
と配線基板との間隔が狭くなり、半導体装置を単体で温
度サイクル試験等の環境試験に投入することによって発
生する接続した突起電極への応力が増大し、半導体チッ
プの接続した突起電極の熱疲労寿命が低下してしまう。In the structure of a semiconductor device in which a semiconductor chip is mounted face down on a wiring board as shown in FIG. 23, an alloy-based projecting electrode in which an electrical connection is formed between the semiconductor chip and the wiring board on the semiconductor chip. Therefore, as described above, when the number of output terminals of the semiconductor chip increases, the interval between the protruding electrodes must be reduced, and the volume of the protruding electrodes decreases. As a result, when the semiconductor chip is mounted on the wiring board, the distance between the semiconductor chip and the wiring board becomes narrower, and the stress on the connected protruding electrodes generated by putting the semiconductor device alone into an environmental test such as a temperature cycle test. And the thermal fatigue life of the protruding electrode connected to the semiconductor chip decreases.

【０００９】〔発明の目的〕本発明の第１の目的は、前
述の課題を解決して、半導体チップの出力端子の増加に
伴い突起端子の体積が小さくなっても、外部の配線基板
との接続したことによって発生する接続部への応力を緩
和して接続信頼性を損なわない半導体装置および半導体
チップを搭載する配線基板の製造方法を提供することに
ある。A first object of the present invention is to solve the above-mentioned problems and to reduce the volume of the protruding terminals with the increase in the number of output terminals of the semiconductor chip. It is an object of the present invention to provide a semiconductor device and a method of manufacturing a wiring board on which a semiconductor chip is mounted without reducing the connection reliability caused by the connection by reducing the stress on the connection portion.

【００１０】本発明のもう１つの目的は、半導体チップ
を配線基板にフェイスダウンで搭載する半導体装置の構
造において、前述の目的に加えて半導体チップの出力端
子の増加に伴い突起電極の体積が小さくなっても、配線
基板との接続したことによって発生する突起電極への応
力を緩和して接続信頼性を損なわない半導体装置および
半導体チップを搭載する配線基板の製造方法を提供する
ことにある。Another object of the present invention is to provide a semiconductor device structure in which a semiconductor chip is mounted face down on a wiring board. In addition to the above-mentioned objects, the volume of the protruding electrode is reduced with an increase in the number of output terminals of the semiconductor chip. It is an object of the present invention to provide a semiconductor device and a method of manufacturing a wiring board on which a semiconductor chip is mounted without reducing the stress on the protruding electrodes caused by the connection with the wiring board and reducing the connection reliability.

【００１１】[0011]

【課題を解決するための手段】前述した目的を達成する
ために、本発明の半導体装置の構造および半導体チップ
を搭載する配線基板の製造方法は、下記記載の手段を採
用する。In order to achieve the above-mentioned object, the structure of a semiconductor device and a method of manufacturing a wiring board on which a semiconductor chip is mounted according to the present invention employs the following means.

【００１２】本発明の半導体装置は、半導体装置回路形
成面に形成した外部引き出し用の電極をもつ半導体チッ
プと、半導体チップを搭載する側には半導体チップの電
極と電気的接続を行うための電極や配線を配し、外部の
配線基板と電気的な接続を行う側に基材の上に基材より
も弾性係数が大きい材料を使った緩和層を形成し、その
上に配線や外部の配線基板と電気的接続を行うパッド電
極を形成した配線基板と、外部の配線基板と電気的接続
を行うパッド電極上にはハンダで形成した突起端子と、
少なくとも半導体チップと電気的接続した接続部を封止
樹脂で覆われている半導体チップを配線基板にフェイス
アップで搭載した構造を特徴としたものである。A semiconductor device according to the present invention has a semiconductor chip having an external lead electrode formed on a semiconductor device circuit formation surface, and an electrode for electrically connecting to the semiconductor chip electrode on the side on which the semiconductor chip is mounted. On the side where electrical connection with the external wiring board is made, form a relaxation layer using a material with a larger elastic modulus than the base on the base, and then place wiring and external wiring on it A wiring board on which a pad electrode for making an electrical connection with the substrate is formed, and a projecting terminal formed of solder on the pad electrode for making an electrical connection with an external wiring board;
The semiconductor device is characterized in that a semiconductor chip having at least a connection portion electrically connected to the semiconductor chip covered with a sealing resin is mounted face-up on a wiring board.

【００１３】本発明の半導体装置は、回路形成面に形成
した外部引き出し用の電極に突起電極をもつ半導体チッ
プと、外部の配線基板と電気的な接続を行う側のみある
いは半導体チップを搭載する側と外部の配線基板と電気
的な接続を行う側の両方に基材の上に基材よりも弾性係
数が大きい材料を使った緩和層を形成する。半導体チッ
プを搭載する側には半導体チップの突起電極と電気的接
続を行うための電極と配線を配し、外部の配線基板と電
気的な接続を行う側には外部の配線基板と電気的接続を
行うパッド電極や配線を形成した配線基板と、外部の配
線基板と電気的接続を行うパッド電極上にはハンダで形
成した突起端子と、半導体チップと配線基板との間隙に
封止樹脂を注入した半導体チップを配線基板にフェイス
ダウンで搭載した構造を特徴とする。さらに、半導体チ
ップを搭載する側の電極にはハンダ層を形成してあると
する。A semiconductor device according to the present invention comprises a semiconductor chip having a protruding electrode on an external lead electrode formed on a circuit forming surface, and a side for electrically connecting to an external wiring board or a side for mounting the semiconductor chip. A relaxation layer using a material having a larger elastic modulus than the base material is formed on the base material on both sides of the substrate and the side for making electrical connection with the external wiring board. On the side where the semiconductor chip is mounted, electrodes and wiring for making an electrical connection with the protruding electrodes of the semiconductor chip are arranged, and on the side for making an electrical connection with the external wiring board, an electrical connection is made with the external wiring board. Insulation resin is injected into the gap between the semiconductor chip and the wiring board, and the wiring board on which the pad electrodes and the wiring are formed, and the protruding terminals formed by solder on the pad electrodes that make the electrical connection with the external wiring board The semiconductor chip is mounted face down on a wiring board. Further, it is assumed that a solder layer is formed on the electrode on which the semiconductor chip is mounted.

【００１４】本発明の半導体チップを搭載する配線基板
の製造方法は、基材の片面あるいは両面に基材よりも弾
性係数が大きい材料を使った緩和層を形成する工程と、
基材に緩和層を形成した基板にこれらを貫通するスルー
ホールを形成する工程と、スルーホールを含め配線を形
成する工程、半導体チップの電極と電気的接続を行うた
めの電極と外部の配線基板と電気的な接続を行うための
パッド電極を形成する工程、半導体チップの電極と電気
的接続を行うための電極のみハンダ層を形成する工程を
有することを特徴とする。The method for manufacturing a wiring board on which a semiconductor chip is mounted according to the present invention comprises a step of forming a relaxation layer using a material having a larger elastic modulus than the base material on one or both surfaces of the base material;
A step of forming through-holes penetrating these on a substrate having a relaxation layer formed on a substrate, a step of forming wiring including through-holes, an electrode for making electrical connection with electrodes of a semiconductor chip, and an external wiring board A step of forming a pad electrode for making an electrical connection with the semiconductor chip, and a step of forming a solder layer only for an electrode for making an electrical connection to an electrode of the semiconductor chip.

【００１５】[0015]

【発明の実施の形態】以下、図面を用いて本発明の半導
体装置および半導体チップを搭載する配線基板の製造方
法における最適な実施形態の説明を行う。まずはじめに
本発明の半導体装置の構造を説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device and a method of manufacturing a wiring board on which a semiconductor chip is mounted according to the present invention. First, the structure of the semiconductor device of the present invention will be described.

【００１６】〔第１の実施形態の半導体装置の構造説
明：図１〜図５〕本発明における第１の実施形態の半導
体装置の構造の実施形態について、図１〜図５を用いて
説明する。図１は本発明の半導体装置の構造における半
導体装置の断面図であり、図２は半導体チップ１の電極
１６側から見た平面図であり、図３は半導体チップ１の
断面図であり、図４は配線基板１７の半導体チップ１搭
載側から見た平面図であり、図５は配線基板１７の断面
図である。[Structural Description of Semiconductor Device of First Embodiment: FIGS. 1 to 5] An embodiment of the structure of the semiconductor device of the first embodiment of the present invention will be described with reference to FIGS. . 1 is a cross-sectional view of the semiconductor device in the structure of the semiconductor device of the present invention, FIG. 2 is a plan view of the semiconductor chip 1 as viewed from the electrode 16 side, and FIG. 3 is a cross-sectional view of the semiconductor chip 1. 4 is a plan view of the wiring board 17 as viewed from the side on which the semiconductor chip 1 is mounted, and FIG. 5 is a sectional view of the wiring board 17.

【００１７】半導体チップ１は図２、図３を用いて説明
する。シリコン基板１４上に電子回路を形成し、その回
路の外部端子としてＡｌまたはＡｕなどで電極１６が形
成されている。電極１６の材料あるいは表面処理につい
ては配線基板１７とをワイヤー８で結線する際のワイヤ
ー８の材料やボンダビリティーを考慮して選択する。半
導体チップ１の電極１６以外の部分は窒化シリコン膜等
の無機膜か前述の無機膜にさらにその上にポリイミド等
の有機膜による保護膜１５で覆われ、外部とは電気的に
絶縁されている。The semiconductor chip 1 will be described with reference to FIGS. An electronic circuit is formed on a silicon substrate 14, and an electrode 16 is formed of Al or Au as an external terminal of the circuit. The material or surface treatment of the electrode 16 is selected in consideration of the material and bondability of the wire 8 when the wiring 16 is connected to the wiring board 17. The portion of the semiconductor chip 1 other than the electrodes 16 is covered with an inorganic film such as a silicon nitride film or the above-mentioned inorganic film, and further covered with a protective film 15 made of an organic film such as a polyimide, and is electrically insulated from the outside. .

【００１８】配線基板１７については図４、図５を用い
て説明する。配線基板１７の半導体チップ１の裏面を搭
載するエリア１８にはダイアタッチパターン１２が形成
されていて、半導体チップ１を搭載した際の電源グラン
ドおよび半導体チップ１から発生する熱を放熱する役割
を兼ねている。ダイアタッチパターン１２内には複数の
サーマルビアホール２１を形成している。サーマルビア
ホール２１は半導体チップ１より発生した熱を配線基板
１７のハンダボール面に逃がす役割とダイアタッチパタ
ーン１２と配線基板１７のパッド電極１０とを電気的に
接続することを兼ねている。またサーマルビアホール２
１や他のスルーホール１３内にはエポキシ樹脂９が埋め
られており、配線基板１７のハンダボール１１搭載側か
ら半導体チップ１搭載側への水分の侵入を抑えることが
できる。The wiring board 17 will be described with reference to FIGS. A die attach pattern 12 is formed in an area 18 of the wiring board 17 on which the back surface of the semiconductor chip 1 is mounted, and also serves as a power ground when the semiconductor chip 1 is mounted and also serves to radiate heat generated from the semiconductor chip 1. ing. A plurality of thermal via holes 21 are formed in the die attach pattern 12. The thermal via hole 21 serves to release heat generated from the semiconductor chip 1 to the solder ball surface of the wiring board 17 and to electrically connect the die attach pattern 12 and the pad electrode 10 of the wiring board 17. Also thermal via hole 2
Epoxy resin 9 is buried in 1 and other through holes 13, so that intrusion of moisture from the solder ball 11 mounting side of the wiring board 17 to the semiconductor chip 1 mounting side can be suppressed.

【００１９】電極１９は、半導体チップ１の電極１６と
をワイヤー８で結線するための電極で、Ｃｕ上にＡｕ／
Ｎｉメッキを施している。ワイヤー８のボンダビリティ
ーを考慮し、Ｎｉ層の厚さが３μｍ〜１５μｍ、Ａｕ層
の厚さが０．３μｍ〜１μｍで形成している。The electrode 19 is an electrode for connecting the electrode 16 of the semiconductor chip 1 with the wire 8.
Ni plating is applied. Considering the bondability of the wire 8, the thickness of the Ni layer is 3 μm to 15 μm, and the thickness of the Au layer is 0.3 μm to 1 μm.

【００２０】配線基板１７の半導体チップ１を搭載する
側は、前述のダイアタッチパターン１２、電極１９以外
部分はソルダーレジスト４で覆われている。The side of the wiring board 17 on which the semiconductor chip 1 is mounted is covered with the solder resist 4 except for the die attach pattern 12 and the electrodes 19 described above.

【００２１】配線基板１７のハンダボール搭載側はＢＴ
レジンガラス布やエポキシ樹脂ガラス布等の基材６上に
弾性率が０．５〜５ｋｇｆ／ｍｍ2 の緩和層７を形成
し、その上に配線やハンダボール１１を搭載するパッド
電極１０を形成している。The solder ball mounting side of the wiring board 17 is BT
A relaxation layer 7 having an elastic modulus of 0.5 to 5 kgf / mm 2 is formed on a base material 6 such as a resin glass cloth or an epoxy resin glass cloth, and a pad electrode 10 on which wiring and solder balls 11 are mounted is formed thereon. doing.

【００２２】パッド電極１０はハンダボール１１を搭載
する際にハンダボール１１がパッド電極１０に対してハ
ンダが充分に濡れ、かつ充分な密着強度を確保するため
に、Ｃｕ上にＡｕ／Ｎｉメッキを施している。それぞれ
金属層の厚さは、Ｎｉ層の厚さが３μｍ〜５μｍ、Ａｕ
層の厚さを０．０２μｍ〜０．０５μｍで形成してい
る。When the solder ball 11 is mounted on the pad electrode 10, Au / Ni plating is performed on Cu so that the solder is sufficiently wetted to the pad electrode 10 and a sufficient adhesion strength is secured. I am giving. Each of the metal layers has a thickness of 3 μm to 5 μm,
The layer has a thickness of 0.02 μm to 0.05 μm.

【００２３】配線基板１７のハンダボール１１を搭載す
る側は前述のパッド電極１０以外部分はソルダーレジス
ト５で覆われている。The part of the wiring board 17 on which the solder balls 11 are mounted is covered with the solder resist 5 except for the pad electrodes 10 described above.

【００２４】半導体装置については前述の半導体チップ
１、配線基板１７を含め図１を用いて説明する。半導体
チップ１は配線基板１７上のダイアタッチパターン１２
上に接着剤３を用いて固定している。接着剤３はエポキ
シ樹脂にＡｇのフィラーを含有しているので、半導体チ
ップ１をダイアタッチパターン１２上に搭載した際の電
源グランドへの電気的接続および半導体チップ１から発
生する熱をダイアタッチパターン１２へ放熱することが
できる。A semiconductor device including the above-described semiconductor chip 1 and wiring board 17 will be described with reference to FIG. The semiconductor chip 1 has a die attach pattern 12 on a wiring board 17.
It is fixed on top using an adhesive 3. Since the adhesive 3 contains an Ag filler in the epoxy resin, the semiconductor chip 1 is electrically connected to a power ground when the semiconductor chip 1 is mounted on the die attach pattern 12 and heat generated from the semiconductor chip 1 is transferred to the die attach pattern. 12 can be dissipated.

【００２５】半導体チップ１上の各電極１６と配線基板
１７上の電極１９との電気的接続はＡｕのワイヤー８で
行われている。Ａｕのワイヤー径は０．０３ｍｍ〜０．
０５ｍｍ程度のワイヤーを使用している。電極１９とパ
ッド電極１０とはスルーホールを介して電気的に接続し
ている。The electrical connection between the electrodes 16 on the semiconductor chip 1 and the electrodes 19 on the wiring board 17 is made by Au wires 8. The wire diameter of Au is 0.03 mm to 0.3 mm.
A wire of about 05 mm is used. The electrode 19 and the pad electrode 10 are electrically connected via a through hole.

【００２６】半導体チップ１、ワイヤー８および配線基
板１７の電極１９は、遮蔽と保護のために封止樹脂２で
封止している。封止樹脂２には熱硬化性のエポキシ系樹
脂を使用している。The semiconductor chip 1, the wires 8 and the electrodes 19 of the wiring board 17 are sealed with a sealing resin 2 for shielding and protection. As the sealing resin 2, a thermosetting epoxy resin is used.

【００２７】さらに、配線基板１７のパッド電極１０に
は、ハンダボール１１を形成している。このハンダボー
ル１１には、ＳｎとＰｂとの比率が６：４の組成のハン
ダを用いている。このハンダボール１１を介してこの半
導体装置と外部の配線基板との電気的接続を行ってい
る。Further, solder balls 11 are formed on the pad electrodes 10 of the wiring board 17. For the solder ball 11, a solder having a composition of Sn: Pb of 6: 4 is used. Through the solder balls 11, the semiconductor device is electrically connected to an external wiring board.

【００２８】〔第２の実施形態の半導体装置の構造説
明：図６〜図１０〕つぎに、以上の説明とべつの第２の
実施形態の実施形態における本発明の半導体装置の構成
の説明を行う。本発明の第２の実施形態の実施形態にお
ける本発明の半導体装置の構成については、図６から図
１０を用いて構造を説明する。図６は本発明の実施形態
における半導体装置の断面図であり、図７は半導体チッ
プ３０の突起電極３３側から見た平面図であり、図８は
半導体チップ３０の断面図であり、図９は配線基板３９
の半導体チップ３０搭載側から見た平面図であり、図１
０は配線基板３９の断面図である。[Structural Description of Semiconductor Device of Second Embodiment: FIGS. 6 to 10] Next, a description of the configuration of the semiconductor device of the present invention in the second embodiment of the present invention will be given. Do. The structure of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention, FIG. 7 is a plan view of the semiconductor chip 30 as viewed from the protruding electrode 33 side, FIG. Is the wiring board 39
FIG. 1 is a plan view as viewed from the side where the semiconductor chip 30 is mounted, and FIG.
0 is a sectional view of the wiring board 39.

【００２９】半導体チップ３０は図７と図８とを用いて
説明する。シリコン基板４５上に電子回路を形成し、そ
の回路の外部端子としてＡｌなどで電極４６が形成され
ている。電極４６の上に配線基板３９の電極４７との電
気的接続を行うためにＣｕあるいはＡｕの突起電極３３
を形成している。The semiconductor chip 30 will be described with reference to FIGS. An electronic circuit is formed on a silicon substrate 45, and an electrode 46 made of Al or the like is formed as an external terminal of the circuit. In order to make electrical connection with the electrode 47 of the wiring board 39 on the electrode 46, a Cu or Au projection electrode 33 is provided.
Is formed.

【００３０】Ａｌの電極４６上にＣｕあるいはＡｕの突
起電極３３形成するためにバリアメタル層４３を蒸着法
やスパッタリング法を用いて形成したのちに、その上に
ＣｕあるいはＡｕの突起電極３３をメッキによって形成
する。バリアメタル層４３は電極４６と突起電極３３の
それぞれの金属の相互拡散を防止するために形成してい
る。In order to form the Cu or Au projection electrode 33 on the Al electrode 46, the barrier metal layer 43 is formed by vapor deposition or sputtering, and then the Cu or Au projection electrode 33 is plated thereon. Formed by The barrier metal layer 43 is formed to prevent mutual diffusion of the respective metals of the electrode 46 and the bump electrode 33.

【００３１】半導体チップ３０の電極４６以外の部分
は、窒化シリコン膜等の無機膜か前述の無機膜にさらに
その上にポリイミド等の有機膜による保護膜４４で覆わ
れ、外部とは電気的に絶縁されている。The portion of the semiconductor chip 30 other than the electrodes 46 is covered with an inorganic film such as a silicon nitride film or the above-mentioned inorganic film, and further covered with a protective film 44 made of an organic film such as polyimide. Insulated.

【００３２】配線基板３９については図９と図１０とを
用いて説明する。配線基板３９の半導体チップ３０搭載
側およびハンダボール４１搭載側の両側には、ＢＴレジ
ンガラス布やエポキシ樹脂ガラス布などの基材３７上に
弾性率が０．５〜５ｋｇｆ／ｍｍ2 の緩和層３５を形成
し、その上に配線、電極４７およびハンダボール４１を
搭載するパッド電極５２を形成している。突起電極３３
に使用する金属の弾性率はＣｕが１３０×１０5 ｋｇｆ
／ｍｍ2で、Ａｕが７８×１０4 ｋｇｆ／ｍｍ2 とハン
ダが３２×１０4 ｋｇｆ／ｍｍ2に比べて堅い材料であ
ることから、半導体チップ３０と配線基板の線膨張係数
の違いにより発生する応力が突起電極３３の根本に集中
するのでこれを緩和するために、配線基板３９の半導体
チップ３０搭載側にも緩和層３５を形成している。The wiring board 39 will be described with reference to FIGS. On both sides of the wiring board 39 on the side where the semiconductor chip 30 is mounted and the side where the solder balls 41 are mounted, a relaxation layer having an elastic modulus of 0.5 to 5 kgf / mm 2 on a base material 37 such as BT resin glass cloth or epoxy resin glass cloth. 35, and a pad electrode 52 on which a wiring, an electrode 47 and a solder ball 41 are mounted is formed thereon. Protruding electrode 33
The elastic modulus of the metal used for copper is 130 × 10 5 kgf
/ Mm 2 , since Au is 78 × 10 4 kgf / mm 2 and the solder is a harder material than 32 × 10 4 kgf / mm 2 , it occurs due to the difference in linear expansion coefficient between the semiconductor chip 30 and the wiring board. Since the generated stress concentrates on the root of the protruding electrode 33, a relief layer 35 is also formed on the side of the wiring substrate 39 on which the semiconductor chip 30 is mounted, in order to alleviate this.

【００３３】配線基板３９の電極４７は半導体チップ３
０に形成している突起電極３３の配置に対応するように
形成している。スルーホール内４０にはエポキシ樹脂４
２が埋められており、配線基板３９のハンダボール４１
搭載側から半導体チップ３０搭載側への水分の侵入を抑
えることができる。The electrode 47 of the wiring board 39 is the semiconductor chip 3
It is formed so as to correspond to the arrangement of the protruding electrodes 33 formed at zero. Epoxy resin 4 in through hole 40
2 are buried, and the solder balls 41 of the wiring board 39 are
Intrusion of moisture from the mounting side to the semiconductor chip 30 mounting side can be suppressed.

【００３４】電極４７は半導体チップ３０の突起電極３
３とを電気的に接続をするために、電極４７のＣｕ上に
ハンダ層４８を施している。このハンダ層４８には、Ｓ
ｎとＰｂとの比率が６：４の組成のハンダを用いてい
る。このハンダ層４８を溶融して、半導体チップ３０の
突起電極３３と接続を行っている。ハンダ層の厚さは２
００μｍ〜５００μｍ程度で形成している。The electrode 47 is the protruding electrode 3 of the semiconductor chip 30.
A solder layer 48 is provided on Cu of the electrode 47 in order to make an electrical connection to the electrode 3. This solder layer 48 includes S
A solder having a composition in which the ratio of n to Pb is 6: 4 is used. The solder layer 48 is melted to make connection with the protruding electrodes 33 of the semiconductor chip 30. Solder layer thickness is 2
The thickness is about 00 μm to 500 μm.

【００３５】配線基板３９の半導体チップ３０を搭載す
る側は、前述の電極４７以外部分はソルダーレジスト３
４で覆われている。On the side of the wiring board 39 on which the semiconductor chip 30 is mounted, the portions other than the electrodes 47 are solder resist 3
4 is covered.

【００３６】ハンダボール４１搭載側のパッド電極５２
はハンダボール４１を搭載する際にハンダボール４１が
パッド電極５２に対してハンダが充分に濡れ、かつ充分
な密着強度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッ
キを施している。各金属層の厚さはＮｉ層の厚さが３〜
５μｍ、Ａｕ層の厚さは０．０２μｍ〜０．０５μｍで
形成している。Pad electrode 52 on solder ball 41 mounting side
In order to ensure that the solder ball 41 sufficiently wets the pad electrode 52 when the solder ball 41 is mounted and that the solder ball 41 has sufficient adhesion strength, Au / Ni plating is applied to Cu. The thickness of each metal layer is 3 to
The Au layer has a thickness of 5 μm and a thickness of 0.02 μm to 0.05 μm.

【００３７】配線基板３９のハンダボール４１を搭載す
る側は、前述のパッド電極５２以外部分はソルダーレジ
スト３４で覆われている。The portion of the wiring board 39 on which the solder balls 41 are mounted is covered with a solder resist 34 except for the pad electrodes 52 described above.

【００３８】半導体装置については前述の半導体チップ
３０、配線基板３９を含め図６を用いて説明する。半導
体チップ１上の各突起電極３３と配線基板３９上の電極
４７との電気的接続は電極４７上に形成したハンダ層４
８を溶融し、突起電極３３と電極４７との接続する。電
極４７とパッド電極５２とはスルーホールを介して電気
的に接続している。A semiconductor device including the above-described semiconductor chip 30 and wiring board 39 will be described with reference to FIG. The electrical connection between each protruding electrode 33 on the semiconductor chip 1 and the electrode 47 on the wiring board 39 is made by the solder layer 4 formed on the electrode 47.
8 is melted, and the protruding electrode 33 and the electrode 47 are connected. The electrode 47 and the pad electrode 52 are electrically connected via a through hole.

【００３９】半導体チップ３０と配線基板３９とのあい
だには、接続部の信頼性向上および半導体チップ３０お
よび配線基板３９に形成されている回路の保護のために
封止樹脂３２で封止している。封止樹脂３２には熱硬化
性のエポキシ系樹脂を使用している。The semiconductor chip 30 and the wiring board 39 are sealed with a sealing resin 32 in order to improve the reliability of the connection portion and protect the circuits formed on the semiconductor chip 30 and the wiring board 39. I have. A thermosetting epoxy resin is used for the sealing resin 32.

【００４０】さらに、配線基板３９のパッド電極５２に
は、ハンダボール４１を形成している。このハンダボー
ル４１には、ＳｎとＰｂとの比率が６：４の組成のハン
ダを用いている。このハンダボール４１を介してこの半
導体装置と外部の配線基板との電気的接続を行ってい
る。Further, the solder balls 41 are formed on the pad electrodes 52 of the wiring board 39. For this solder ball 41, a solder having a composition in which the ratio of Sn to Pb is 6: 4 is used. The semiconductor device and the external wiring board are electrically connected via the solder balls 41.

【００４１】〔第３の実施形態の半導体装置の構造説
明：図１１〜図１５〕つぎに、さらにべつの第３の実施
形態の実施形態における本発明における半導体装置の構
成の説明を行う。本発明の第３の実施形態の実施形態に
ついては、図１１〜図１５を用いて構造を説明する。図
１１は本発明の実施形態における半導体装置の断面図で
あり、図１２は半導体チップ７０の突起電極７１側から
見た平面図であり、図１３は半導体チップ７０の断面図
であり、図１４は配線基板８０の半導体チップ７０搭載
側から見た平面図であり、図１５は配線基板８０の断面
図である。[Structural Description of Semiconductor Device of Third Embodiment: FIGS. 11 to 15] Next, the structure of a semiconductor device according to the present invention in another third embodiment will be described. The structure of the third embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention, FIG. 12 is a plan view of the semiconductor chip 70 as viewed from the protruding electrode 71 side, FIG. 15 is a plan view of the wiring board 80 as viewed from the side where the semiconductor chip 70 is mounted, and FIG. 15 is a cross-sectional view of the wiring board 80.

【００４２】半導体チップ７０は図７と図８とを用いて
説明する。シリコン基板８４上に電子回路を形成し、そ
の回路の外部端子としてＡｌなどで電極８６が形成され
ている。電極８６の上に配線基板８０の電極８７との電
気的接続を行うためにＳｎとＰｂとの比率が６：４の組
成のハンダで突起電極７１を形成している。The semiconductor chip 70 will be described with reference to FIGS. An electronic circuit is formed on a silicon substrate 84, and electrodes 86 are formed of Al or the like as external terminals of the circuit. The protruding electrode 71 is formed on the electrode 86 with solder having a composition of Sn: Pb of 6: 4 in order to electrically connect with the electrode 87 of the wiring board 80.

【００４３】Ａｌの電極８６上に、ハンダの突起電極７
１を形成するためにバリアメタル層８５を蒸着法やスパ
ッタリング法を用いて形成したのちに、その上にハンダ
の突起電極７１をメッキによって形成する。バリアメタ
ル層８５は電極８６と突起電極７１のそれぞれの金属の
相互拡散を防止するために形成している。On the Al electrode 86, the solder bump electrode 7
After forming the barrier metal layer 85 by using an evaporation method or a sputtering method in order to form 1, a solder bump electrode 71 is formed thereon by plating. The barrier metal layer 85 is formed to prevent mutual diffusion of the respective metals of the electrode 86 and the bump electrode 71.

【００４４】半導体チップ７０の電極８６以外の部分は
窒化シリコン膜等の無機膜か前述の無機膜にさらにその
上にポリイミド等の有機膜による保護膜７３で覆われ、
外部とは電気的に絶縁されている。The portions of the semiconductor chip 70 other than the electrodes 86 are covered with an inorganic film such as a silicon nitride film or the above-mentioned inorganic film, and further covered with a protective film 73 made of an organic film such as polyimide.
It is electrically insulated from the outside.

【００４５】配線基板８０については図９と図１０とを
用いて説明する。配線基板８０のハンダボール８２搭載
側にはＢＴレジンガラス布やエポキシ樹脂ガラス布等の
基材７６上に弾性率が０．５〜５ｋｇｆ／ｍｍ2 の緩和
層７７を形成し、その上に配線やハンダボール８２を搭
載するパッド電極８１を形成している。The wiring board 80 will be described with reference to FIGS. 9 and 10. On the solder ball 82 side of the wiring board 80, a relaxation layer 77 having an elastic modulus of 0.5 to 5 kgf / mm 2 is formed on a base material 76 such as BT resin glass cloth or epoxy resin glass cloth, and wiring is formed thereon. And a pad electrode 81 on which a solder ball 82 is mounted.

【００４６】配線基板８０の電極８７は半導体チップ７
０に形成している突起電極７１の配置に対応するように
形成している。スルーホール７９内にはエポキシ樹脂８
３が埋められており、配線基板８０のハンダボール８２
搭載側から半導体チップ７０搭載側への水分の侵入を抑
えることができる。The electrode 87 of the wiring board 80 is
It is formed so as to correspond to the arrangement of the protruding electrodes 71 formed at zero. Epoxy resin 8 in through hole 79
3 are buried, and the solder balls 82 of the wiring board 80 are
Intrusion of moisture from the mounting side to the semiconductor chip 70 mounting side can be suppressed.

【００４７】電極８７は半導体チップ７０のハンダで形
成した突起電極７１が充分に濡れ、しかも充分な密着強
度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッキを施し
ている。それぞれの金属層の厚さは、Ｎｉ層の厚さが３
μｍ〜５μｍ、Ａｕ層の厚さは０．０２μｍ〜０．０５
μｍで形成している。The electrode 87 is formed by plating Au / Ni on Cu in order to sufficiently wet the protruding electrode 71 formed by soldering the semiconductor chip 70 and secure sufficient adhesion strength. The thickness of each metal layer is such that the thickness of the Ni layer is 3
μm to 5 μm, thickness of Au layer is 0.02 μm to 0.05
It is formed in μm.

【００４８】配線基板８０の半導体チップ７０を搭載す
る側は、前述の電極８７以外部分はソルダーレジスト７
４で覆われている。On the side of the wiring board 80 on which the semiconductor chip 70 is mounted, the portions other than the electrodes 87 are solder resist 7
4 is covered.

【００４９】ハンダボール８２搭載側のパッド電極８１
はハンダボール８２を搭載する際にハンダボール８２が
パッド電極８１に対してハンダが充分に濡れ、かつ充分
な密着強度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッ
キを施している。それぞれの金属層の厚さは、Ｎｉ層の
厚さが３μｍ〜５μｍ、Ａｕ層の厚さは０．０２μｍ〜
０．０５μｍで形成している。Pad electrode 81 on solder ball 82 mounting side
In order to ensure that the solder ball 82 sufficiently wets the pad electrode 81 when the solder ball 82 is mounted and that the solder ball 82 has sufficient adhesion strength, Au / Ni plating is applied to Cu. The thickness of each metal layer is 3 μm to 5 μm for the Ni layer and 0.02 μm for the Au layer.
It is formed with a thickness of 0.05 μm.

【００５０】配線基板８０のハンダボール８２を搭載す
る側は前述のパッド電極８１以外部分はソルダーレジス
ト７４で覆われている。The portion of the wiring board 80 on which the solder balls 82 are mounted is covered with a solder resist 74 except for the pad electrodes 81 described above.

【００５１】半導体装置については前述の半導体チップ
７０、配線基板８０を含め図１１を用いて説明する。半
導体チップ７０上の各突起電極７１と配線基板８０上の
電極８７との電気的接続は突起電極７１のハンダを溶融
し、突起電極７１と電極８７との接続する。電極８７と
パッド電極８７とはスルーホールを介して電気的に接続
している。The semiconductor device will be described with reference to FIG. 11, including the semiconductor chip 70 and the wiring board 80 described above. The electrical connection between each protruding electrode 71 on the semiconductor chip 70 and the electrode 87 on the wiring board 80 is achieved by melting the solder of the protruding electrode 71 and connecting the protruding electrode 71 and the electrode 87. The electrode 87 and the pad electrode 87 are electrically connected via a through hole.

【００５２】半導体チップ７０と配線基板８０とのあい
だには、接続部の信頼性向上および半導体チップ７０お
よび配線基板８０に形成されている回路の保護のために
封止樹脂７２で封止している。封止樹脂７２には熱硬化
性のエポキシ系樹脂を使用している。The semiconductor chip 70 and the wiring board 80 are sealed with a sealing resin 72 to improve the reliability of the connection portion and to protect the circuits formed on the semiconductor chip 70 and the wiring board 80. I have. A thermosetting epoxy resin is used for the sealing resin 72.

【００５３】さらに、配線基板７０のパッド電極８１に
は、ハンダボール８２を形成している。このハンダボー
ル８２には、ＳｎとＰｂとの比率が６：４の組成のハン
ダを用いている。このハンダボール８２を介してこの半
導体装置と外部の配線基板との電気的接続を行ってい
る。Further, solder balls 82 are formed on the pad electrodes 81 of the wiring board 70. For the solder ball 82, a solder having a composition in which the ratio of Sn to Pb is 6: 4 is used. The semiconductor device is electrically connected to an external wiring board via the solder balls 82.

【００５４】〔配線基板の製造方法：図１６〜図２０〕
つぎに、さきに説明した本発明の第の実施形態に用いた
配線基板の製造方法について説明する。図１６〜図２０
は本発明の配線基板の製造工程を示す断面図であり、以
下図１６〜２０の図面を用いて説明する。[Method of Manufacturing Wiring Board: FIGS. 16 to 20]
Next, a method of manufacturing the wiring board used in the above-described first embodiment of the present invention will be described. 16 to 20
Is a cross-sectional view showing a manufacturing process of the wiring board of the present invention, which will be described below with reference to FIGS.

【００５５】図１６は配線基板のベースになる基材１０
０である。この基材１００は厚さが０．２〜０．６ｍｍ
程度のＢＴレジンガラス布やエポキシ樹脂ガラス布等を
使用する。基材１００の両面は、その基材１００上に形
成する緩和層１０１を密着をよくするために、粗化処
理、触媒活性化処理を行う。FIG. 16 shows a base material 10 serving as a base of a wiring board.
0. This base material 100 has a thickness of 0.2 to 0.6 mm.
BT resin glass cloth or epoxy resin glass cloth is used. Both surfaces of the substrate 100 are subjected to a roughening treatment and a catalyst activation treatment in order to improve the adhesion of the relaxation layer 101 formed on the substrate 100.

【００５６】両面を粗化処理、触媒活性化処理をおこな
った基材１００上にフィルム状の厚さ３０μｍ〜５０μ
ｍの緩和層１０１および緩和層１０１との密着をよくす
るために表面処理を施した厚さ１８μｍのＣｕ箔１０２
を配し、両側より加圧および温度をかけて積層成形す
る。これによって基材１００の両面に緩和層１０１を形
成した図１７に示す両面板ができる。A film having a thickness of 30 μm to 50 μm is formed on the substrate 100 which has been subjected to a roughening treatment and a catalyst activation treatment on both surfaces.
m relaxing layer 101 and an 18 μm-thick Cu foil 102 that has been subjected to a surface treatment in order to improve adhesion with the relaxing layer 101.
And pressurize and apply temperature from both sides to form a laminate. Thereby, a double-sided board shown in FIG. 17 in which the relaxation layers 101 are formed on both sides of the base material 100 is obtained.

【００５７】両面板に複数のスルーホール１０３をドリ
ル加工あるいはレーザー加工のよって形成する。スルー
ホール１０３内にＣｕメッキを施すために触媒活性化処
理を行い、Ｃｕメッキを行う。これによって図１８に示
すようなスルーホール１０３が形成できる。A plurality of through holes 103 are formed in the double-sided board by drilling or laser processing. In order to perform Cu plating in the through hole 103, a catalyst activation process is performed, and Cu plating is performed. As a result, a through hole 103 as shown in FIG. 18 can be formed.

【００５８】つぎに図１９に示すようなスルーホール１
０３内にエポキシ樹脂１０４充填する。このエポキシ樹
脂１０４の充填方法は、スクリーン印刷法を用いて、基
板の上面に液状のエポキシ樹脂１０４を供給し、スキー
ジによるスルーホール１０３内への塗り込み行う。塗り
込み後エポキシ樹脂１０４を熱硬化し、硬化後基板表面
を研磨する。この方法でスルーホール１０３内にエポキ
シ樹脂１０４を完全に充填できる。Next, a through hole 1 as shown in FIG.
03 is filled with an epoxy resin 104. As a method for filling the epoxy resin 104, a liquid epoxy resin 104 is supplied to the upper surface of the substrate by using a screen printing method, and the epoxy resin 104 is applied to the inside of the through hole 103 by a squeegee. After application, the epoxy resin 104 is thermally cured, and after curing, the substrate surface is polished. By this method, the epoxy resin 104 can be completely filled in the through hole 103.

【００５９】つぎに配線を形成するために、基板両面に
感光性樹脂を塗布し、所定の露光マスクを介し露光、現
像を行い、配線に必要な部分のみエッチングレジスト膜
を形成する。その後Ｃｕのエッチングを行い不要なＣｕ
層を除去し、さらにエッチングレジストを除去する。こ
れによって図２０に示すような配線が形成できる。Next, in order to form a wiring, a photosensitive resin is applied to both surfaces of the substrate, exposed and developed through a predetermined exposure mask, and an etching resist film is formed only in a portion necessary for the wiring. Thereafter, Cu is etched to remove unnecessary Cu.
The layer is removed, and the etching resist is removed. As a result, a wiring as shown in FIG. 20 can be formed.

【００６０】つぎに電極１０６、パッド電極１０７を形
成するために、両面にソルダーレジスト１０７となる感
光性樹脂を塗布し、所定のマスクを介し露光、現像を行
い、電極１０６、パッド電極１０７のみが露出するよう
にソルダーレジスト１０８を形成する。その後、ハンダ
の濡れ性と密着強度を確保するためにソルダーレジスト
１０８をマスクにして、電極１０６、パッド電極１０７
上にＡｕ／Ｎｉメッキを行う。各金属層の厚さはＮｉ層
の厚さが３μｍ〜５μｍ、Ａｕ層の厚さは０．０２μｍ
〜０．０５μｍで形成している。これによって図２１に
示すような電極、パッド電極が形成できる。Next, in order to form the electrode 106 and the pad electrode 107, a photosensitive resin to be the solder resist 107 is applied to both surfaces, and is exposed and developed through a predetermined mask, so that only the electrode 106 and the pad electrode 107 are formed. A solder resist 108 is formed so as to be exposed. After that, in order to secure solder wettability and adhesion strength, the electrode 106 and the pad electrode 107 are
Au / Ni plating is performed thereon. The thickness of each metal layer is 3 μm to 5 μm for the Ni layer, and 0.02 μm for the Au layer.
It is formed with a thickness of about 0.05 μm. Thus, electrodes and pad electrodes as shown in FIG. 21 can be formed.

【００６１】さらに、電極１０６は、半導体チップの突
起電極とを電気的に接続をするために、電極１０６上に
ハンダ層１０９を施している。このハンダ層１０９はス
クリーン印刷法を用いて形成する。電極１０６部分のみ
開口している所定のメタルマスクを使い、そのマスク上
にソルダーペースト供給し、スキージングすることでマ
スクの開口部のみソルダーペーストがマスクを通過し、
電極１０６部分にソルダーペースト供給できる。その
後、ハンダの融点よりも高い温度に基板を通過させるこ
とによりハンダ層１０９が形成できる。ハンダ層１０９
には、ＳｎとＰｂとの比率が６：４の組成のハンダを用
い、ハンダ層１０９の厚さは２０μｍ〜５０μｍ程度で
形成している。これで図２２に示すように、第２の実施
形態に用いた配線基板が完成する。他の実施形態の配線
基板についても前述に示した製造方法の工程あるいは材
料を一部を削除することで作製できる。Further, a solder layer 109 is provided on the electrode 106 in order to electrically connect with the protruding electrode of the semiconductor chip. This solder layer 109 is formed using a screen printing method. Using a predetermined metal mask having an opening only at the electrode 106 portion, supplying a solder paste on the mask, and performing squeezing, the solder paste passes through the mask only at the opening of the mask,
Solder paste can be supplied to the electrode 106 portion. Thereafter, the solder layer 109 can be formed by passing the substrate at a temperature higher than the melting point of the solder. Solder layer 109
, A solder having a composition of Sn: Pb at a ratio of 6: 4 is used, and the thickness of the solder layer 109 is about 20 μm to 50 μm. Thus, as shown in FIG. 22, the wiring board used in the second embodiment is completed. A wiring board according to another embodiment can also be manufactured by partially removing the steps or materials of the manufacturing method described above.

【００６２】[0062]

【発明の効果】以上説明したように、本発明は半導体チ
ップを配線基板上に搭載し、ハンダボールを介して外部
の配線基板と電気的に接続を行う半導体装置で、配線基
板内に半導体チップおよび外部の配線基板との接続によ
り発生する応力を緩和する緩和層を形成している。この
ことによって、半導体装置単体の信頼性および外部の配
線基板の接続した際の接続信頼性を向上することができ
る。今後半導体チップの出力端子の増加に伴い、半導体
装置の突起端子の体積の小さくなって半導体装置の接続
信頼性を損なうことはない。As described above, the present invention relates to a semiconductor device in which a semiconductor chip is mounted on a wiring board and electrically connected to an external wiring board via solder balls. Further, a relaxation layer for relaxing stress generated by connection with an external wiring board is formed. Thus, the reliability of the semiconductor device alone and the connection reliability when the external wiring board is connected can be improved. As the output terminals of the semiconductor chip increase in the future, the volume of the protruding terminals of the semiconductor device will not be reduced and the connection reliability of the semiconductor device will not be impaired.

【００６３】また、配線基板の製造においては、既存の
製造装置を使用することが可能なので、生産上有利であ
る。In the manufacture of a wiring board, an existing manufacturing apparatus can be used, which is advantageous in production.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態における半導体装置を
示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施形態における半導体チップ
を示す平面図である。FIG. 2 is a plan view showing a semiconductor chip according to the first embodiment of the present invention.

【図３】本発明の第１の実施形態における半導体チップ
を示す断面図である。FIG. 3 is a sectional view showing a semiconductor chip according to the first embodiment of the present invention.

【図４】本発明の第１の実施形態における配線基板を示
す平面図である。FIG. 4 is a plan view showing the wiring board according to the first embodiment of the present invention.

【図５】本発明の第１の実施形態における配線基板を示
す断面図である。FIG. 5 is a sectional view showing a wiring board according to the first embodiment of the present invention.

【図６】本発明の第２の実施形態における半導体装置を
示す断面図である。FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

【図７】本発明の第２の実施形態における半導体チップ
を示す平面図である。FIG. 7 is a plan view showing a semiconductor chip according to a second embodiment of the present invention.

【図８】本発明の第２の実施形態における半導体チップ
を示す断面図である。FIG. 8 is a sectional view showing a semiconductor chip according to a second embodiment of the present invention.

【図９】本発明の第２の実施形態における配線基板を示
す平面図である。FIG. 9 is a plan view showing a wiring board according to a second embodiment of the present invention.

【図１０】本発明の第２の実施形態における配線基板を
示す断面図である。FIG. 10 is a cross-sectional view illustrating a wiring board according to a second embodiment of the present invention.

【図１１】本発明の第３の実施形態における半導体装置
を示す断面図である。FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

【図１２】本発明の第３の実施形態における半導体チッ
プを示す平面図である。FIG. 12 is a plan view illustrating a semiconductor chip according to a third embodiment of the present invention.

【図１３】本発明の第３の実施形態における半導体チッ
プを示す断面図である。FIG. 13 is a sectional view showing a semiconductor chip according to a third embodiment of the present invention.

【図１４】本発明の第３の実施形態における配線基板を
示す平面図である。FIG. 14 is a plan view showing a wiring board according to a third embodiment of the present invention.

【図１５】本発明の第３の実施形態における配線基板を
示す断面図である。FIG. 15 is a sectional view showing a wiring board according to a third embodiment of the present invention.

【図１６】本発明の実施形態における配線基板の製造方
法における基材を示す断面図である。FIG. 16 is a cross-sectional view showing a base material in the method for manufacturing a wiring board according to the embodiment of the present invention.

【図１７】本発明の実施形態における配線基板の製造方
法における緩和層を形成した状態を示す断面図である。FIG. 17 is a cross-sectional view showing a state in which a relaxation layer is formed in the method for manufacturing a wiring board according to the embodiment of the present invention.

【図１８】本発明の実施形態における配線基板の製造方
法におけるスルーホールを形成した状態を示す断面図で
ある。FIG. 18 is a cross-sectional view showing a state in which a through hole is formed in the method of manufacturing a wiring board according to the embodiment of the present invention.

【図１９】本発明の実施形態における配線基板の製造方
法におけるスルーホール内にエポキシ樹脂を充填した状
態を示す断面図である。FIG. 19 is a cross-sectional view showing a state in which an epoxy resin is filled in through holes in the method of manufacturing a wiring board according to the embodiment of the present invention.

【図２０】本発明の実施形態における配線基板の製造方
法における配線を形成した状態を示す断面図である。FIG. 20 is a cross-sectional view showing a state in which wiring is formed in the method of manufacturing a wiring board according to the embodiment of the present invention.

【図２１】本発明の実施形態における配線基板の製造方
法における電極、パッド電極を形成した状態を示す断面
図である。FIG. 21 is a cross-sectional view showing a state where electrodes and pad electrodes are formed in the method for manufacturing a wiring board according to the embodiment of the present invention.

【図２２】本発明の実施形態における配線基板の製造方
法におけるハンダ層を形成した状態を示す断面図であ
る。FIG. 22 is a cross-sectional view showing a state in which a solder layer is formed in the method of manufacturing a wiring board according to the embodiment of the present invention.

【図２３】従来技術における半導体装置を示す断面図で
ある。FIG. 23 is a cross-sectional view showing a semiconductor device according to a conventional technique.

【図２４】従来技術における半導体装置を示す断面図で
ある。FIG. 24 is a cross-sectional view showing a semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ 封止樹脂 ７ 緩和層 １０ パッド電極 １１ ハンダボール １６ 電極 １７ 配線基板 １９ 電極 ３３ 突起電極 ４８ ハンダ層 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Sealing resin 7 Relaxation layer 10 Pad electrode 11 Solder ball 16 Electrode 17 Wiring board 19 Electrode 33 Projection electrode 48 Solder layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 回路形成面に形成した外部引き出し用の
電極をもつ半導体チップと、半導体チップを搭載する側
には半導体チップの電極と電気的接続を行うための電極
や配線を配し、外部の配線基板と電気的な接続を行う側
に基材の上に基材よりも弾性率が低い材料を使った緩和
層を形成し、その上に配線や外部の配線基板と電気的接
続を行うパッド電極を形成した配線基板と、外部の配線
基板と電気的接続を行うパッド電極上にはハンダで形成
した突起端子と、少なくとも半導体チップと電気的接続
した接続部を封止樹脂で覆われていることを特徴とする
半導体チップを配線基板にフェイスアップで搭載する半
導体装置。1. A semiconductor chip having an external lead-out electrode formed on a circuit forming surface, and an electrode and a wiring for making electrical connection with an electrode of the semiconductor chip are arranged on a side on which the semiconductor chip is mounted. Form a relaxation layer using a material with a lower elastic modulus than the base material on the side where the electrical connection with the wiring board is made, and then make electrical connection with wiring and external wiring boards on it The wiring board on which the pad electrode is formed, the protruding terminal formed of solder on the pad electrode for making an electrical connection with the external wiring board, and at least the connection part electrically connected to the semiconductor chip are covered with a sealing resin. A semiconductor device wherein a semiconductor chip is mounted face-up on a wiring board. 【請求項２】 回路形成面に形成した外部引き出し用の
電極に突起電極をもつ半導体チップと、外部の配線基板
と電気的な接続を行う側のみあるいは半導体チップを搭
載する側と外部の配線基板と電気的な接続を行う側の両
方に基材の上に基材よりも弾性係数が大きい材料を使っ
た緩和層を形成しその上に半導体チップを搭載する側に
は半導体チップの突起電極と電気的接続を行うための電
極と配線をを配し、外部の配線基板と電気的な接続を行
う側には外部の配線基板と電気的接続を行うパッド電極
や配線を形成した配線基板と、外部の配線基板と電気的
接続を行うパッド電極上にはハンダで形成した突起端子
と、半導体チップと配線基板との間隙に封止樹脂を注入
したことを特徴とする半導体チップを配線基板にフェイ
スダウンで搭載する半導体装置。2. A semiconductor chip having a protruding electrode on an external lead electrode formed on a circuit forming surface, and only a side for electrically connecting to an external wiring board or a side on which the semiconductor chip is mounted and an external wiring board On both the sides that make electrical connections, a relaxation layer using a material with a larger elastic modulus than the base material is formed on the base material, and the semiconductor chip is mounted on the side on which the semiconductor chip is mounted. Arranging electrodes and wiring for electrical connection, a wiring board on which pad electrodes and wiring for electrically connecting with the external wiring board are formed on the side for making electrical connection with the external wiring board, A protruding terminal formed of solder is formed on a pad electrode for making an electrical connection with an external wiring board, and a sealing resin is injected into a gap between the semiconductor chip and the wiring board. Mount with down Semiconductor device. 【請求項３】 配線基板の半導体チップを搭載する側の
電極には、ハンダ層を形成してあることを特徴とする請
求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein a solder layer is formed on an electrode of the wiring board on which the semiconductor chip is mounted. 【請求項４】 基材の片面または両面に基材よりも弾性
係数が大きい材料を使った緩和層を形成する工程と、基
材に緩和層を形成した基板にこれらを貫通するスルーホ
ールを形成する工程と、スルーホールを含め配線を形成
する工程と、半導体チップの電極と電気的接続を行うた
めの電極と外部の配線基板と電気的な接続を行うための
パッド電極を形成する工程と、半導体チップの電極と電
気的接続を行うための電極のみハンダ層を形成する工程
とを有することを特徴とする半導体チップを搭載する配
線基板の製造方法。4. A step of forming a relaxation layer using a material having a larger elastic modulus than that of the base material on one or both surfaces of the base material, and forming a through hole penetrating these through the base material having the relaxation layer formed on the base material. Forming a wiring including a through hole, forming an electrode for making an electrical connection with an electrode of a semiconductor chip, and forming a pad electrode for making an electrical connection with an external wiring board, Forming a solder layer only on an electrode for making electrical connection with an electrode of the semiconductor chip.
JP12676297A 1997-05-16 1997-05-16 Manufacturing method of wiring board mounting semiconductor chip Expired - Fee Related JP3795628B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12676297A JP3795628B2 (en) 1997-05-16 1997-05-16 Manufacturing method of wiring board mounting semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12676297A JP3795628B2 (en) 1997-05-16 1997-05-16 Manufacturing method of wiring board mounting semiconductor chip

Publications (2)

Publication Number Publication Date
JPH10321750A true JPH10321750A (en) 1998-12-04
JP3795628B2 JP3795628B2 (en) 2006-07-12

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423581B1 (en) * 1999-06-18 2002-07-23 Micron Technology, Inc. Method of fabricating an encapsulant lock feature in integrated circuit packaging
JP2007019275A (en) * 2005-07-07 2007-01-25 Rohm Co Ltd Substrate, semiconductor device, and manufacturing method thereof
US7256495B2 (en) 2003-02-24 2007-08-14 Samsung Electro-Mechanics Co., Ltd. Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same
GB2444775A (en) * 2006-12-13 2008-06-18 Cambridge Silicon Radio Ltd Chip mounting
JP2015090891A (en) * 2013-11-05 2015-05-11 株式会社ザイキューブ Semiconductor device and manufacturing method of the same

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JP2019204921A (en) * 2018-05-25 2019-11-28 凸版印刷株式会社 Glass circuit substrate and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423581B1 (en) * 1999-06-18 2002-07-23 Micron Technology, Inc. Method of fabricating an encapsulant lock feature in integrated circuit packaging
US7256495B2 (en) 2003-02-24 2007-08-14 Samsung Electro-Mechanics Co., Ltd. Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same
JP2007019275A (en) * 2005-07-07 2007-01-25 Rohm Co Ltd Substrate, semiconductor device, and manufacturing method thereof
GB2444775A (en) * 2006-12-13 2008-06-18 Cambridge Silicon Radio Ltd Chip mounting
GB2444775B (en) * 2006-12-13 2011-06-08 Cambridge Silicon Radio Ltd Chip mounting
US9177885B2 (en) 2006-12-13 2015-11-03 Cambridge Silicon Radio Limited Chip mounting
US9659894B2 (en) 2006-12-13 2017-05-23 Qualcomm Technologies International, Ltd. Chip mounting
JP2015090891A (en) * 2013-11-05 2015-05-11 株式会社ザイキューブ Semiconductor device and manufacturing method of the same

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