JP2015090891A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfy needs of an art to improve electric connection reliability because large distortion caused by a thermal expansion coefficient difference at an interface between an LSI and a PCB, which occurs when the semiconductor LSI having a through electrode is connected to the PCB and an operation temperature increases becomes prominent as the chip size of the semiconductor LSI is increased thereby to break electric connection between the semiconductor LSI and the PCB.SOLUTION: A semiconductor device comprises: a through electrode arranged on a semiconductor substrate; a land-shaped first electrode which is formed on a first principal surface of the semiconductor substrate and electrically connected to the through electrode; a wiring pattern connected to the first electrode; and a ball-shaped second electrode formed on the wiring pattern in which: (1) a region including the first electrode and the wiring pattern are arranged on a distortion absorption layer arranged on the first principal surface; and (2) the first electrode and the wiring pattern are formed by a seed metal layer and a conductive layer.

Description

The present invention relates to a device structure, a mounting structure, and a manufacturing method thereof related to three-dimensional stacked mounting of a semiconductor LSI.

Against the background of advances in semiconductor industry technology, the demand for higher integration in semiconductor LSIs does not stop. In order to promote high integration, there are methods for reducing the size of a unit element (transistor) or increasing the chip size. However, new development of manufacturing technology associated with miniaturization requires enormous resources. As the chip size increases, the design and inspection of large-scale circuits has become complicated. Furthermore, if the chip size is large, the length of the signal transmission line becomes long, and the limit of speeding up occurs.

  In order to eliminate these drawbacks, a structure in which a plurality of chips are stacked in the height direction, that is, a three-dimensional structure has been proposed. In this structure, a through electrode (Through Via) for electrically connecting the front and back surfaces of the chip (in the case of a silicon substrate, it is referred to as TSV or Through Silicon Via) is used. In this paragraph, the structure of the through electrode will be outlined using a chip size package (CSP) as an example. (1) A “through hole” is formed from the main surface side where the circuit of the semiconductor LSI is not arranged toward an electrode (for example, a bonding pad) constituting the circuit, and (2) insulation is provided in a side wall region of the hole. Forming a layer, (3) filling the hole with a conductor, or attaching a conductor to the side wall of the hole to form a through electrode, and (4) electrically connecting the through electrode to the main surface side. The structure can be realized by a process of forming an electrode pattern and (5) forming a conductive ball (for example, a solder ball) connected to the electrode pattern. In this example, the completed CSP can be directly mounted on a printed circuit board (PCB) (which is a “wiring board”) via the conductive balls, thereby achieving a reduction in size and cost of the system. Is possible.

  A device suitable for three-dimensional stacking is manufactured by directly processing a semiconductor LSI according to the previous paragraph. On the other hand, there is a method of stacking an “intermediate substrate” called an “interposer” on a semiconductor LSI. Such an interposer is composed of a silicon substrate or the like, and generally has a wiring pattern (also referred to as a “rewiring pattern”) formed on both sides thereof, and through electrodes that electrically connect the front and back surfaces of the substrate are arranged. . The interposer and the semiconductor LSI are stacked, and the interposer side is mounted on the PCB.

  Although the two configuration examples outlined in the above paragraph are being put into practical use, it is known that connection reliability deteriorates due to thermal history. This is because the semiconductor LSI (or interposer) and the PCB have different coefficients of thermal expansion, and the stress generated in the lateral direction due to the thermal history (for example, the high temperature atmosphere and the low temperature atmosphere are repeated) destroys the connection portion.

In order to prevent such connection reliability deterioration, a structure shown in FIG. 11 has been proposed. FIG. 4 is a diagram published in FIG. In the figure, a part of the wiring pattern (chrome layer 16) drawn from the electrode (12), the copper layer (20), the pedestal (24), and the solder ball (26) are formed on the resin layer (14). Located at the top. This resin layer is made of polyimide or the like and functions as a “stress relaxation layer”, and is supposed to prevent the connection portion from being broken due to the lateral stress described above. FIG. 12 is a diagram published in FIG. 5 of Patent Document 1 cited below. In the figure, the wiring (3) from the electrode (12) is connected to the external electrode (5) (corresponding to the solder ball 26), but from the middle of the wiring (3) (additionally indicated by a circle in the figure) It is shown that it is arranged on the upper part of the stress relaxation layer (7) (same as the resin layer (14)). In such a configuration, there is a possibility that the connection portion can be prevented from being broken. However, since the region of the electrode (12) is not taken measures against the stress, the extremely large stress is prevented from being generated around the electrode (12). There is a disadvantage that destruction is induced.

  About the photosensitive resin composition arrange | positioned in area | regions, such as a wiring pattern, it is disclosed by the following cited patent document 2, for example. In claim 1 of the document 2, “the photosensitive resin composition is (1) a bismaleimide compound having a cyclic imide bond and a divalent hydrocarbon group derived from dimer acid, (2) a photopolymerization initiator”. And (3) a silicon compound having four or more alkoxy groups bonded to a silicon atom ”. This resin composition has a small Young's modulus (tensile modulus) after curing of 2 GPa or less. Further, it is characterized in that a fine pattern can be formed with a relatively low exposure amount and the temperature for thermosetting is relatively low. Such a photosensitive resin composition is a good example for the present invention.

Japanese Patent No. 4895054 Japanese Patent Application Publication No. 2013/083958 Specification

As described above, when a semiconductor LSI having a through electrode is connected to a PCB, it is necessary to develop a technique for ensuring high connection reliability in consideration of the difference in coefficient of thermal expansion. When there is a difference in the coefficient of thermal expansion, when the operating temperature rises, a lateral stress is generated at the interface between the semiconductor LSI and the PCB, and a large strain is generated at the interface. Such distortion becomes significant as the chip size of the semiconductor LSI increases, and the electrical connection between the semiconductor LSI and the PCB is broken. A similar phenomenon occurs even in a configuration in which interposers are stacked. As an example, the coefficient of thermal expansion is
Silicon: 2.6 × 10 ⁻⁶ PCB: 14 × 10 ⁻⁶
It is. Assuming that the chip size of the semiconductor LSI is 5 mm □ and a temperature rise of 100 ° C., a strain of 5.7 μm (in the direction in which the semiconductor LSI is stretched) occurs when the temperature rises. On the other hand, Young's modulus (elastic modulus) is silicon: 130 GPa
Copper (assuming wiring material): 129.8 GPa Solder ball: about 30 GPa
PCB: about 28GPa
Therefore, the distortion is concentrated on the solder ball. As a result, cracks occur in the solder balls and the electrical connectivity is destroyed. Further, since the wiring pattern is as thin as several tens of μm, there is a risk that the wiring pattern is disconnected due to the distortion. In particular, when the wiring pattern is shaped to “climb over” the uneven area on the surface of the semiconductor LSI, the “shoulder” portion of the wiring pattern (generally the thickness is locally reduced and the mechanical strength is reduced. Is known to do). In FIG. 12, a region to which a circle is added corresponds to the “shoulder” portion.

  Although the chip size of a semiconductor LSI is continually miniaturized, there is a limit to the miniaturization of an image sensor due to light sensitivity and resolution. Currently, image sensors as small as 2 mm □ to 3 mm □ for devices such as smartphones are in practical use. However, in order to obtain high sensitivity and high resolution, the chip size must be increased, and a large-sized chip of 24 × 36 mm is adopted in a high-quality single-lens reflex digital camera. As the chip size increases, the effect of the above-described strain increases, and a strain-absorbing structure is essential for a chip-size image sensor whose side length exceeds about 5 mm.

  Semiconductor LSIs are often stacked in application fields other than image sensors. For example, there is a case where a plurality of LSIs are arranged in a plane (arranged in a two-dimensional plane) and stacked on the upper surface of a large-area semiconductor LSI, and this stacked structure is made “one system”. In such a structure, since the chip size of the lowermost semiconductor LSI is large, when the structure is mounted on a PCB, the above-described strain absorption structure is essential. Furthermore, even if a strain absorbing structure is introduced, the ease of manufacturing of this structure and the mechanical strength (for example, maintaining local adhesion with a semiconductor device) are also important development issues.

Technology development to reduce the distortion caused by the difference in thermal expansion coefficient between the semiconductor LSI (or interposer) and PCB, and to avoid the destruction of electrical connectivity with solder balls and wiring patterns as described in the previous paragraph Is strongly demanded.

A through electrode electrically connected to a conductor disposed on a second main surface side which is one surface of the semiconductor substrate; a first main surface which is the other surface of the semiconductor substrate; and the through electrode A land-like first electrode electrically connected to the electrode; a wiring pattern connected to the first electrode; and the wiring pattern in a region where the first electrode on the first main surface is not disposed. In the semiconductor device including the ball-shaped second electrode formed on the upper portion of (1), (1) the region including the first electrode and the wiring pattern are disposed on the first main surface (2) Both the first electrode and the wiring pattern are composed of a seed metal layer and a conductive layer disposed on the surface of the seed metal layer, and (3) The strain absorbing layer is composed of a photosensitive resin composition, and (4) the sensitivity Young's modulus after curing of sexual resin composition to be a value that does not exceed 0.5 GPa.

  The “semiconductor device” used in this specification includes both the above-described CSP configuration (a semiconductor LSI can be directly processed and mounted on a PCB) and an interposer configuration. The CSP configuration is not limited to an image sensor, and may be a signal processing LSI, a storage device, a communication LSI, or the like. Further, the size of one side of the semiconductor device chip may exceed about 5 mm.

  In addition, in the “connection” between the “land-shaped first electrode” and the “wiring pattern” described in the preceding paragraph, “both are mechanically connected and consequently both are electrically connected”. It includes such “connections”. For example, the land-like first electrode and the wiring pattern are in contact with each other in the same plane, or the latter is disposed above the former. Furthermore, both may constitute a common component, and may be simply divided into regions and given names. Furthermore, in both manufacturing processes, they may be manufactured in different processes or may be manufactured in the same process.

  In the above-described means, the first electrode, the wiring pattern, and the second electrode (in a strict sense, the state in which the wiring pattern is sandwiched) are all disposed on the strain absorbing layer. It is characteristic that it is. That is, the wiring pattern is arranged along a substantially flat surface, and does not get over the uneven “shoulder” portion.

In this paragraph, the strain absorbing layer described above is described. The inventors of the present invention evaluated the reliability of electrical connection due to thermal history using the photosensitive resin composition described in Patent Document 2. The Young's modulus of the composition used here is a grade of 0.1 to 0.5 GPa. As a result, it was possible to obtain high electrical connection reliability as compared with the configuration not using this resin composition. Specifically, as a result of performing a temperature cycle test between −30 ° C. and + 80 ° C.,
When the resin composition is not used: Disconnection occurs at 1500 cycles Resin composition (thickness: 10 μm or more): There was no deterioration in electrical connectivity even at 4000 cycles or more.

In this paragraph, the “seed metal layer and conductive layer” and “ball-shaped second electrode” are described. The seed metal layer has a function of increasing the adhesion strength between the conductive layer and the base, and is formed by a known technique such as sputtering using titanium or the like, and the thickness thereof does not exceed several hundred nm. . The seed metal layer may have a multilayer structure made of titanium, platinum, platinum, or the like. The conductive layer is disposed on the surface of the seed metal layer and is formed by a known method such as electrolytic plating, electroless plating, vapor deposition, CVD, printing, etc., and its thickness does not exceed 100 μm. The conductive layer may be a metal such as copper or aluminum, a conductive semiconductor such as polycrystalline silicon, or a multilayer structure made of these. The “ball-shaped second electrode” is processed into a ball shape by heat-treating a solder paste or the like formed by a known method such as screen printing.

  The strain absorbing layer described above was bonded to (1) a bismaleimide compound having a cyclic imide bond and a divalent hydrocarbon group derived from dimer acid, (2) a photopolymerization initiator, and (3) bonded to a silicon atom. A photosensitive resin composition containing a silicon compound having 4 or more alkoxy groups is used, and the Young's modulus after curing of the photosensitive resin composition is set to a value not exceeding 0.5 GPa.

  In addition, the photosensitive resin composition described in the previous paragraph is equivalent to the composition described in claim 1 of the cited Patent Document 2 described above. In the document 2, the Young's modulus after the effect is set to “2 GPa or less”. As described above, since a grade product of “0.1 to 0.5 GPa” was used in the experiments by the inventors, the value in the previous paragraph is “a value not exceeding 0.5 GPa”.

(1) a step of disposing a through hole for a through electrode in a semiconductor substrate constituting a semiconductor device, (2) a step of disposing a strain absorbing layer on a first main surface of the semiconductor substrate, and (3) the through hole A step of filling the hole with a conductor layer or attaching a conductor layer to the inner wall of the through hole to form a through electrode; and (4) being connected to the through electrode and disposed on the surface of the strain absorbing layer. Forming a land-like first electrode to be formed; (5) forming a wiring pattern connected to the first electrode on the surface of the strain absorbing layer; and (6) a surface of the wiring pattern. A semiconductor device is manufactured in a process including a step of disposing a ball-shaped second electrode in a region where the first electrode is not disposed.

  In the manufacturing method described in the previous paragraph, (3) to (5) may be a single step. For example, in the step of disposing a conductor layer on the first main surface side, (1) a conductor layer is disposed in the through hole to form a through electrode, and at the same time, (2) the conductor layer has the land-like shape. It is an example which forms a 1st electrode and the said wiring pattern. The conductor layer includes a seed metal layer and a conductive layer.

Note that (3) in the previous paragraph is “to provide conductivity to the through-hole to form a through-electrode”. In general, the through hole is often filled with a conductor layer, but a “hollow structure” in which the conductor layer is attached only to the inner wall of the through hole may be used.

  According to the present invention, there is no deterioration in electrical connectivity due to a difference in thermal expansion coefficient, and a highly reliable mounting is possible even in a semiconductor LSI having a large chip size, and a wiring pattern does not go over an uneven area on the surface of a semiconductor device. And the semiconductor device which has a wiring pattern with high adhesiveness was obtained.

It is a figure which shows the structure of a semiconductor device. <Example 1> It is a figure which shows the structure which mounted the semiconductor device (semiconductor LSI) in PCB. <Example 2> It is a figure which shows the evaluation result of electrical connection reliability. It is a figure which shows the structure which mounted the semiconductor device (interposer) in PCB. <Example 3> It is a figure which shows the manufacturing method of a semiconductor device. <Example 4> It is a figure which shows the improved manufacturing method of a semiconductor device. <Example 5> It is a figure which shows the improved manufacturing method of a semiconductor device. <Example 6> It is a figure which shows the improved manufacturing method of a semiconductor device. <Example 7> It is a figure which shows the other structure when a semiconductor device is mounted. <Example 8> It is a figure which shows the other structure when a semiconductor device is mounted. <Example 9> It is a figure which shows a prior art example. It is a figure which shows a prior art example.

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration example of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view seen from above. In the figure, only basic components are displayed, and a semiconductor device is conceptually shown. In the figure, reference numeral 101 denotes a semiconductor substrate made of silicon or the like, and one main surface (the lower main surface in the figure is referred to as a “second main surface”) is made of an oxide film or the like. The insulating layer 102 is covered. A transistor 103 and the like are disposed on the substrate 101. Conductors 104 and 105 made of a conductor such as polysilicon or metal are disposed inside the insulating layer 102. In the figure, the corresponding 104 corresponds to the gate electrode of the transistor. The reference numeral 105 denotes a “conductor disposed on the second main surface side”, and more specifically corresponds to a conductor (for example, a bonding pad) that transmits and receives signals. The 105 is led out to the “first main surface” (the upper main surface in the figure) which is the other main surface of the substrate by the through electrode 106 and connected to the “land-shaped first electrode” 107. Has been. Reference numeral 108 arranged around the through electrode and on the first main surface side is an insulating layer for electrical insulation. The 107 is connected to the wiring pattern 109. In this “connection”, 107 and 109 are integrated (made simultaneously in the same manufacturing process), and each area is given a name. Further, in the wiring pattern 109, a “ball-shaped second electrode” 110 formed on the upper portion of the 107 in a region where the 107 is not disposed. With this configuration, the conductor 105 arranged on the second main surface side of the substrate is electrically connected to the 110.

  The through electrode (106), “first electrode” (107), and “wiring pattern” (109) described in the previous paragraph are composed of a seed metal layer made of titanium or the like and a conductive layer made of copper or the like. Further, it has a multilayer structure of two or more layers. The seed metal layer is formed by a known method such as sputtering of titanium or the like, and the thickness thereof does not exceed several hundred nm. The seed metal layer may have a multilayer structure made of titanium, platinum, platinum, or the like. The conductive layer is disposed on the surface of the seed metal layer and is formed by a known method such as electrolytic plating, electroless plating, vapor deposition, CVD, printing, etc., and its thickness does not exceed 100 μm. The conductive layer may be a metal such as copper or aluminum, a conductive semiconductor such as polycrystalline silicon, or a multilayer structure made of these. The “second electrode” (110) is made of solder such as a mixture of tin, silver, and copper. The 110 is processed into a ball shape by heat-treating a solder paste or the like formed by a known method such as screen printing. The solder resist layer 111 is disposed so that the heat treatment process allows the 110 to be formed into a “ball shape” without spreading.

In FIG. 1, reference numeral 112 denotes a strain absorbing layer, which is made of, for example, a photosensitive resin composition described in Patent Document 2. In the configuration shown in the figure, all of the 107, 109, and 110 are arranged above the 112. Note that the 110 is arranged above the 112 via the wiring pattern 109.

  FIG. 1 shows a case where the semiconductor device is a “semiconductor LSI”. However, the semiconductor device may be an “interposer”. In such a case, the transistor 103 (including 104) or the like is not integrated on the substrate 101. On the other hand, the conductor 105 is often arranged to electrically connect the front and back surfaces of the interposer.

FIG. 2 shows a second embodiment of the present invention and shows a configuration in which the semiconductor device described up to the previous paragraph is mounted on a PCB. In the figure, the same reference numerals as those in FIG. 1 denote the same components. Further, in the figure, the case where there are two “second electrodes” is illustrated. In the figure, reference numeral 120 denotes the above-described semiconductor device (semiconductor LSI), which is displayed upside down from FIG. Reference numeral 121 denotes a PCB such as FR-4, on which a pattern 122 formed of copper foil or the like is arranged, and a position facing the “ball-shaped second electrode” 110 provided on the 120 Is arranged. After the relative position with respect to 121 is adjusted, 120 is electrically connected to 122 by melting 110 in a known heat treatment process. Reference numeral 123 denotes an underfill layer poured to strengthen the electrical connection.

In the configuration of FIG. 2, when the operating temperature rises, stress is generated in the lateral direction (on the drawing) due to the difference in thermal expansion coefficient between 120 and 121. In the case of a temperature rise, the PCB is greatly deformed in the lateral direction, and therefore 120 is distorted into a concave shape. Considering that the “ball-shaped second electrode” 110 is a material such as solder and the Young's modulus is smaller than the Young's modulus of the substrate 101 (made of silicon) and the wiring pattern 109 (made of copper), the strain Will concentrate on the 110. Such strain causes cracks in the 110, and the electrical connection is broken. Although the possibility of destruction may be low immediately after the mounting process, the possibility of destruction increases as the thermal history passes.

However, since the strain absorption layer 112 is present in the configuration of FIG. 2 and its Young's modulus is a small value not exceeding 0.5 GPa, the above-described strain can be reduced. That is, the expansion / contraction in the lateral direction caused by the difference in the thermal expansion coefficient described above is absorbed by the deformation of the 112 in the thickness direction (perhaps the thickness is reduced). As a result, the strain of 110 is extremely reduced, the 120 is not distorted, and the electrical connection is not broken even if the thermal history is repeated.

FIG. 3 shows evaluation results of electrical connection reliability actually measured by the inventors. The evaluation target is a sample in the mounting state illustrated in FIG. 2, and 10 × 9 “ball-shaped second electrodes” are two-dimensionally arranged on the semiconductor device 120 at a pitch of 0.5 mm, A daisy chain is formed between them. The chip size of the semiconductor device is 5.6 mm × 4.9 mm. The material of the strain absorbing layer used for the evaluation was the photosensitive resin composition described in the cited patent document 2, and was obtained from Nippon Steel & Sumikin Chemical Co., Ltd., the applicant of the patent. The used photosensitive resin composition is a grade product having a Young's modulus of 0.1 to 0.5 GPa. In FIG. 3A, the horizontal axis represents the number of cycles of thermal history (-30 ° C. to + 80 ° C.), and the vertical axis represents the total resistance value of the daisy chain. In FIG. 6A, the parameter “t” is the thickness of the strain absorbing layer 112, and “t = 0 μm” is the case where there is no strain absorbing layer. As is clear from the figure, when there is no strain absorbing layer, the total resistance value increases after 1500 thermal histories, and the electrical connection is broken. A sectional view of the “ball-shaped second electrode” in this state is shown in FIG. In FIG. 2B, the upper side is a semiconductor device and the lower side is a PCB, and it is shown that a crack is generated on the semiconductor device side. On the other hand, as shown in FIG. 3A, the connection reliability is ensured as the thickness of the strain absorbing layer increases even if the thermal history cycle increases. If a thermal history of 4000 times is targeted, it can be seen that a thickness of at least 10 μm, more preferably more than 15 μm is required. From the evaluation results, the effects of the present invention were clarified quantitatively.

  FIG. 4 is a diagram showing a mounting configuration on a PCB when the semiconductor device is an “interposer” according to a third embodiment of the present invention. In the figure, the same numbers as those in FIGS. 1 and 2 indicate the same components. FIG. 4 illustrates the case where there are two “second electrodes” (110). In the figure, reference numeral 150 denotes an interposer which is displayed upside down as in FIG. Reference numeral 151 denotes a semiconductor LSI, which is electrically connected via a connection terminal 152 to a wiring group (not shown) arranged on the “second main surface” of 150 (the upper surface of 150 in the figure). . That is, the interposer 150 is stacked on the semiconductor LSI (151). Reference numeral 121 denotes a PCB such as FR-4, on which a pattern 122 formed of copper foil or the like is arranged, and a position facing the “ball-shaped second electrode” 110 provided on the 150 Is arranged. After the relative position with respect to 121 is adjusted, 120 is electrically connected to 122 by melting 110 in a known heat treatment process. Reference numeral 123 denotes an underfill layer poured to strengthen the electrical connection.

Also in the third embodiment illustrated in FIG. 4, since the strain absorbing layer 132 exists, the strain caused by the difference in thermal expansion coefficient between the PCB 121 and the interposer 150 can be avoided.

FIG. 5 is a diagram showing a method of manufacturing a semiconductor device (semiconductor LSI), which is Embodiment 4 of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same components. A manufacturing method will be described in detail using the structure shown in FIG. In FIG. 2A, a conductor 105 is buried in the insulating layer 102 on the second main surface side of the substrate. In FIG. 4B, a photoresist (PR) is applied to the first main surface side of the substrate, and patterning for forming a through electrode is performed. Reference numeral 130 denotes a patterned PR layer having an opening in a region where the through electrode is formed. In FIG. 6C, through holes 131 are formed by a known method such as reactive ion etching (RIE) using 130 as a mask. By switching the RIE atmosphere gas, the substrate 101 and the insulating layer 102 are etched, and the first main surface side of the conductor 105 is exposed. In FIG. 6D, after the PR layer 130 is removed, an insulating layer 108 (generally a silicon oxide layer) is deposited by a known method such as chemical vapor deposition (CVD). The purpose of depositing 108 is to provide electrical insulation between the inner wall of the through hole 131 and the first main surface. Due to the characteristic of CVD, the deposition thickness on the first main surface (the upper surface in the figure) is larger than the deposition thickness on the inner wall of the through hole. Further, in this deposition step, an insulating layer is also deposited on the surface of the conductor 105 (which becomes the bottom of the through hole), so that only this portion of the insulating layer is removed by the technique such as RIE described above.

  In FIG. 5E, a strain absorbing layer is deposited on the first main surface side of the substrate, and patterning is performed. In this deposition, the photosensitive resin composition (liquid) is applied and patterned by a PR process. Reference numeral 132 denotes a patterned strain absorbing layer. By the patterning, a strain absorption layer is formed in a region including the region where the “land-shaped first electrode” and the “wiring pattern” are arranged (details will be described later). In FIG. 5F, a conductor layer 133 is formed on the first main surface side including the inner wall of the through hole. For example, as a first step, a seed metal layer such as titanium is deposited (deposited on the entire surface on the first main surface side). There is no particular limitation on the thickness, but generally the thickness does not exceed several hundred nm, and is deposited by a known method such as sputtering. Subsequently, a photosensitive film such as a dry film is applied to the surface of 132 to perform patterning. This patterning is for selectively forming a conductive layer in subsequent steps. Subsequently, a conductive layer made of a metal such as copper is formed by electroless plating, electrolytic plating, vapor deposition, printing, or the like. After removing the photosensitive film such as the dry film described above, the exposed seed metal layer is removed by etching to form a conductor layer. In this embodiment, the “conductor layer” has a two-layer structure (generally a multilayer structure) of a “seed metal layer” and a “conductive layer”. FIG. 5F shows an example in which “the through hole is filled with a conductor layer”, but the present invention is not limited to this. A conductor layer may be formed on the bottom and the side wall of the through-hole and may be in a “hollow state”. The thickness of the conductive layer made of a metal such as copper is not particularly limited, but generally does not exceed 100 μm. At the stage where the conductive layer (seed metal layer + conductive layer) is formed (figure (f)), the "land-shaped first electrode" (107) and the "wiring pattern" (109) are the same. It is formed at the same time in the process. In FIG. 8F, the through hole 131 in which the conductor layer 133 is formed is the same component as the through electrode 106 described above.

  In FIG. 5G, a region excluding a partial region of the wiring pattern 109 (a region where the “ball-shaped second electrode” is arranged in the next step) is formed with a patterned solder resist 134. Cover. In FIG. 8H, the ball-shaped second electrode 110 is formed by heat-treating a solder paste or the like formed by a known method such as screen printing.

  FIG. 5 illustrates the case where the semiconductor device is a semiconductor LSI. When the semiconductor device is an interposer, it is manufactured similarly.

  The manufacturing method shown in FIG. 5 can be summarized as follows: (1) a step of arranging a through hole (131) for a through electrode in a semiconductor substrate constituting a semiconductor device; and (2) a first main surface of the semiconductor substrate. A step of disposing a strain absorbing layer (132), (3) a step of imparting conductivity to the through hole to form a through electrode (106), and (4) a connection to the through electrode and the absorption of the strain. Forming a land-like first electrode (107) disposed on the surface of the layer; and (5) forming a wiring pattern (109) connected to the first electrode on the surface of the strain absorbing layer. And (6) a step of disposing a ball-shaped second electrode (110) in a region on the surface of the wiring pattern where the first electrode is not disposed. It became possible.

  In this embodiment, the steps (3) to (5) described in the previous paragraph are a single identical step. You may manufacture a semiconductor device in a process different from these processes, respectively.

  5, different patterning steps (here, “two steps”) are used to form the through holes 131 and the strain absorbing layer 132. Exposure using a mask for these patterning steps. Although the process is used, a margin for alignment is necessary, that is, as shown by the circle 136 in FIG.5 (e), the opening size of the strain absorbing layer (the second patterning process) is the size of the through hole. Since the alignment margin limits the pitch of the through holes, the plurality of conductors 105 may be arranged in close contact with each other in order to limit the pitch of the through holes. However, this embodiment is effective when the above-mentioned alignment margin may be provided, which is more effective than the improved manufacturing method described later. Seth is there is an advantage of being simple and easy.

FIG. 6 shows a fifth embodiment of the present invention and shows an improved manufacturing method of a semiconductor device. In the present embodiment, a manufacturing method that eliminates the drawback (alignment margin) of the fourth embodiment described in the previous paragraph is shown. In the figure, the same reference numerals as those in FIGS. 1 to 5 denote the same components. In FIG. 1A, reference numeral 180 denotes a semiconductor device. In FIG. 6B, the strain absorbing layer 182 is formed on the upper surface (first main surface) 180, and patterning is performed so that an opening can be formed in the through hole. A through hole 131 is formed from this opening by RIE or the like, and the conductor 105 is exposed at the bottom of the 131. In FIG. 4D, an insulating layer 108 is formed on the side wall of the through hole and the surface of the strain absorbing layer 182. In this formation process, since the insulating layer is also attached to the bottom of the through hole, it is removed by a known method.

  In FIG. 6E, a part of the insulating layer 108 is left and the region 108 where a ball-shaped second electrode to be described later is disposed is etched away. In FIG. 5F, the conductor layer 133 is embedded in the through hole (becomes the through electrode 106), and at the same time, the conductor layer is formed on the surface of the strain absorbing layer. The conductor layer has a two-layer structure of “seed metal layer + conductive layer” as described above. FIG. 5F shows a patterned conductor layer. As a result, the conductor layer 133 on the surface of the strain absorbing layer constitutes the “land-shaped first electrode 107” and the “wiring pattern 109”. In FIG. 5G, a patterned solder resist layer 134 is formed, and in FIG. 9H, a ball-shaped second electrode 110 is formed.

  However, in the embodiment of FIG. 6, since only the strain absorption layer exists between the wiring pattern 109 and the substrate 101, the electrical insulation of the strain absorption layer may be a problem. For example, the substrate is at the ground potential and a high voltage signal flows through the wiring pattern. Such electrical insulation depends on the value of the high voltage and the conductivity of the strain absorbing layer, but there may be cases where the embodiment of FIG. 6 is not applied.

  FIG. 7 is a sixth embodiment of the present invention and shows a structure with improved electrical insulation described in the previous paragraph and a manufacturing method thereof. In the figure, the same reference numerals as those in FIGS. 1 to 6 denote the same components. FIGS. 7A to 7D are the same as FIGS. 6A to 6D. In FIG. 5E, a conductor layer 133 is formed on the insulating layer 108 disposed over the entire upper surface of the strain absorbing layer, and the “land-shaped first electrode 107” and the “ball-shaped first electrode” are formed. Two electrodes 109 "are formed. FIGS. 6F and 6G are the same as FIGS. 6G and 6H, respectively.

  In this embodiment, since the strain absorbing layer 182 and the insulating layer 108 exist between the conductor layer and the substrate 101, the problem caused by the electrical insulation as described above does not occur.

In this paragraph, we consider the case of such a configuration. The Young's modulus of each material in the configuration shown in FIG.
Silicon: 130 GPa SiO2 (assuming 108 material): 73 GPa
Copper (assuming wiring material): 129.8 GPa Solder ball: about 30 GPa
PCB: about 28GPa
It is. Considering these numerical values, “wiring pattern” and “ball-shaped second electrode region” have “slightly soft (= small Young's modulus)” SiO 2 (silicon oxide) immediately below the wiring pattern. In addition, a “soft” strain absorbing layer is disposed below. For this reason, the strain absorption mechanism is hardly affected by the presence of SiO2. Further, even if the SiO2 layer is ruptured (a lot of cracks are generated) due to strain, the conductivity of the wiring pattern is not affected.

  FIG. 8 is a diagram showing another method for manufacturing a semiconductor device with improved electrical insulation, which is Embodiment 7 of the present invention. In the figure, the same reference numerals as those in FIGS. 1 to 6 denote the same components. In FIG. 6A, the “underlying insulating layer 190” is disposed on the surface of the semiconductor device (180). FIG. 5B shows a state in which the strain absorption layer 192 is disposed and patterned. In FIG. 3C, a through hole 131 is opened from the opening provided in the strain absorbing layer by IRE or the like. In FIG. 4D, an insulating layer 194 is formed on the side wall of the through hole 131 and the surface of the strain absorbing layer 192. In FIG. 5E, a part of the insulating layer 194 is left, and the portion 194 in a region where a ball-shaped second electrode described later is disposed is etched away.

In FIG. 8F, the conductor layer 133 is embedded in the through hole (becomes the through electrode 106), and at the same time, the conductor layer is formed on the surface of the strain absorbing layer. The conductor layer has a two-layer structure of “seed metal layer + conductive layer” as described above. FIG. 5F shows a patterned conductor layer. As a result, the conductor layer 133 on the surface of the strain absorbing layer constitutes the “land-shaped first electrode 107” and the “wiring pattern 109”. In FIG. 5G, a patterned solder resist layer 134 is formed, and in FIG. 9H, a ball-shaped second electrode 110 is formed.

  In the embodiment shown in FIG. 8, since the “underlying insulating layer 190” is disposed below the wiring pattern 109, the above-described problem caused by the electrical insulation does not occur.

  The embodiment illustrated in FIGS. 5 to 8 is considered as a design factor of the semiconductor device. That is, it may be appropriately selected from these embodiments in consideration of the ease of the manufacturing process, the magnitude of the voltage flowing through the wiring pattern, the pitch of the through holes, and the like.

FIG. 9 shows an eighth embodiment of the present invention and shows another configuration when a semiconductor device is mounted. In the figure, the same numbers as those in FIGS. 1 and 2 indicate the same components. FIG. 5A shows a semiconductor device 170 having a strain absorbing layer 112 (only a part is shown), which has the same configuration as FIG. FIG. 5B shows a PCB 171 having a pattern 122 formed on the upper surface, and a strain absorbing layer 172 provided on the surface. FIG. 2C shows a structure in which a semiconductor device 170 and a PCB 171 are stacked. In FIG. 6C, as a result of lamination, the solder resist layer 111 and the strain absorbing layer 172 are in contact with each other, and both are integrated. As a result, the strain caused by the difference between the thermal expansion coefficients of the semiconductor device and the PCB is efficiently absorbed by the two strain absorption layers (112 and 172), so that there is an advantage that resistance to thermal history is increased.

FIG. 10 shows a ninth embodiment of the present invention and shows another configuration when a semiconductor device is mounted. In the figure, the same numbers as those in FIG. 9 indicate the same components. The difference between the present embodiment and the eighth embodiment described in the previous paragraph is in the configuration of the PCB in FIG. That is, in this embodiment, the strain absorbing layer 172 is disposed on the upper surface of the PCB (171), and the pattern 122 is formed on the upper surface of the 172. According to such a configuration, since the strain generated due to the difference in thermal expansion coefficient between the semiconductor device 170 and the PCB 171 can be absorbed on both the 170 side and the 171 side, the effect is great.

The present invention has been described with reference to the drawings. The present invention can be implemented in many different ways. For example, the present invention can be applied to a semiconductor LSI having a ball grid array structure or a semiconductor LSI having a chip size package structure in which an electronic circuit or a wiring pattern is formed only on one surface of a semiconductor substrate without having a through electrode. It will be readily appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description.

  According to the present invention, a technology has been developed that reduces electrical connection breakage due to a difference in thermal expansion coefficient when a semiconductor device such as a semiconductor LSI or an interposer is connected to a PCB, and ensures high connection reliability. The present invention is particularly effective when applied to image sensors and various LSIs having a relatively large chip size (for example, a chip size with a side length exceeding 5 mm). As an example, a remarkable effect can be obtained even when a plurality of LSIs are arranged in a plane on the upper surface of a large-area semiconductor LSI and stacked to form a single system. .

101 Substrate 102, 108, 190, 194 Insulating layer 103 Transistor 104, 105 Conductor 106 Through electrode 107 Land-shaped first electrode 109 Wiring pattern 110 Ball-shaped second electrode 111, 134 Solder resist 112, 132, 172, 182, 192 Strain absorbing layer 120, 170, 180 Semiconductor device 121, 171 Printed circuit board (PCB)
122 Pattern 123 Underfill layer 130 Photoresist (PR) layer 131 Through hole 133 Conductor layer 136 Circle 150 indicating alignment margin Interposer 151 Semiconductor LSI
152 Connection terminal

Claims (3)

A through electrode electrically connected to a conductor disposed on a second main surface side which is one surface of the semiconductor substrate; a first main surface which is the other surface of the semiconductor substrate; and the through electrode A land-like first electrode electrically connected to the electrode; a wiring pattern connected to the first electrode; and the wiring pattern in a region where the first electrode on the first main surface is not disposed. In a semiconductor device comprising a ball-like second electrode formed on the top of
The region including the first electrode and the wiring pattern are disposed on an upper portion of the strain absorbing layer disposed on the first main surface,
Both the first electrode and the wiring pattern are composed of a seed metal layer and a conductive layer disposed on the surface of the seed metal layer,
The strain absorbing layer is composed of a photosensitive resin composition,
A semiconductor device, wherein the Young's modulus after curing of the photosensitive resin composition is a value not exceeding 0.5 GPa. The strain absorbing layer contains a bismaleimide compound having a cyclic imide bond and a divalent hydrocarbon group derived from dimer acid, a photopolymerization initiator, and a silicon compound having four or more alkoxy groups bonded to silicon atoms. Comprising a photosensitive resin composition,
2. The semiconductor device according to claim 1, wherein the Young's modulus after curing of the photosensitive resin composition is a value not exceeding 0.5 GPa. Arranging a through hole for a through electrode in a semiconductor substrate constituting a semiconductor device;
Disposing a strain absorbing layer on the first main surface of the semiconductor substrate;
Filling the through hole with a conductor layer or attaching a conductor layer to the inner wall of the through hole to form a through electrode;
Forming a land-like first electrode connected to the through electrode and disposed on the surface of the strain absorbing layer;
Forming a wiring pattern connected to the first electrode on the surface of the strain absorbing layer;
And a step of disposing a ball-shaped second electrode on a surface of the wiring pattern where the first electrode is not disposed.