JP2013187353A - Electronic device and method for manufacturing electronic device - Google Patents

Electronic device and method for manufacturing electronic device Download PDF

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Publication number
JP2013187353A
JP2013187353A JP2012051293A JP2012051293A JP2013187353A JP 2013187353 A JP2013187353 A JP 2013187353A JP 2012051293 A JP2012051293 A JP 2012051293A JP 2012051293 A JP2012051293 A JP 2012051293A JP 2013187353 A JP2013187353 A JP 2013187353A
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electronic device
cross
protective film
sectional area
wiring board
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Yoshitaka Kyogoku
好孝 京極
Shinji Watanabe
真司 渡邉
Akira Matsumoto
明 松本
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device which suppresses peeling in a multilayer wiring layer, and has high reliability.SOLUTION: An electronic device includes a wiring board 70, a semiconductor device 72 mounted on the wiring board 70, and a solder terminal 20 which connects the wiring board 70 with the semiconductor device 72. The semiconductor device 72 includes a multilayer wiring layer 32, an electrode pad 40 provided on the multilayer wiring layer 32, a protection film 38 which is provided on the multilayer wiring layer 32 and has an opening on the electrode pad 40, and a connection terminal 10 which is provided on the electrode pad 40 and the protection film 38 and is connected to the wiring board 70 through the solder terminal 20. In the connection terminal 10, a cross-sectional area in a first cross section parallel to the surface of the protection film 38 is larger than that in a second cross section positioned on the same plane as the surface of the protection film 38, in an end in contact with the solder terminal 20, and the solder terminal 20 has a small area portion 22 having a cross-sectional area smaller than that in the first cross section.

Description

本発明は、電子装置および電子装置の製造方法に関する。   The present invention relates to an electronic device and a method for manufacturing the electronic device.

半導体装置は、接続端子や半田端子を介して配線基板と接続する。この半導体装置と配線基板との接続部における構造等に関しては、様々な技術が検討されており、例えば特許文献１〜５に記載の技術が挙げられる。特許文献１に記載の技術は、半導体装置に形成された高さの異なる導電性ピラーについて、高さに対応して導電性ピラーの太さを変えるというものである。特許文献２に記載の技術は、半導体基板のパッド電極上に形成された柱状金属バンプの周囲に半田バンプを形成するというものである。   The semiconductor device is connected to a wiring board through connection terminals and solder terminals. With respect to the structure and the like in the connection portion between the semiconductor device and the wiring board, various techniques have been studied, for example, the techniques described in Patent Documents 1 to 5. The technique described in Patent Document 1 is to change the thickness of the conductive pillars corresponding to the heights of the conductive pillars having different heights formed in the semiconductor device. The technique described in Patent Document 2 is to form solder bumps around columnar metal bumps formed on pad electrodes of a semiconductor substrate.

特許文献３に記載の技術は、接続端子のうち銅によって構成される部分を、一定以上の高さを有するように形成するというものである。特許文献４に記載の技術は、半導体チップに形成された柱状のポスト電極が第一の金属部分と第二の金属部分とにより構成され、第一の金属部分の幅寸法を第二の金属部分の幅寸法よりも小さくするというものである。特許文献５に記載の技術は、はんだ拡散防止およびはんだ接着効果のある金属突起を基板の電極に固着し、この金属突起の上部をはんだによって覆うというものである。   The technique described in Patent Document 3 is to form a portion made of copper in the connection terminal so as to have a certain height or more. In the technique described in Patent Document 4, a columnar post electrode formed on a semiconductor chip is constituted by a first metal part and a second metal part, and the width dimension of the first metal part is set to the second metal part. This is to make it smaller than the width dimension. The technique described in Patent Document 5 is to fix a metal protrusion having an effect of preventing solder diffusion and solder adhesion to an electrode of a substrate and covering the upper part of the metal protrusion with solder.

特開平１０−６４９５３号公報Japanese Patent Laid-Open No. 10-64953 特開２０００−９１３７１号公報JP 2000-91371 A 米国特許６６８１９８２明細書US Patent 6681982 Specification 特開２００９−８１１５３号公報JP 2009-81153 A 特開平７−１４２４８８号公報JP-A-7-142488

半導体装置と配線基板との熱膨張率の違いにより、これらによって構成される電子装置にひずみが生じることがある。電子装置に発生したひずみは、半導体装置上に形成された接続端子を変形させる。接続端子の変形は、半導体装置を構成する多層配線層に対し、多層配線層が剥離する方向への応力を発生させる。電子装置の信頼性を向上させるためには、この応力によって多層配線装置の剥離が生じることを抑制する必要がある。   Due to the difference in coefficient of thermal expansion between the semiconductor device and the wiring board, distortion may occur in the electronic device constituted by these. The distortion generated in the electronic device deforms the connection terminal formed on the semiconductor device. The deformation of the connection terminal generates a stress in the direction in which the multilayer wiring layer peels off from the multilayer wiring layer constituting the semiconductor device. In order to improve the reliability of the electronic device, it is necessary to suppress the peeling of the multilayer wiring device due to this stress.

本発明によれば、配線基板と、
前記配線基板上に実装された半導体装置と、
前記配線基板と前記半導体装置を接続する半田端子と、
を備え、
前記半導体装置は、
多層配線層と、
前記多層配線層に設けられた電極パッドと、
前記多層配線層上に設けられ、前記電極パッド上に開口を有する保護膜と、
前記電極パッド上および前記保護膜上に設けられ、前記半田端子を介して前記配線基板と接続する接続端子と、
を有し、
前記接続端子は、前記半田端子と接する端部における前記保護膜の表面と平行な第１の断面における断面積が、前記保護膜の表面と同一平面に位置する第２の断面における断面積よりも大きく、
前記半田端子は、断面積が前記第１の断面における断面積よりも小さい小面積部を有する電子装置が提供される。 According to the present invention, a wiring board;
A semiconductor device mounted on the wiring board;
Solder terminals for connecting the wiring board and the semiconductor device;
With
The semiconductor device includes:
A multilayer wiring layer;
Electrode pads provided on the multilayer wiring layer;
A protective film provided on the multilayer wiring layer and having an opening on the electrode pad;
A connection terminal provided on the electrode pad and on the protective film and connected to the wiring board via the solder terminal;
Have
The connection terminal has a cross-sectional area in a first cross section parallel to the surface of the protective film at an end in contact with the solder terminal, more than a cross-sectional area in a second cross section located on the same plane as the surface of the protective film. big,
The solder terminal is provided with an electronic device having a small area portion whose sectional area is smaller than the sectional area in the first section.

本発明によれば、接続端子は、半田端子と接する端部における保護膜の表面と平行な第１の断面における断面積が、保護膜の表面と同一平面に位置する第２の断面における断面積よりも大きい形状を有する。第１の断面における断面積を大きくすることができ、半田端子を構成する半田材料の濡れ上がりが抑制することができる。これにより、接続端子よりも半田端子において変形が生じやすくなる。そして、半田端子は、断面積が第１の断面における断面積よりも小さい小面積部分を有する。このため、電子装置に発生するひずみによる応力を、小面積部が変形することによって吸収することができる。よって、接続端子の変形が抑制される。   According to the present invention, the connection terminal has a cross-sectional area in the second cross section in which the cross-sectional area in the first cross section parallel to the surface of the protective film at the end in contact with the solder terminal is located on the same plane as the surface of the protective film. Has a larger shape. The cross-sectional area in the first cross section can be increased, and wetting of the solder material constituting the solder terminal can be suppressed. Thereby, deformation is more likely to occur in the solder terminal than in the connection terminal. The solder terminal has a small area portion whose sectional area is smaller than the sectional area in the first section. For this reason, the stress by the distortion which generate | occur | produces in an electronic device can be absorbed when a small area part deform | transforms. Therefore, deformation of the connection terminal is suppressed.

また、接続端子は、保護膜上に形成されている。これにより、接続端子からの応力を保護膜において吸収することができる。そして、接続端子は、第２の断面における断面積が第１の断面における断面積よりも小さい形状を有する。第２の断面における断面積を小さくすることにより、接続端子間の間隔が広くなり、接続端子からの応力を吸収することができる保護膜の面積が増えることとなる。   The connection terminal is formed on the protective film. Thereby, the stress from the connection terminal can be absorbed in the protective film. The connection terminal has a shape in which the cross-sectional area in the second cross section is smaller than the cross-sectional area in the first cross section. By reducing the cross-sectional area in the second cross section, the interval between the connection terminals is widened, and the area of the protective film that can absorb the stress from the connection terminals is increased.

このようにして、接続端子から多層配線層に働く応力が緩和されることから、多層配線層の剥離が抑制される。従って、信頼性の高い電子装置を提供することができる。   In this way, the stress acting on the multilayer wiring layer from the connection terminal is relieved, so that peeling of the multilayer wiring layer is suppressed. Therefore, a highly reliable electronic device can be provided.

本発明によれば、半導体装置を、半田端子を介して配線基板へ実装する工程を備え、前記半導体装置は、多層配線層と、前記多層配線層上に設けられた電極パッドと、前記多層配線層上に設けられ、前記電極パッド上に開口を有する保護膜と、前記電極パッド上および前記保護膜上に設けられ、前記半田端子を介して前記配線基板と接続する接続端子と、を有し、前記接続端子は、前記半田端子と接する端部における前記保護膜の表面と平行な第１の断面における断面積が、前記保護膜の表面と同一平面に位置する第２の断面における断面積よりも大きく、前記半田端子は、断面積が前記第１の断面における断面積よりも小さい小面積部を有する電子装置の製造方法が提供される。   According to the present invention, the method includes a step of mounting a semiconductor device on a wiring board via a solder terminal. The semiconductor device includes a multilayer wiring layer, an electrode pad provided on the multilayer wiring layer, and the multilayer wiring. A protective film provided on the layer and having an opening on the electrode pad; and a connection terminal provided on the electrode pad and on the protective film and connected to the wiring board via the solder terminal. The connection terminal has a cross-sectional area in a first cross section parallel to the surface of the protective film at an end in contact with the solder terminal, from a cross-sectional area in a second cross section located on the same plane as the surface of the protective film. The solder terminal is provided with a method of manufacturing an electronic device having a small area portion whose cross-sectional area is smaller than the cross-sectional area in the first cross section.

本発明によれば、多層配線層における剥離を抑制し、信頼性の高い電子装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, peeling in a multilayer wiring layer can be suppressed and a reliable electronic device can be provided.

第１の実施形態に係る電子装置を示す断面図である。It is sectional drawing which shows the electronic device which concerns on 1st Embodiment. 図１に示す電子装置を示す断面図である。It is sectional drawing which shows the electronic device shown in FIG. 図１に示す半導体装置のうち配線基板と対向する面を示す平面図である。It is a top view which shows the surface facing a wiring board among the semiconductor devices shown in FIG. 図１に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 図１に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 図１に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 図１に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 比較例に係る電子装置を示す断面図である。It is sectional drawing which shows the electronic device which concerns on a comparative example. 第２の実施形態に係る電子装置を示す断面図である。It is sectional drawing which shows the electronic device which concerns on 2nd Embodiment. 図９に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 図９に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 図９に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 図９に示す電子装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device shown in FIG. 第３の実施形態に係る電子装置を示す断面図である。It is sectional drawing which shows the electronic device which concerns on 3rd Embodiment. 第４の実施形態に係る電子装置を示す断面図である。It is sectional drawing which shows the electronic device which concerns on 4th Embodiment.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

図１は、第１の実施形態に係る電子装置１００を示す断面図である。電子装置１００は、配線基板７０と、半導体装置７２と、半田端子２０を備える。電子装置１００は、半導体パッケージである。また、半導体装置７２は、半導体チップである。そして、配線基板７０は、インタポーザである。   FIG. 1 is a cross-sectional view showing an electronic device 100 according to the first embodiment. The electronic device 100 includes a wiring board 70, a semiconductor device 72, and solder terminals 20. The electronic device 100 is a semiconductor package. The semiconductor device 72 is a semiconductor chip. The wiring board 70 is an interposer.

半導体装置７２は、配線基板７０上に実装されている。半田端子２０は、配線基板７０と半導体装置７２を接続する。半導体装置７２は、多層配線層３２と、電極パッド４０と、保護膜３８と、接続端子１０と、を有する。電極パッド４０は、多層配線層３２上に設けられている。保護膜３８は、多層配線層３２上に設けられ、電極パッド４０上に開口を有する。接続端子１０は、電極パッド４０上および保護膜３８上に設けられ、半田端子２０を介して配線基板７０と接続する。また、接続端子１０は、半田端子２０と接する端部における保護膜３８の表面と平行な第１の断面における断面積が、保護膜３８の表面と同一平面に位置する第２の断面における断面積よりも大きい。半田端子２０は、断面積が第１の断面における断面積よりも小さい小面積部２２を有する。以下、図１〜３を用いて、電子装置１００の構成について詳細に説明する。   The semiconductor device 72 is mounted on the wiring board 70. The solder terminal 20 connects the wiring board 70 and the semiconductor device 72. The semiconductor device 72 includes the multilayer wiring layer 32, the electrode pad 40, the protective film 38, and the connection terminal 10. The electrode pad 40 is provided on the multilayer wiring layer 32. The protective film 38 is provided on the multilayer wiring layer 32 and has an opening on the electrode pad 40. The connection terminal 10 is provided on the electrode pad 40 and the protective film 38 and is connected to the wiring substrate 70 via the solder terminal 20. Further, the connection terminal 10 has a cross-sectional area in a second cross section in which the cross-sectional area in the first cross section parallel to the surface of the protective film 38 at the end in contact with the solder terminal 20 is located in the same plane as the surface of the protective film 38. Bigger than. The solder terminal 20 has a small area portion 22 whose cross-sectional area is smaller than the cross-sectional area in the first cross section. Hereinafter, the configuration of the electronic device 100 will be described in detail with reference to FIGS.

配線基板７０は、電極５４と、保護膜５０と、を備えている。電極５４は、配線基板７０のうち半導体装置７２と対向する面に設けられている。電極５４は、ランド形状であってもよい。保護膜５０は、配線基板７０のうち半導体装置７２と対向する面に設けられており、電極５４上において開口を有する。この開口は、平面視で電極５４より大きくてもよいし、小さくてもよい。電極５４は、半田端子２０を介して接続端子１０と接続する。   The wiring board 70 includes an electrode 54 and a protective film 50. The electrode 54 is provided on the surface of the wiring board 70 that faces the semiconductor device 72. The electrode 54 may have a land shape. The protective film 50 is provided on the surface of the wiring substrate 70 facing the semiconductor device 72 and has an opening on the electrode 54. This opening may be larger or smaller than the electrode 54 in plan view. The electrode 54 is connected to the connection terminal 10 via the solder terminal 20.

本実施形態では、小面積部２２は、半田端子２０のうち配線基板７０と接続する端部に位置している。本実施形態における半田端子２０の小面積部２２は、配線基板７０上の半田端子２０を形成するための開口径を、接続端子１０の第１の断面よりも小さくすることにより形成することができる。半田端子２０は、例えばＳｎ系の半田または導電性の樹脂等によって構成される。   In the present embodiment, the small area portion 22 is located at an end portion of the solder terminal 20 that is connected to the wiring board 70. The small area portion 22 of the solder terminal 20 in the present embodiment can be formed by making the opening diameter for forming the solder terminal 20 on the wiring board 70 smaller than the first cross section of the connection terminal 10. . The solder terminal 20 is composed of, for example, Sn-based solder or conductive resin.

半導体装置７２は、半導体基板３０と、保護膜３６と、をさらに有する。半導体基板３０は、例えばＳｉ基板である。多層配線層３２は、半導体基板３０上に形成されており、層間絶縁膜として、例えばＳｉＯ２よりも誘電率が低い層間絶縁膜を含んでいる。保護膜３６は、多層配線層３２上に形成されている。また、保護膜３６は、電極パッド４０上に開口を有している。この開口は、平面視で電極パッド４０よりも大きくてもよいし、小さくてもよい。保護膜３６は、例えばパッシベーション膜であり、ＳｉＮおよびＳｉＯ２の少なくとも一方によって構成される。保護膜３８は、保護膜３６上に形成されている。保護膜３８も同様に、電極パッド４０上に開口を有している。この開口は、平面視で電極パッド４０よりも大きくてもよいし、小さくてもよい。保護膜３８は、例えばポリイミドによって構成される。 The semiconductor device 72 further includes a semiconductor substrate 30 and a protective film 36. The semiconductor substrate 30 is, for example, a Si substrate. The multilayer wiring layer 32 is formed on the semiconductor substrate 30 and includes an interlayer insulating film having a dielectric constant lower than that of, for example, SiO 2 as an interlayer insulating film. The protective film 36 is formed on the multilayer wiring layer 32. The protective film 36 has an opening on the electrode pad 40. This opening may be larger or smaller than the electrode pad 40 in plan view. The protective film 36 is a passivation film, for example, and is composed of at least one of SiN and SiO 2 . The protective film 38 is formed on the protective film 36. Similarly, the protective film 38 has an opening on the electrode pad 40. This opening may be larger or smaller than the electrode pad 40 in plan view. The protective film 38 is made of polyimide, for example.

接続端子１０は、保護膜３６および保護膜３８の開口に形成されており、例えば保護膜３８の開口の全周において保護膜３８上に乗り上がるように形成されている。接続端子１０が保護膜３８に乗り上げるように形成されることにより、接続端子１０からの応力を保護膜３８によって吸収することができる。このため、接続端子１０から多層配線層３２に働く応力が緩和される。   The connection terminal 10 is formed in the openings of the protective film 36 and the protective film 38, for example, so as to ride on the protective film 38 in the entire periphery of the opening of the protective film 38. By forming the connection terminal 10 so as to run over the protective film 38, the stress from the connection terminal 10 can be absorbed by the protective film 38. For this reason, the stress which acts on the multilayer wiring layer 32 from the connection terminal 10 is relieved.

接続端子１０の第１の断面が円形であるとしたとき、この断面の幅をａとする。また、半田端子２０の配線基板７０と接続する端部における断面が円形であるとしたとき、この断面の幅をｂとする。この場合において、ａ≧ｂ＋２５μｍであることが好ましい。接続端子１０の降伏応力は、例えば半田端子２０の降伏応力よりも大きい。接続端子１０は、例えばＣｕにより構成される。   When the first cross section of the connection terminal 10 is circular, the width of this cross section is a. Further, when the cross section at the end portion of the solder terminal 20 connected to the wiring board 70 is circular, the width of the cross section is b. In this case, it is preferable that a ≧ b + 25 μm. The yield stress of the connection terminal 10 is larger than the yield stress of the solder terminal 20, for example. The connection terminal 10 is made of Cu, for example.

図２は、図１に示す電子装置１００を示す断面図である。図２に示すように、半導体装置７２は、電極パッド４０および接続端子１０を複数有している。これに対応して、配線基板７０は、電極５４を複数有している。電子装置１００は、配線基板７０と半導体装置７２との空間を封止するアンダーフィル樹脂５６をさらに備えている。   FIG. 2 is a cross-sectional view showing the electronic device 100 shown in FIG. As shown in FIG. 2, the semiconductor device 72 includes a plurality of electrode pads 40 and connection terminals 10. Correspondingly, the wiring board 70 has a plurality of electrodes 54. The electronic device 100 further includes an underfill resin 56 that seals a space between the wiring board 70 and the semiconductor device 72.

図３は、図１に示す半導体装置７２のうち配線基板７０と対向する面を示す平面図である。図３に示すように、接続端子１０は、千鳥格子状に並んでいる。保護膜３８の表面と同一平面において、互いに隣り合う２つの接続端子１０のうち、最も近接する２つの接続端子１０間の間隔ｄは、例えば２５０μｍ以下である。   FIG. 3 is a plan view showing a surface of the semiconductor device 72 shown in FIG. As shown in FIG. 3, the connection terminals 10 are arranged in a staggered pattern. In the same plane as the surface of the protective film 38, the distance d between the two adjacent connection terminals 10 among the two adjacent connection terminals 10 is, for example, 250 μm or less.

図４〜７は、図１に示す電子装置１００の製造方法を示す断面図である。電子装置１００の製造方法は、例えば次のようである。まず、半導体基板３０上に多層配線層３２を形成する。このとき、電極パッド４０も形成される。次いで、多層配線層３２上および電極パッド４０上に、保護膜３６を形成する。そして電極パッド４０上に位置する保護膜３６に開口を形成する。次いで、保護膜３６上および電極パッド４０上に、保護膜３８を形成する。そして、電極パッド４０上に位置する保護膜３８に開口を形成する。次いで、保護膜３８上および保護膜３８の開口内にシード膜を形成する（図示せず）。そして、該シード膜上に、感光性のレジスト６０を塗布する（図４）。   4 to 7 are cross-sectional views showing a method for manufacturing the electronic device 100 shown in FIG. A method for manufacturing the electronic device 100 is, for example, as follows. First, the multilayer wiring layer 32 is formed on the semiconductor substrate 30. At this time, the electrode pad 40 is also formed. Next, a protective film 36 is formed on the multilayer wiring layer 32 and the electrode pad 40. Then, an opening is formed in the protective film 36 located on the electrode pad 40. Next, a protective film 38 is formed on the protective film 36 and the electrode pad 40. Then, an opening is formed in the protective film 38 located on the electrode pad 40. Next, a seed film is formed on the protective film 38 and in the opening of the protective film 38 (not shown). Then, a photosensitive resist 60 is applied on the seed film (FIG. 4).

次いで、レジスト６０を露光する。この露光時において、露光の光９０の焦点位置９２を、半導体装置７２のレジスト６０を塗布する側とは反対側に調整する。これにより、レジスト６０は、電極パッド４０上および保護膜３８上において、逆テーパ状に露光されることとなる（図５）。なお、露光の光９０の焦点位置９２と半導体装置７２との間隔を変えることで、逆テーパの形状を調整することができる。   Next, the resist 60 is exposed. At the time of this exposure, the focal position 92 of the exposure light 90 is adjusted to the side opposite to the side where the resist 60 of the semiconductor device 72 is applied. As a result, the resist 60 is exposed in a reverse taper shape on the electrode pad 40 and the protective film 38 (FIG. 5). Note that the reverse taper shape can be adjusted by changing the distance between the focal position 92 of the exposure light 90 and the semiconductor device 72.

次いで、レジスト６０を現像し、キュアする。これにより、電極パッド４０上および保護膜３８上において、レジスト６０の開口６２を形成する（図６）。そして、開口６２内に、シード膜をシードとしてめっき法を用いて接続端子１０を形成する。その後、レジスト６０および不要なシード膜を除去して、半導体装置７２を得る（図７）。この半導体装置７２を、半田端子２０を介して配線基板７０に実装する。これにより、電子装置１００が得られる（図１）。   Next, the resist 60 is developed and cured. Thereby, the opening 62 of the resist 60 is formed on the electrode pad 40 and the protective film 38 (FIG. 6). Then, the connection terminal 10 is formed in the opening 62 by using a plating method with the seed film as a seed. Thereafter, the resist 60 and unnecessary seed film are removed to obtain the semiconductor device 72 (FIG. 7). The semiconductor device 72 is mounted on the wiring board 70 via the solder terminals 20. Thereby, the electronic device 100 is obtained (FIG. 1).

次に、本実施形態の効果について説明する。図８は、比較例に係る電子装置を示す断面図である。比較例に係る電子装置において、接続端子１０は、第１の断面における断面積と、第２の断面における断面積が等しい形状を有する。このため、半田端子２０を構成する半田材料が接続端子１０の側面に濡れ上がりやすい。これに対し、本実施形態に係る電子装置１００では、接続端子１０は、第１の断面における断面積が、第２の断面における断面積よりも大きい形状を有する。第１の断面における断面積を大きくできるため、半田端子２０を構成する半田材料が、接続端子１０の側面に濡れ上がることが抑制することができる。よって、接続端子よりも半田端子において変形が生じやすく、接続端子の変形が抑制される。   Next, the effect of this embodiment will be described. FIG. 8 is a cross-sectional view illustrating an electronic device according to a comparative example. In the electronic device according to the comparative example, the connection terminal 10 has a shape in which the cross-sectional area in the first cross section is equal to the cross-sectional area in the second cross section. For this reason, the solder material constituting the solder terminal 20 is likely to wet onto the side surface of the connection terminal 10. On the other hand, in the electronic device 100 according to this embodiment, the connection terminal 10 has a shape in which the cross-sectional area in the first cross section is larger than the cross-sectional area in the second cross section. Since the cross-sectional area in the first cross section can be increased, it is possible to suppress the solder material constituting the solder terminal 20 from getting wet on the side surface of the connection terminal 10. Therefore, deformation is more likely to occur in the solder terminal than in the connection terminal, and deformation of the connection terminal is suppressed.

また、比較例に係る電子装置において、半田端子２０は、第１の断面における断面積よりも断面積が小さい部分を有しない。よって、半導体装置７２と配線基板７０の熱膨張率の違いにより生じる電子装置に発生するひずみによる応力を、半田端子において吸収することが困難となり、その分、接続端子１０が変形しまたは傾くこととなる。これに対し、本実施形態に係る電子装置１００では、半田端子２０は、断面積が第１の断面における断面積よりも小さい小面積部分を有する。このため、電子装置に発生するひずみによる応力を小面積部２２において吸収することができ、接続端子の変形が抑制される。   In the electronic device according to the comparative example, the solder terminal 20 does not have a portion having a smaller cross-sectional area than the cross-sectional area in the first cross section. Therefore, it becomes difficult to absorb the stress due to strain generated in the electronic device due to the difference in thermal expansion coefficient between the semiconductor device 72 and the wiring substrate 70 at the solder terminal, and the connection terminal 10 is deformed or inclined correspondingly. Become. On the other hand, in the electronic device 100 according to the present embodiment, the solder terminal 20 has a small area portion whose sectional area is smaller than the sectional area in the first section. For this reason, the stress by the distortion which generate | occur | produces in an electronic device can be absorbed in the small area part 22, and a deformation | transformation of a connection terminal is suppressed.

さらに、比較例に係る電子装置において、接続端子１０は、第２の断面における断面積が、第１の断面における断面積と等しい形状を有する。これに対し、本実施形態に係る電子装置１００では、接続端子１０は、第２の断面における断面積が、第１の断面における断面積よりも小さい形状を有する。第２の断面における断面積を小さくすることにより、接続端子１０間の間隔が広くなり、接続端子１０からの応力を吸収することができる保護膜３８の面積が増えることとなる。   Furthermore, in the electronic device according to the comparative example, the connection terminal 10 has a shape in which the cross-sectional area in the second cross section is equal to the cross-sectional area in the first cross section. On the other hand, in the electronic device 100 according to the present embodiment, the connection terminal 10 has a shape in which the cross-sectional area in the second cross section is smaller than the cross-sectional area in the first cross section. By reducing the cross-sectional area in the second cross section, the interval between the connection terminals 10 is widened, and the area of the protective film 38 that can absorb the stress from the connection terminals 10 is increased.

このようにして、接続端子１０が第１の断面における断面積が第２の断面における断面積よりも大きい形状を有し、かつ半田端子２０が小面積部を有することにより、接続端子１０から多層配線層３２に働く応力が緩和される。これにより、多層配線層３２の剥離が抑制される。従って、信頼性の高い電子装置を提供することができる。   In this way, the connection terminal 10 has a shape in which the cross-sectional area in the first cross section is larger than the cross-sectional area in the second cross section, and the solder terminal 20 has a small area portion. The stress acting on the wiring layer 32 is relaxed. Thereby, peeling of the multilayer wiring layer 32 is suppressed. Therefore, a highly reliable electronic device can be provided.

また、電子装置に発生したひずみは、多層配線層上に形成された保護膜に亀裂を生じさせることがある。保護膜に亀裂が生じると、接続端子からの応力を保護膜において吸収できなくなる。このため、多層配線層における剥離をさらに誘発する原因となる。本実施形態によれば、接続端子１０は、第２の断面における断面積が第１の断面における断面積よりも小さい形状を有する。第２の断面における断面積が小さいことから、接続端子１０からの応力を吸収することができる保護膜３８の長さが増える。このため、保護膜３８における亀裂の発生が抑制される。よって、多層配線層の剥離を抑制することができる。   In addition, the strain generated in the electronic device may cause a crack in the protective film formed on the multilayer wiring layer. If a crack occurs in the protective film, the protective film cannot absorb the stress from the connection terminal. For this reason, it causes further peeling in the multilayer wiring layer. According to the present embodiment, the connection terminal 10 has a shape in which the cross-sectional area in the second cross section is smaller than the cross-sectional area in the first cross section. Since the cross-sectional area in the second cross section is small, the length of the protective film 38 that can absorb the stress from the connection terminal 10 increases. For this reason, generation | occurrence | production of the crack in the protective film 38 is suppressed. Therefore, peeling of the multilayer wiring layer can be suppressed.

図９は、第２の実施形態に係る電子装置１０２を示す断面図であり、第１の実施形態における図１に対応している。本実施形態に係る電子装置１０２は、接続端子１０の形状を除いて、第１の実施形態に係る電子装置１００と同様である。   FIG. 9 is a cross-sectional view showing the electronic device 102 according to the second embodiment, and corresponds to FIG. 1 in the first embodiment. The electronic device 102 according to the present embodiment is the same as the electronic device 100 according to the first embodiment except for the shape of the connection terminal 10.

電子装置１０２における接続端子１０は、図９に示すように、側面において段差を形成することにより、第１の断面における断面積が、第２の断面における断面積よりも大きい形状を実現している。なお、接続端子１０の側面における段差は、複数であってもよい。   As shown in FIG. 9, the connection terminal 10 in the electronic device 102 forms a step on the side surface, thereby realizing a shape in which the cross-sectional area in the first cross section is larger than the cross-sectional area in the second cross section. . Note that there may be a plurality of steps on the side surface of the connection terminal 10.

図１０〜１３は、図９に示す電子装置１０２の製造方法を示す断面図である。電子装置１０２の製造方法は、例えば次のようである。まず、半導体基板３０上に多層配線層３２を形成する。このとき、電極パッド４０も形成される。次いで、多層配線層３２上および電極パッド４０上に、保護膜３６を形成する。そして電極パッド４０上に位置する保護膜３６に開口を形成する。次いで、保護膜３６上および電極パッド４０上に、保護膜３８を形成する。そして、電極パッド４０上に位置する保護膜３８に開口を形成する。次いで、保護膜３８上および保護膜３８の開口内にシード膜を形成する（図示せず）。そして、該シード膜上に、感光性のレジスト６０を塗布する（図１０）。   10 to 13 are cross-sectional views showing a method for manufacturing the electronic device 102 shown in FIG. The method for manufacturing the electronic device 102 is, for example, as follows. First, the multilayer wiring layer 32 is formed on the semiconductor substrate 30. At this time, the electrode pad 40 is also formed. Next, a protective film 36 is formed on the multilayer wiring layer 32 and the electrode pad 40. Then, an opening is formed in the protective film 36 located on the electrode pad 40. Next, a protective film 38 is formed on the protective film 36 and the electrode pad 40. Then, an opening is formed in the protective film 38 located on the electrode pad 40. Next, a seed film is formed on the protective film 38 and in the opening of the protective film 38 (not shown). Then, a photosensitive resist 60 is applied on the seed film (FIG. 10).

次いで、レジスト６０を露光する。そして、レジスト６０を現像し、キュアする。これにより、電極パッド４０上および保護膜３８上において、レジスト６０の開口６２を形成する（図１１）。次いで、レジスト６０上および開口６２内に感光性のレジスト６４を塗布する。そして、レジスト６４を露光する。その後、レジスト６４を現像し、キュアする。これにより、電極パッド４０上、保護膜３８上、およびレジスト６０上において、レジスト６４の開口６６を形成する。このとき、開口６６は、平面視で開口６２よりも大きく形成される（図１２）。なお、感光性のレジストを形成し開口を形成するこれらの工程を、さらに繰り返してもよい。   Next, the resist 60 is exposed. Then, the resist 60 is developed and cured. As a result, an opening 62 of the resist 60 is formed on the electrode pad 40 and the protective film 38 (FIG. 11). Next, a photosensitive resist 64 is applied on the resist 60 and in the opening 62. Then, the resist 64 is exposed. Thereafter, the resist 64 is developed and cured. Thereby, an opening 66 of the resist 64 is formed on the electrode pad 40, the protective film 38, and the resist 60. At this time, the opening 66 is formed larger than the opening 62 in plan view (FIG. 12). Note that these steps of forming a photosensitive resist and forming an opening may be further repeated.

そして、開口６２、６６内に、シード膜をシードとしてめっき法を用いて接続端子１０を形成する。その後、レジスト６０、６４および不要なシード膜を除去して、半導体装置７２を得る（図１３）。この半導体装置７２を、半田端子２０を介して配線基板７０に実装する。これにより、電子装置１０２が得られる（図９）。   Then, the connection terminals 10 are formed in the openings 62 and 66 using a seed film as a seed by plating. Thereafter, the resists 60 and 64 and the unnecessary seed film are removed to obtain the semiconductor device 72 (FIG. 13). The semiconductor device 72 is mounted on the wiring board 70 via the solder terminals 20. Thereby, the electronic device 102 is obtained (FIG. 9).

本実施形態によっても、第１の実施形態と同様の効果を得ることができる。   Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

図１４は、第３の実施形態に係る電子装置１０４を示す断面図であり、第１の実施形態における図１に対応している。本実施形態に係る電子装置１０４は、半田端子２０が、両端以外の部分において小面積部２２を有する点を除いて、第１の実施形態に係る電子装置１００と同様である。本実施形態における半田端子２０の小面積部２２は、半田端子２０を構成する半田材料の量を少なくするように調整して形成する。本実施形態によっても、第１の実施形態と同様の効果を得ることができる。   FIG. 14 is a cross-sectional view showing an electronic device 104 according to the third embodiment, and corresponds to FIG. 1 in the first embodiment. The electronic device 104 according to the present embodiment is the same as the electronic device 100 according to the first embodiment, except that the solder terminal 20 has a small area portion 22 at portions other than both ends. The small area portion 22 of the solder terminal 20 in this embodiment is formed by adjusting so as to reduce the amount of solder material constituting the solder terminal 20. Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

図１５は、第４の実施形態に係る電子装置１０６を示す断面図であり、第１の実施形態における図２に対応している。本実施形態に係る電子装置１０６は、半導体装置７２がウェハレベルＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）である点を除いて、第１の実施形態に係る電子装置１００と同様である。また、本実施形態において、配線基板７０は、回路基板である。   FIG. 15 is a cross-sectional view showing an electronic device 106 according to the fourth embodiment, and corresponds to FIG. 2 in the first embodiment. The electronic device 106 according to the present embodiment is the same as the electronic device 100 according to the first embodiment, except that the semiconductor device 72 is a wafer level CSP (Chip Size Package). In the present embodiment, the wiring board 70 is a circuit board.

図１５に示すように、半導体装置７２のうち配線基板７０に実装される面は、接続端子１０の下面が露出するように、モールド樹脂５８によって覆われている。接続端子１０の露出した面に半田端子２０を形成し、これを配線基板７０へ実装することにより、電子装置１０６が形成される。保護膜３８の表面と同一平面において、近接する２つの接続端子１０の間の距離ｄは、例えば３００μｍ以下である。   As shown in FIG. 15, the surface of the semiconductor device 72 mounted on the wiring board 70 is covered with the mold resin 58 so that the lower surface of the connection terminal 10 is exposed. By forming the solder terminal 20 on the exposed surface of the connection terminal 10 and mounting it on the wiring board 70, the electronic device 106 is formed. In the same plane as the surface of the protective film 38, the distance d between two adjacent connection terminals 10 is, for example, 300 μm or less.

本実施形態によっても、第１の実施形態と同様の効果を得ることができる。   Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

（参考例）
以下の参考例において、多層配線層の剥離の発生率および保護膜の亀裂の発生率を測定した。測定サンプルにおいて、接続端子の径をａとし、半田端子が配線基板と接続する端部における径をｂとする。なお、接続端子の形状は、その径が均一な柱状である。また、半田端子が配線基板と接続する端部における径ｂは一定である。 (Reference example)
In the following reference examples, the occurrence rate of peeling of the multilayer wiring layer and the occurrence rate of cracks in the protective film were measured. In the measurement sample, the diameter of the connection terminal is a, and the diameter at the end where the solder terminal is connected to the wiring board is b. The connection terminal has a columnar shape with a uniform diameter. Further, the diameter b at the end where the solder terminal is connected to the wiring board is constant.

ａ＝ｂ−５μｍでサンプルを作成し、フリップ実装後に多層配線層の剥離を観察したところ、多層配線層の剥離の発生率は１００％であった。この場合において、保護膜の亀裂を観察したところ、保護膜の亀裂が見られたサンプルは０であった。   When a sample was prepared with a = b−5 μm and the peeling of the multilayer wiring layer was observed after flip mounting, the occurrence rate of peeling of the multilayer wiring layer was 100%. In this case, when the crack of the protective film was observed, the number of samples in which the crack of the protective film was observed was zero.

一方で、ａ＝ｂ＋２５μｍでサンプルを形成し、フリップチップ実装後に多層配線層の剥離を観察したところ、多層配線層の剥離の発生率は１０％であった。この場合において、保護膜の亀裂を観察したところ、保護膜の亀裂の発生率は１０％であった。なお、多層配線層の剥離と保護膜の亀裂は、同一のサンプルによって発生した。   On the other hand, when a sample was formed with a = b + 25 μm and peeling of the multilayer wiring layer was observed after flip chip mounting, the occurrence rate of peeling of the multilayer wiring layer was 10%. In this case, when the crack of the protective film was observed, the occurrence rate of the protective film was 10%. Note that peeling of the multilayer wiring layer and cracking of the protective film occurred with the same sample.

このように、多層配線層の剥離が抑制された。これは、接続端子の径が大きくなる程、半田端子を構成する半田材料が接続端子の側面に濡れ上がることが抑制されるためと考えられる。一方で、保護膜に亀裂の発生が見られた。これは、接続端子の径が大きくなる程、接続端子間の間隔は狭くなり、接続端子からの応力を吸収することができる保護膜の長さが減少するためと考えられる。   Thus, peeling of the multilayer wiring layer was suppressed. This is presumably because the larger the diameter of the connection terminal, the more the solder material constituting the solder terminal is prevented from getting wet on the side surface of the connection terminal. On the other hand, cracks were observed in the protective film. This is presumably because the distance between the connection terminals becomes narrower as the diameter of the connection terminal becomes larger, and the length of the protective film capable of absorbing the stress from the connection terminal decreases.

以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。   As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

１０ 接続端子
２０ 半田端子
２２ 小面積部
３０ 半導体基板
３２ 多層配線層
３６ 保護膜
３８ 保護膜
４０ 電極パッド
５０ 保護膜
５４ 電極
５６ アンダーフィル樹脂
５８ モールド樹脂
６０ レジスト
６２ 開口
６４ レジスト
６６ 開口
７０ 配線基板
７２ 半導体装置
９０ 露光の光
９２ 焦点位置
１００ 電子装置
１０２ 電子装置
１０４ 電子装置
１０６ 電子装置 DESCRIPTION OF SYMBOLS 10 Connection terminal 20 Solder terminal 22 Small area part 30 Semiconductor substrate 32 Multilayer wiring layer 36 Protective film 38 Protective film 40 Electrode pad 50 Protective film 54 Electrode 56 Underfill resin 58 Mold resin 60 Resist 62 Opening 64 Resist 66 Opening 70 Wiring board 72 Semiconductor device 90 Exposure light 92 Focus position 100 Electronic device 102 Electronic device 104 Electronic device 106 Electronic device

Claims (11)

配線基板と、
前記配線基板上に実装された半導体装置と、
前記配線基板と前記半導体装置を接続する半田端子と、
を備え、
前記半導体装置は、
多層配線層と、
前記多層配線層に設けられた電極パッドと、
前記多層配線層上に設けられ、前記電極パッド上に開口を有する保護膜と、
前記電極パッド上および前記保護膜上に設けられ、前記半田端子を介して前記配線基板と接続する接続端子と、
を有し、
前記接続端子は、前記半田端子と接する端部における前記保護膜の表面と平行な第１の断面における断面積が、前記保護膜の表面と同一平面に位置する第２の断面における断面積よりも大きく、
前記半田端子は、断面積が前記第１の断面における断面積よりも小さい小面積部を有する電子装置。 A wiring board;
A semiconductor device mounted on the wiring board;
Solder terminals for connecting the wiring board and the semiconductor device;
With
The semiconductor device includes:
A multilayer wiring layer;
Electrode pads provided on the multilayer wiring layer;
A protective film provided on the multilayer wiring layer and having an opening on the electrode pad;
A connection terminal provided on the electrode pad and on the protective film and connected to the wiring board via the solder terminal;
Have
The connection terminal has a cross-sectional area in a first cross section parallel to the surface of the protective film at an end in contact with the solder terminal, more than a cross-sectional area in a second cross section located on the same plane as the surface of the protective film. big,
The solder terminal is an electronic device having a small area portion whose sectional area is smaller than the sectional area in the first section. 請求項１に記載の電子装置において、
前記接続端子のうち前記第１の断面における幅をａとし、前記接続端子のうち前記配線基板と接続する端部の断面おける幅をｂとしたときに、ａ≧ｂ＋２５μｍである電子装置。 The electronic device according to claim 1,
An electronic device in which a ≧ b + 25 μm, where a is a width in the first cross section of the connection terminals and b is a width in a cross section of an end portion of the connection terminals connected to the wiring board. 請求項１または２に記載の電子装置において、
前記半田端子は、前記配線基板と接続する端部において前記小面積部を有する電子装置。 The electronic device according to claim 1 or 2,
The solder terminal is an electronic device having the small area portion at an end portion connected to the wiring board. 請求項１または２に記載の電子装置において、
前記半田端子は、両端以外の部分において前記小面積部を有する電子装置。 The electronic device according to claim 1 or 2,
The solder terminal is an electronic device having the small area portion at a portion other than both ends. 請求項１乃至４いずれか１項に記載の電子装置において、
前記保護膜の表面と同一平面における前記接続端子間の距離は、３００μｍ以下である電子装置。 The electronic device according to any one of claims 1 to 4,
An electronic device in which a distance between the connection terminals in the same plane as the surface of the protective film is 300 μm or less. 請求項１乃至５いずれか１項に記載の電子装置において、
前記半導体装置は、前記接続端子を複数有する電子装置。 The electronic device according to claim 1,
The semiconductor device is an electronic device having a plurality of the connection terminals. 請求項１乃至６いずれか１項に記載の電子装置において、
前記接続端子の降伏応力は、前記半田端子の降伏応力よりも大きい電子装置。 The electronic device according to any one of claims 1 to 6,
An electronic device in which a yield stress of the connection terminal is larger than a yield stress of the solder terminal. 請求項１乃至７いずれか１項に記載の電子装置において、
前記多層配線層は、ＳｉＯ２よりも誘電率が低い層間絶縁膜により構成されている電子装置。 The electronic device according to any one of claims 1 to 7,
The electronic device in which the multilayer wiring layer is constituted by an interlayer insulating film having a dielectric constant lower than that of SiO 2 . 請求項１乃至８いずれか１項に記載の電子装置において、
前記半導体装置は、半導体チップであり、
前記電子装置は、半導体パッケージである電子装置。 The electronic device according to any one of claims 1 to 8,
The semiconductor device is a semiconductor chip,
The electronic device is an electronic device that is a semiconductor package. 請求項１乃至９いずれか１項に記載の電子装置において、
前記半導体装置は、ウェハレベルＣＳＰである電子装置。 The electronic device according to any one of claims 1 to 9,
The semiconductor device is an electronic device which is a wafer level CSP. 半導体装置を、半田端子を介して配線基板へ実装する工程を備え、
前記半導体装置は、
多層配線層と、
前記多層配線層上に設けられた電極パッドと、
前記多層配線層上に設けられ、前記電極パッド上に開口を有する保護膜と、
前記電極パッド上および前記保護膜上に設けられ、前記半田端子を介して前記配線基板と接続する接続端子と、
を有し、
前記接続端子は、前記半田端子と接する端部における前記保護膜の表面と平行な第１の断面における断面積が、前記保護膜の表面と同一平面に位置する第２の断面における断面積よりも大きく、
前記半田端子は、断面積が前記第１の断面における断面積よりも小さい小面積部を有する電子装置の製造方法。 A step of mounting a semiconductor device on a wiring board via a solder terminal;
The semiconductor device includes:
A multilayer wiring layer;
An electrode pad provided on the multilayer wiring layer;
A protective film provided on the multilayer wiring layer and having an opening on the electrode pad;
A connection terminal provided on the electrode pad and on the protective film and connected to the wiring board via the solder terminal;
Have
The connection terminal has a cross-sectional area in a first cross section parallel to the surface of the protective film at an end in contact with the solder terminal, more than a cross-sectional area in a second cross section located on the same plane as the surface of the protective film. big,
The method of manufacturing an electronic device, wherein the solder terminal has a small area portion whose sectional area is smaller than the sectional area in the first section.
JP2012051293A 2012-03-08 2012-03-08 Electronic device and method for manufacturing electronic device Pending JP2013187353A (en)

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WO2015129900A1 (en) * 2014-02-28 2015-09-03 日本発條株式会社 Spring member and pressing unit
US9530744B2 (en) 2014-02-10 2016-12-27 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
JP2017069283A (en) * 2015-09-28 2017-04-06 日亜化学工業株式会社 Package, light-emitting device, light-emitting module and package manufacturing method
US9818709B2 (en) 2015-04-30 2017-11-14 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530744B2 (en) 2014-02-10 2016-12-27 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
WO2015129900A1 (en) * 2014-02-28 2015-09-03 日本発條株式会社 Spring member and pressing unit
JPWO2015129900A1 (en) * 2014-02-28 2017-03-30 日本発條株式会社 Spring member and pressing unit
US9818709B2 (en) 2015-04-30 2017-11-14 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US10008466B2 (en) 2015-04-30 2018-06-26 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
JP2017069283A (en) * 2015-09-28 2017-04-06 日亜化学工業株式会社 Package, light-emitting device, light-emitting module and package manufacturing method

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