JP3003510B2 - Method for forming electrode part of wiring board - Google Patents
Method for forming electrode part of wiring boardInfo
- Publication number
- JP3003510B2 JP3003510B2 JP16681094A JP16681094A JP3003510B2 JP 3003510 B2 JP3003510 B2 JP 3003510B2 JP 16681094 A JP16681094 A JP 16681094A JP 16681094 A JP16681094 A JP 16681094A JP 3003510 B2 JP3003510 B2 JP 3003510B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- forming
- wiring board
- layer
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路素子
（以下、チップと称する）を搭載し、外部回路に接続す
るために用いる配線基板に関する。詳しくは、ボール・
グリッド・アレイ型（Ball Grid Array …以下、ＢＧＡ
と称する）の半導体パッケージ向けの配線基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which a semiconductor integrated circuit device (hereinafter referred to as a chip) is mounted and used for connecting to an external circuit. For more information,
Grid array type (Ball Grid Array… below, BGA
(Hereinafter referred to as a wiring board) for semiconductor packages.
【０００２】[0002]
【従来の技術】従来、チップをプリント配線板などの外
部回路に接続するための代表的な装置として、クワッド
・フラット・パッケージ（Quad Flat Package …以下、
ＱＦＰと称する）がある。2. Description of the Related Art Conventionally, as a typical device for connecting a chip to an external circuit such as a printed wiring board, a quad flat package (hereinafter referred to as "quad flat package") has been used.
QFP).
【０００３】ＱＦＰは、パッケージの内部でチップとリ
ードフレームのインナー・リードとをワイヤボンディン
グ等により接続し、チップを含む領域を樹脂にてモール
ドしてパッケージとし、その四辺からリードフレームの
アウター・リードを引き出し、前記リードをガルウィン
グ状に形成し、外部回路と接続する方式の半導体パッケ
ージであり、最も広く普及している。（図３参照）In a QFP, a chip and an inner lead of a lead frame are connected by wire bonding or the like inside a package, a region including the chip is molded with a resin to form a package, and outer leads of the lead frame are formed from four sides thereof. A semiconductor package of a type in which the leads are formed in a gull-wing shape and connected to an external circuit is most widely used. (See Fig. 3)
【０００４】昨今、新規な上記の接続用装置として、Ｂ
ＧＡ型の半導体パッケージが普及しつつある。[0004] Recently, as a new connection device described above, B
GA type semiconductor packages are becoming widespread.
【０００５】前記パッケージは、特開昭59−172758号公
報に例示されるような、外部回路に直接的表面取付けが
できるリードレス・チップキャリヤに関するものであ
り、 複数のワイヤボンドパッド51によって取り囲まれたダ
イボンディング部位を有する上方のボンディング面。
（図５(a) 参照） 前記上方のボンディング面に対向し、内側のはんだパ
ッド52配列を含む下方のはんだ付け面。（図５(b) 参
照） 前記はんだパッド52の一部を前記ワイヤボンドパッド
51の一部に電気的に結合する手段53。（図５(c) 参照） 前記内側のはんだパッド52を取り囲んでいる前記下方
のはんだ付け面の絶縁性周辺部位54。（図５(c) 参照） を具えることを特徴とする。（図５参照）The above-mentioned package relates to a leadless chip carrier which can be directly mounted on an external circuit as exemplified in Japanese Patent Application Laid-Open No. Sho 59-172758, and is surrounded by a plurality of wire bond pads 51. Upper bonding surface having a die bonding site.
(See FIG. 5 (a).) A lower soldering surface facing the upper bonding surface and including an array of inner solder pads 52. (See FIG. 5B.) A part of the solder pad 52 is replaced with the wire bond pad.
Means 53 for electrically coupling to a portion of 51; (See FIG. 5 (c).) An insulating peripheral portion 54 of the lower soldering surface surrounding the inner solder pad 52. (See FIG. 5 (c)). (See Fig. 5)
【０００６】また、これに似た形態の半導体パッケージ
として、上記はんだパッドの代わりに金属ピンを立てた
構造で、プリント配線板に予め形成したスルーホールに
挿入してはんだ付けすることで固定する、いわゆるピン
・グリッド・アレイ型（PinGrid Array…以下、ＰＧＡ
と称する）の半導体パッケージがある。（図４参照）Further, as a semiconductor package of a similar form, a structure in which metal pins are provided in place of the above solder pads is inserted into a through hole formed in a printed wiring board in advance and fixed by soldering. The so-called Pin Grid Array type (PGA)
Semiconductor package). (See Fig. 4)
【０００７】なお、上記参照図面では、チップの端子の
数およびリードの本数が９個についての場合で説明を簡
略化している。In the above reference drawings, the description is simplified for the case where the number of terminals of the chip and the number of leads are nine.
【０００８】ＱＦＰに対してのＢＧＡの利点は、特に実
装密度の向上にあり、ＱＦＰを取り付けるのに必要な外
部回路基板の実質的面積よりも、ＢＧＡを取り付けるの
に必要な前記面積が大幅に小さくなる点にある。また、
リードフレームと異なり、配線基板では配線パターンの
設計が自在であり、１つのモジュールにチップを複数個
搭載することが容易となる。このタイプの半導体装置
は、マルチ・チップ・モジュール（Multi-Chip-Module
＝ＭＣＭ）として昨今普及しつつある。[0008] The advantage of the BGA over the QFP is, in particular, an increase in the packing density, and the area required for mounting the BGA is significantly larger than the substantial area of the external circuit board required for mounting the QFP. The point is that it becomes smaller. Also,
Unlike the lead frame, the wiring pattern of the wiring board can be freely designed, and it is easy to mount a plurality of chips on one module. This type of semiconductor device is a multi-chip module (Multi-Chip-Module).
= MCM).
【０００９】一般的なＢＧＡ型の半導体パッケージは、
プリント配線板用の銅張積層板（エポキシ樹脂等からな
る絶縁性基材の両面または片面に、銅箔を貼り合わせた
もの）をベース材料（上記）とし、これをフォトエッ
チング法等の方法で加工して、チップ搭載部と配線部
（上記と）を形成している。A general BGA type semiconductor package is:
A copper-clad laminate for printed wiring boards (a copper foil bonded to both sides or one side of an insulating substrate made of epoxy resin or the like) is used as a base material (described above), and this is obtained by a method such as a photoetching method. By processing, a chip mounting portion and a wiring portion (as described above) are formed.
【００１０】配線基板を外部回路（プリント配線板）に
直接接続するために、球状のはんだパッド（以下、本明
細書においては、「球状のはんだパッド」も「はんだボ
ール」も同義語であり、混在して用いる）を前記基板の
下面に設ける際、はんだボールの形状や大きさ（高さ）
は、電極端子の表面に滴下するはんだペーストの量や滴
下のさせ方に依存する。In order to directly connect a wiring board to an external circuit (printed wiring board), a spherical solder pad (hereinafter, in this specification, “spherical solder pad” and “solder ball” are synonyms; When used on the lower surface of the substrate, the shape and size (height) of the solder ball
Depends on the amount of the solder paste dropped on the surface of the electrode terminal and the manner of dropping.
【００１１】そのため、各ボールにバラツキが生じ、配
線基板と外部回路（プリント配線板）との接続にあたっ
ては、接続不良が発生する原因となる。As a result, variations occur in each ball, which causes a connection failure when connecting the wiring board to an external circuit (printed wiring board).
【００１２】[0012]
【発明が解決しようとする課題】本発明は、ＢＧＡのは
んだボールに要求されている、形状や大きさの均一化を
実現することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to realize a uniform shape and size required for BGA solder balls.
【００１３】[0013]
【課題を解決するための手段】本発明では、配線基板の
下面に形成した樹脂層の電極端子部分に、はんだボール
形成部となる凹部を設け、前記凹部にはんだペーストを
滴下する。According to the present invention, a concave portion serving as a solder ball forming portion is provided in an electrode terminal portion of a resin layer formed on a lower surface of a wiring board, and a solder paste is dropped into the concave portion.
【００１４】請求項１に記載の本発明は、以下の工程を
備えることを特徴とする配線基板の電極部形成方法であ
る。 （ａ）外部回路への表面取付け用端子となる終端が、下
面に略マトリクス状に配置されて導電層がパターニング
された配線基板の前記下面に、金属層を全面に形成する
工程。 （ｂ）前記金属層を、前記終端に対応して略マトリクス
状に配置されるようにパターニングする工程。 （ｃ）前記下面に、エポキシ樹脂やポリイミド樹脂等の
樹脂層を全面に塗布形成する工程。 （ｄ）前記樹脂層表面に、金属層を全面に形成する工
程。 （ｅ）前記金属層を、工程（ｂ）における略マトリクス
状に配置された金属層に対応する箇所が開口するよう
に、パターニングする工程。 （ｆ）前記開口部にレーザー光線を照射し、その部分の
樹脂層を除去し、凹部を形成する工程。 （ｇ）工程（ｅ）でパターニングされた金属層を除去し
た後、前記凹部にはんだペーストを滴下し、球状パッド
を形成する工程。According to a first aspect of the present invention, there is provided a method for forming an electrode portion of a wiring board, comprising the following steps. (A) A step of forming a metal layer on the entire lower surface of the wiring board on which the conductive layer is patterned by arranging the terminations to be the terminals for surface attachment to the external circuit on the lower surface. (B) patterning the metal layer so as to be arranged substantially in a matrix corresponding to the terminal end; (C) a step of applying and forming a resin layer such as an epoxy resin or a polyimide resin on the entire lower surface. (D) forming a metal layer on the entire surface of the resin layer; (E) a step of patterning the metal layer so that a portion corresponding to the metal layer arranged in a substantially matrix shape in step (b) is opened. (F) a step of irradiating the opening with a laser beam, removing the resin layer in that portion, and forming a recess. (G) a step of forming a spherical pad by dropping a solder paste into the recess after removing the metal layer patterned in step (e).
【００１５】請求項２に記載の発明は、前記工程（ａ）
および工程（ｄ）において形成する金属層が銅からなる
ことを特徴とする。[0015] The invention as set forth in claim 2 is characterized in that the step (a)
And the metal layer formed in the step (d) is made of copper.
【００１６】請求項３に記載の発明は、前記工程（ｂ）
においてパターニングした金属層表面に、Ａｕ−Ｎｉメ
ッキを施す工程を付加することを特徴とする。According to a third aspect of the present invention, in the step (b),
A step of applying an Au-Ni plating to the surface of the metal layer patterned in the method described above.
【００１７】請求項４に記載の発明は、工程（ｃ）に次
いで、前記略マトリクスに対応した開口を有するマスク
を介して、集光したレーザービームにより、前記マスク
の開口部を走査露光することを特徴とする。According to a fourth aspect of the present invention, after the step (c), the opening of the mask is scanned and exposed by a focused laser beam through a mask having an opening corresponding to the substantially matrix. It is characterized by.
【００１８】[0018]
【作用】レーザー光線の選択的な照射によって形成され
た凹部にはんだペーストを滴下することによるため、は
んだボールの形状は前記凹部の形状に依存することにな
る。前記凹部の形成は、フォトエッチングで形成された
レーザー照射部へのレーザー照射によるため、形状等の
均一化は容易であり、はんだボールの形状も均一化させ
易い。The shape of the solder ball depends on the shape of the recess because the solder paste is dropped into the recess formed by the selective irradiation of the laser beam. Since the formation of the concave portion is performed by irradiating a laser irradiation portion formed by photoetching with a laser, it is easy to make the shape and the like uniform, and it is easy to make the shape of the solder ball uniform.
【００１９】前記凹部は、絶縁性材料（エポキシ樹脂や
ポリイミド樹脂等の樹脂層）に形成されるため、隣り合
うはんだボール同士の電気的短絡の惧れがない。Since the recess is formed in an insulating material (a resin layer such as an epoxy resin or a polyimide resin), there is no fear of an electrical short circuit between adjacent solder balls.
【００２０】電極端子である金属層表面に、Ａｕ−Ｎｉ
メッキを施すことにより、その後のレーザー加工（工程
(f) ）やフォトエッチング加工（工程(e) ）において、
前記メッキ層がストッパの役割を果たすことになる。On the surface of the metal layer as the electrode terminal, Au-Ni
By applying plating, subsequent laser processing (process
(f)) and photo-etching (step (e))
The plating layer functions as a stopper.
【００２１】[0021]
【実施例】以下、本発明の実施例を製造工程順に示す図
面を用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings showing the order of manufacturing steps.
【００２２】＜実施例１＞周知のプリント配線板と同様
の構成であるが、導体パターン11の終端部12が下面にお
いて略マトリクス状に配置された配線基板10を用いる。
（図１参照）<Embodiment 1> The wiring board 10 has the same structure as a known printed wiring board, but uses a wiring board 10 in which terminal portions 12 of a conductor pattern 11 are arranged in a substantially matrix on the lower surface.
(See Fig. 1)
【００２３】前記配線基板10の下面に、スパッタリング
またはメッキによりＣｕ層（金属層13）を全面に形成す
る。（図２(a) 参照）On the lower surface of the wiring substrate 10, a Cu layer (metal layer 13) is formed on the entire surface by sputtering or plating. (See Fig. 2 (a))
【００２４】前記金属層13を、フォトエッチング加工に
よって、前記終端部12に対応して略マトリクス状に配置
されるようにパターニングし、電極端子とする。（図２
(b)参照）The metal layer 13 is patterned by photo-etching so as to be arranged substantially in a matrix corresponding to the terminal portion 12, thereby forming an electrode terminal. (Figure 2
(See (b))
【００２５】前記電極端子13に、電解メッキまたは無電
解メッキにより、Ａｕ−Ｎｉメッキ14を施す。（図２
(b')参照） 前記メッキ層14は、後でレーザー照射に対するストッパ
として機能することになるので、レーザー光の反射が大
きい材質であることが望ましい。また、後ではんだパッ
ドを形成する電極端子の表面であるので、はんだとの密
着性（濡れ性）の良好な材質であることが望ましい。An Au—Ni plating 14 is applied to the electrode terminals 13 by electrolytic plating or electroless plating. (Figure 2
(Refer to (b ').) Since the plating layer 14 functions as a stopper for laser irradiation later, it is preferable that the plating layer 14 be made of a material that reflects a large amount of laser light. Further, since it is the surface of the electrode terminal on which a solder pad is to be formed later, it is desirable that the material be good in adhesion (wetting) to the solder.
【００２６】さらにその表面に、エポキシ樹脂やポリイ
ミド樹脂等の樹脂層15を全面に塗布形成する。（図２
(c) 参照） 前記樹脂層15は、後ではんだボール形成部となり、溶融
したはんだが滴下されることもあるため、はんだの融点
での耐熱性の高い材質であることが望ましい。また、は
んだが表面張力によりボール状になりやすいように、は
んだ濡れ性が悪い材質であることが望ましい。Further, a resin layer 15 such as an epoxy resin or a polyimide resin is applied and formed on the entire surface. (Figure 2
(Refer to (c).) Since the resin layer 15 will later become a solder ball forming portion and the molten solder may be dropped, it is preferable that the resin layer 15 be made of a material having high heat resistance at the melting point of the solder. Further, it is preferable that the material is poor in solder wettability so that the solder is easily formed into a ball shape due to surface tension.
【００２７】前記樹脂層15の表面に、Ｃｕ層（金属層1
6）を全面に形成する。（図２(d) 参照）On the surface of the resin layer 15, a Cu layer (metal layer 1) is formed.
6) is formed on the entire surface. (See Fig. 2 (d))
【００２８】前記金属層16を、電極端子13に対応する箇
所が開口するように、フォトエッチング加工によってパ
ターニングし、開口部17を設ける。（図２(e) 参照） 前記開口部17以外の金属層16は、後のレーザー照射に対
するマスクとして機能することになる。The metal layer 16 is patterned by photoetching so as to open an area corresponding to the electrode terminal 13, and an opening 17 is provided. (Refer to FIG. 2E.) The metal layer 16 other than the opening 17 functions as a mask for the subsequent laser irradiation.
【００２９】前記開口部17にレーザー光線を照射し、そ
の部分の樹脂層15を除去し、凹部18を形成する。（図２
(f) 参照） レーザー光線の照射にあたっては、ＹＡＧレーザーやＣ
Ｏ2 レーザーを用い、前記レーザーを集光して、開口部
17を走査露光する。The opening 17 is irradiated with a laser beam, and the resin layer 15 in that portion is removed to form a recess 18. (Figure 2
(See (f)) When irradiating the laser beam, use a YAG laser or C
Using an O 2 laser, focus the laser and open the aperture
17 is scanned and exposed.
【００３０】凹部18の形成後、表面に残った金属層16
（マスク）をエッチングによって除去する。（図２(g)
参照）After the formation of the recess 18, the metal layer 16 remaining on the surface
The (mask) is removed by etching. (Fig. 2 (g)
reference)
【００３１】次いで、前記凹部18にはんだペーストを滴
下し、球状のはんだパッド20を形成する。（図２(g')参
照） はんだパッドの形成にあたっては、固形のはんだボール
を凹部に配置した後、リフロー加熱を行なうことによる
か、ディスペンサではんだペーストを塗布した後、ＩＲ
リフロー装置で加熱してはんだペーストを溶融させるこ
とによっても良い。Next, a solder paste is dropped into the concave portion 18 to form a spherical solder pad 20. (Refer to FIG. 2 (g ').) When forming the solder pad, a solid solder ball is placed in a concave portion, and then reflow heating is performed, or a solder paste is applied using a dispenser, and then an IR is applied.
The solder paste may be melted by heating with a reflow device.
【００３２】＜実施例２＞図２(c) に示す工程に次い
で、電極端子13に対応したパターンで開口を有するマス
クをレーザーマスクとして用いて、同様の走査露光を行
なう。図示はしないが、前記走査露光の方法として、レ
ーザーマスクを配線基板に密着させて開口部を走査露光
する方法と、各開口部に集光用凸レンズが配置され、開
口部を通ったレーザー光がビーム径を絞られて加工部
（開口部17の樹脂層15）に入射させる方法とがある。本
実施例によれば、図(d) 〜(e) に示す金属層16の形成〜
パターニングの工程が省略されることになる。<Embodiment 2> Following the step shown in FIG. 2C, the same scanning exposure is performed using a mask having openings in a pattern corresponding to the electrode terminals 13 as a laser mask. Although not shown, as the method of the scanning exposure, a method in which a laser mask is brought into close contact with a wiring substrate to scan and expose openings, and a converging convex lens is arranged in each opening, and laser light passing through the openings is used. There is a method in which the beam diameter is narrowed and the beam is incident on the processed portion (the resin layer 15 of the opening 17). According to the present embodiment, the formation of the metal layer 16 shown in FIGS.
The patterning step will be omitted.
【００３３】[0033]
【発明の効果】形状や大きさが均一化されたＢＧＡ用の
はんだボールを形成する方法が提供された。According to the present invention, there is provided a method for forming a solder ball for a BGA having a uniform shape and size.
【００３４】[0034]
【図面の簡単な説明】[Brief description of the drawings]
【図１】配線基板の説明図。FIG. 1 is an explanatory diagram of a wiring board.
【図２】本発明を、製造工程順に示す断面説明図。FIG. 2 is an explanatory cross-sectional view showing the present invention in the order of manufacturing steps.
【図３】従来のチップキャリア（ＱＦＰ）の説明図。FIG. 3 is an explanatory diagram of a conventional chip carrier (QFP).
【図４】従来のチップキャリア（ＰＧＡ）の説明図。FIG. 4 is an explanatory diagram of a conventional chip carrier (PGA).
【図５】従来のＢＧＡ方式のチップキャリアのの説明
図。FIG. 5 is an explanatory view of a conventional BGA type chip carrier.
10…配線基板 11…導体パターン 12…終端部 13…金属層（電極端子） 14…Ａｕ−Ｎｉメッキ 15…樹脂層 16…金属層 17…開口部 18…凹部 20…はんだパッド 10 ... wiring board 11 ... conductor pattern 12 ... terminal part 13 ... metal layer (electrode terminal) 14 ... Au-Ni plating 15 ... resin layer 16 ... metal layer 17 ... opening 18 ... recess 20 ... solder pad
Claims (4)
面取付けができるように略マトリクス状に球状パッドを
配置するにあたって、以下の工程を備えることを特徴と
する配線基板の電極部形成方法。 （ａ）外部回路への表面取付け用端子となる終端が、下
面に略マトリクス状に配置されて導電層がパターニング
された配線基板の前記下面に、金属層を全面に形成する
工程。 （ｂ）前記金属層を、前記終端に対応して略マトリクス
状に配置されるようにパターニングする工程。 （ｃ）前記下面に、エポキシ樹脂やポリイミド樹脂等の
樹脂層を全面に塗布形成する工程。 （ｄ）前記樹脂層表面に、金属層を全面に形成する工
程。 （ｅ）前記金属層を、工程（ｂ）における略マトリクス
状に配置された金属層に対応する箇所が開口するよう
に、パターニングする工程。 （ｆ）前記開口部にレーザー光線を照射し、その部分の
樹脂層を除去し、凹部を形成する工程。 （ｇ）工程（ｅ）でパターニングされた金属層を除去し
た後、前記凹部にはんだペーストを滴下し、球状パッド
を形成する工程。1. A method of forming an electrode portion on a wiring board, comprising the steps of: arranging spherical pads on a lower surface of the wiring board in a substantially matrix so as to allow direct surface mounting with an external circuit. Method. (A) A step of forming a metal layer on the entire lower surface of the wiring board on which the conductive layer is patterned by arranging the terminations to be the terminals for surface attachment to the external circuit on the lower surface. (B) patterning the metal layer so as to be arranged substantially in a matrix corresponding to the terminal end; (C) a step of applying and forming a resin layer such as an epoxy resin or a polyimide resin on the entire lower surface. (D) forming a metal layer on the entire surface of the resin layer; (E) a step of patterning the metal layer so that a portion corresponding to the metal layer arranged in a substantially matrix shape in step (b) is opened. (F) a step of irradiating the opening with a laser beam, removing the resin layer in that portion, and forming a recess. (G) a step of forming a spherical pad by dropping a solder paste into the recess after removing the metal layer patterned in step (e).
する金属層が銅からなる請求項１に記載の配線基板の電
極部形成方法。2. The method according to claim 1, wherein the metal layer formed in the steps (a) and (d) is made of copper.
層表面に、Ａｕ−Ｎｉメッキを施す工程を付加すること
を特徴とする請求項１または請求項２に記載の配線基板
の電極部形成方法。3. The method for forming an electrode part on a wiring board according to claim 1, wherein a step of applying Au-Ni plating to the surface of the metal layer patterned in step (b) is added.
対応した開口を有するマスクを介して、集光したレーザ
ービームにより、前記マスクの開口部を走査露光するこ
とを特徴とする請求項１または請求項３に記載の配線基
板の電極部形成方法。4. The method according to claim 1, further comprising, after step (c), scanning and exposing the opening of the mask with a focused laser beam through a mask having an opening corresponding to the substantially matrix. 4. The method for forming an electrode part on a wiring board according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16681094A JP3003510B2 (en) | 1994-07-19 | 1994-07-19 | Method for forming electrode part of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16681094A JP3003510B2 (en) | 1994-07-19 | 1994-07-19 | Method for forming electrode part of wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0831979A JPH0831979A (en) | 1996-02-02 |
| JP3003510B2 true JP3003510B2 (en) | 2000-01-31 |
Family
ID=15838095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16681094A Expired - Fee Related JP3003510B2 (en) | 1994-07-19 | 1994-07-19 | Method for forming electrode part of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3003510B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0841840A1 (en) * | 1996-11-12 | 1998-05-13 | Hewlett-Packard Company | Method for the manufacture of micro solder bumps on copper pads |
| JPH1174651A (en) | 1997-03-13 | 1999-03-16 | Ibiden Co Ltd | Printed wiring board and its manufacture |
| JP3870778B2 (en) * | 2001-12-20 | 2007-01-24 | ソニー株式会社 | Manufacturing method of element-embedded substrate and element-embedded substrate |
-
1994
- 1994-07-19 JP JP16681094A patent/JP3003510B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0831979A (en) | 1996-02-02 |
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