JP3795628B2 - Manufacturing method of wiring board mounting semiconductor chip - Google Patents

Manufacturing method of wiring board mounting semiconductor chip Download PDF

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Publication number
JP3795628B2
JP3795628B2 JP12676297A JP12676297A JP3795628B2 JP 3795628 B2 JP3795628 B2 JP 3795628B2 JP 12676297 A JP12676297 A JP 12676297A JP 12676297 A JP12676297 A JP 12676297A JP 3795628 B2 JP3795628 B2 JP 3795628B2
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Prior art keywords
wiring board
electrode
semiconductor chip
solder
semiconductor device
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JP12676297A
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JPH10321750A (en
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敦 小村
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Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof

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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable suppression of stresses to a connection part caused by connecting a semiconductor chip to an external wiring board, even when a volume of projected terminals of a semiconductor device is decreased with an increased number of output terminals of the semiconductor chip, to thereby secure a connection reliability. SOLUTION: A wiring board 17 is provided on its solder ball mounting side with a base material 6, made of a BT resin glass cloth or an epoxy resin glass cloth. Formed on the base material is a buffer layer 7 having an elastic modulus of 0.5-5 kgf/mm<2> . Formed on the buffer layer is a pad electrode 10, on which wiring and solder balls 11 are formed. The solder balls 11 are made of a composition with Sn and Pb in an Sn/Pb ratio of 6:4.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップを配線基板に搭載し半導体チップと配線基板とを電気的な接続を行い、その接続部を覆うように樹脂で封止し、配線基板上に外部の配線基板と接続を行うためのハンダ突起端子を設けた半導体装置に使用する、半導体チップを搭載する配線基板の製造方法に関する。
【０００２】
【従来の技術】
近年、半導体装置の高機能化にともない、半導体装置の外部端子の数は増大する傾向にあり、側面に外部端子を設けているＱＦＰのような半導体装置は外部端子の端子ピッチを狭くしたとしても、外形サイズが大きくなってしまう傾向にある。
これにたいして、ＢＧＡあるいはＣＳＰのような電極端子をアレイ上に配置できる半導体装置は、外部端子の増加ができ、且つＱＦＰよりも外形サイズを小さくすることが可能である。このような半導体装置の例としては配線基板を使用した半導体装置として、たとえば特開平６−３４９９７３号公報や、配線基板を使用しない半導体装置として特開平２−４９４６０号公報があげられる。
【０００３】
配線基板を使用した電極端子をアレイ上に形成した半導体装置の構造について図２３を用いて説明する。
図２３は、前述の特開平６−３４９９７３号公報に開示された半導体装置を示す断面図である。
【０００４】
半導体チップ１２０上には合金系の突起電極１２２が形成されている。配線基板１２６には半導体チップ１２０の突起電極１２２の配置に対応するように形成された電極１２３が形成され、他面には外部の配線基板との接続するようにパッド電極１２４が形成されている。
半導体チップ１２０と配線基板１２６とは、半導体チップ１２０に形成した突起電極１２２で電気的接続を行い、半導体チップ１２０を覆うように樹脂１２１で封止されている。配線基板１２６の他面のパッド電極上には合金系の突起端子１２５が形成されている。
【０００５】
配線基板を使用しない電極端子をアレイ上に形成した半導体装置の構造について、図２４を用いて説明する。
図２４は前述の特開平２−４９４６０号公報に開示された半導体装置を示す断面図である。
【０００６】
半導体チップ１３０の主表面上には電極１３１が形成されていて、この電極は外部の配線基板との接続するための突起端子１３５の一部として機能している。電極１３１の一部表面の露出させるように、半導体チップ１３０の表面にパッシベーション膜が形成されている。電極１３１の一部表面上に外部の配線基板との接続するための突起端子１３５が形成されている。この突起端子１３５の一部を露出させ、かつ半導体チップ全体を覆うように樹脂１３２で封止されている。
【０００７】
【発明が解決しようとする課題】
しかしながら、半導体チップの出力端子が増加すると、アレイ状に形成している突起端子の間隔を狭めなければならなくなり、これによって突起端子の体積が小さくなってしまう。
これによって配線基板あるいは半導体装置に直接突起端子に形成した前述のような半導体装置では、外部の配線基板と接続したとき、外部の配線基板と半導体装置との間隔が狭くなり、さらに温度サイクル試験等の環境試験に投入することによって発生する接続部への応力が増大し、半導体装置の熱疲労寿命が低下してしまう。接続不良になった半導体装置は突起端子の根本で破断を起こしている。
【０００８】
また、図２３にしめすような半導体チップを配線基板にフェイスダウンで搭載する半導体装置の構造においては、半導体チップと配線基板に電気的な接続を半導体チップに形成した合金系の突起電極で行うので、前述のように半導体チップの出力端子が増加すると、突起電極の間隔も狭めなければならなくなり、よって突起電極の体積が小さくなってしまう。
これによって半導体チップを配線基板に搭載したとき、半導体チップと配線基板との間隔が狭くなり、半導体装置を単体で温度サイクル試験等の環境試験に投入することによって発生する接続した突起電極への応力が増大し、半導体チップの接続した突起電極の熱疲労寿命が低下してしまう。
【０００９】
〔発明の目的〕
本発明の第１の目的は、前述の課題を解決して、半導体チップの出力端子の増加に伴い突起端子の体積が小さくなっても、外部の配線基板と接続したことによって発生する接続部への応力を緩和して接続信頼性を損なわない半導体装置を実現することができる、半導体チップを搭載する配線基板の製造方法を提供することである。
【００１０】
本発明のもう１つの目的は、半導体チップを配線基板にフェイスダウンで搭載する半導体装置の構造において、前述の目的に加えて半導体チップの出力端子の増加に伴い突起電極の体積が小さくなっても、配線基板と接続したことによって発生する突起電極への応力を緩和して接続信頼性を損なわない半導体装置に使用する半導体チップを搭載する配線基板の製造方法を提供することにある。
【００１１】
【課題を解決するための手段】
前述した目的を達成するために、本発明の半導体チップを搭載する配線基板の製造方法は、下記記載の手段を採用する。
【００１２】
本発明の半導体チップを搭載する配線基板の製造方法は、ＢＴレジンガラス布やエポキ
シ樹脂ガラス布であるベース基材の両面に弾性率が０．５〜５ｋｇｆ／ｍｍ ２ であるフィルム状の緩和層と更にそれら緩和層の両方の外側にＣｕ箔を配し、両側より加圧および加温して積層成形板を得る工程と、該積層成形板を貫通するスルーホールを形成する工程と、該スルーホールを含め前記Ｃｕ箔に配線を形成する工程と、半導体チップの電極との電気的接続を行うための電極と外部の配線基板との電気的接続を行うためのパッド電極を形成する工程とを有することを特徴とする。
【００１３】
本発明の半導体チップを搭載する配線基板の製造方法は、ＢＴレジンガラス布やエポキシ樹脂ガラス布であるベース基材の、一方の面にＣｕ箔を配し、他方の面に弾性率が０．５〜５ｋｇｆ／ｍｍ ２ であるフィルム状の緩和層と更にその上にＣｕ箔とを配し、両側より加圧および加温して積層成形板を得る工程と、該積層成形板を貫通するスルーホールを形成する工程と、該スルーホールを含め前記Ｃｕ箔に配線を形成する工程と、前記一方の面に半導体チップの電極との電気的接続を行うための電極と前記他方の面に外部の配線基板との電気的接続を行うためのパッド電極を形成する工程とを有することを特徴とする。
【００１５】
【発明の実施の形態】
以下、図面を用いて本発明の半導体チップを搭載する配線基板の製造方法における最適な実施形態の説明を行う。
まずはじめに本発明の配線基板を用いた半導体装置の構造を説明する。
【００１６】
〔第１の参考例である半導体装置の構造説明：図１〜図５〕
本発明の配線基板を用いた第１の参考例である半導体装置の構造の実施形態について、図１〜図５を用いて説明する。図１は半導体装置の断面図であり、図２は半導体チップ１の電極１６側から見た平面図であり、図３は半導体チップ１の断面図であり、図４は配線基板１７の半導体チップ１搭載側から似た平面図であり、図５は配線基板１７の断面図である。
【００１７】
半導体チップ１は図２、図３を用いて説明する。シリコン基板１４上に電子回路を形成し、その回路の外部端子としてＡｌまたはＡｕなどで電極１６が形成されている。電極１６の材料あるいは表面処理については配線基板１７とをワイヤー８で結線する際のワイヤー８の材料やボンダビリティーを考慮して選択する。半導体チップ１の電極１６以外の部分は窒化シリコン膜等の無機膜か前述の無機膜にさらにその上にポリイミド等の有機膜による保護膜１５で覆われ、外部とは電気的に絶縁されている。
【００１８】
配線基板１７については図４、図５を用いて説明する。配線基板１７の半導体チップ１の裏面を搭載するエリア１８にはダイアタッチパターン１２が形成されていて、半導体チップ１を搭載した際の電源グランドおよび半導体チップ１から発生する熱を放熱する役割を兼ねている。
ダイアタッチパターン１２内には複数のサーマルビアホール２１を形成している。サーマルビアホール２１は半導体チップ１より発生した熱を配線基板１７のハンダボール面に逃がす役割とダイアタッチパターン１２と配線基板１７のパッド電極１０とを電気的に接続することを兼ねている。
またサーマルビアホール２１や他のスルーホール１３内にはエポキシ樹脂９が埋められており、配線基板１７のハンダボール１１搭載側から半導体チップ１搭載側への水分の侵入を抑えることができる。
【００１９】
電極１９は、半導体チップ１の電極１６とをワイヤー８で結線するための電極で、Ｃｕ上にＡｕ／Ｎｉメッキを施している。ワイヤー８のボンダビリティーを考慮し、Ｎｉ層の厚さが３μｍ〜１５μｍ、Ａｕ層の厚さが０．３μｍ〜１μｍで形成している。
【００２０】
配線基板１７の半導体チップ１を搭載する側は、前述のダイアタッチパターン１２、電極１９以外部分はソルダーレジスト４で覆われている。
【００２１】
配線基板１７のハンダボール搭載側はＢＴレジンガラス布やエポキシ樹脂ガラス布等の基材６上に弾性率が０．５〜５ｋｇｆ／ｍｍ2 の緩和層７を形成し、その上に配線やハンダボール１１を搭載するパッド電極１０を形成している。
【００２２】
パッド電極１０はハンダボール１１を搭載する際にハンダボール１１がパッド電極１０に対してハンダが充分に濡れ、かつ充分な密着強度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッキを施している。それぞれ金属層の厚さは、Ｎｉ層の厚さが３μｍ〜５μｍ、Ａｕ層の厚さを０．０２μｍ〜０．０５μｍで形成している。
【００２３】
配線基板１７のハンダボール１１を搭載する側は前述のパッド電極１０以外部分はソルダーレジスト５で覆われている。
【００２４】
半導体装置については前述の半導体チップ１、配線基板１７を含め図１を用いて説明する。半導体チップ１は配線基板１７上のダイアタッチパターン１２上に接着剤３を用いて固定している。接着剤３はエポキシ樹脂にＡｇのフィラーを含有しているので、半導体チップ１をダイアタッチパターン１２上に搭載した際の電源グランドへの電気的接続および半導体チップ１から発生する熱をダイアタッチパターン１２へ放熱することができる。
【００２５】
半導体チップ１上の各電極１６と配線基板１７上の電極１９との電気的接続はＡｕのワイヤー８で行われている。Ａｕのワイヤー径は０．０３ｍｍ〜０．０５ｍｍ程度のワイヤーを使用している。電極１９とパッド電極１０とはスルーホールを介して電気的に接続している。
【００２６】
半導体チップ１、ワイヤー８および配線基板１７の電極１９は、遮蔽と保護のために封止樹脂２で封止している。封止樹脂２には熱硬化性のエポキシ系樹脂を使用している。
【００２７】
さらに、配線基板１７のパッド電極１０には、ハンダボール１１を形成している。このハンダボール１１には、ＳｎとＰｂとの比率が６：４の組成のハンダを用いている。
このハンダボール１１を介してこの半導体装置と外部の配線基板との電気的接続を行っている。
【００２８】
〔第２の参考例である半導体装置の構造説明：図６〜図１０〕
つぎに、本発明の配線基板を用いた第２の参考例である半導体装置の構成の説明を行う。
本発明の配線基板を用いた第２の参考例である半導体装置の構造の実施形態について、図６から図１０を用いて説明する。図６は半導体装置の断面図であり、図７は半導体チップ３０の突起電極３３側から見た平面図であり、図８は半導体チップ３０の断面図であり、図９は配線基板３９の半導体チップ３０搭載側から似た平面図であり、図１０は配線基板３９の断面図である。
【００２９】
半導体チップ３０は図７と図８とを用いて説明する。
シリコン基板４５上に電子回路を形成し、その回路の外部端子としてＡｌなどで電極４６が形成されている。電極４６の上に配線基板３９の電極４７との電気的接続を行うためにＣｕあるいはＡｕの突起電極３３を形成している。
【００３０】
Ａｌの電極４６上にＣｕあるいはＡｕの突起電極３３形成するためにバリアメタル層４３を蒸着法やスパッタリング法を用いて形成したのちに、その上にＣｕあるいはＡｕの突起電極３３をメッキによって形成する。バリアメタル層４３は電極４６と突起電極３３のそれぞれの金属の相互拡散を防止するために形成している。
【００３１】
半導体チップ３０の電極４６以外の部分は、窒化シリコン膜等の無機膜か前述の無機膜にさらにその上にポリイミド等の有機膜による保護膜４４で覆われ、外部とは電気的に絶縁されている。
【００３２】
配線基板３９については図９と図１０とを用いて説明する。
配線基板３９の半導体チップ３０搭載側およびハンダボール４１搭載側の両側には、ＢＴレジンガラス布やエポキシ樹脂ガラス布などの基材３７上に弾性率が０．５〜５ｋｇｆ／ｍｍ2 の緩和層３５を形成し、その上に配線、電極４７およびハンダボール４１を搭載するパッド電極５２を形成している。
突起電極３３に使用する金属の弾性率はＣｕが１３０×１０5 ｋｇｆ／ｍｍ2 で、Ａｕが７８×１０4 ｋｇｆ／ｍｍ2 とハンダが３２×１０4 ｋｇｆ／ｍｍ2に比べて堅い材料であることから、半導体チップ３０と配線基板の線膨張係数の違いにより発生する応力が突起電極３３の根本に集中するのでこれを緩和するために、配線基板３９の半導体チップ３０搭載側にも緩和層３５を形成している。
【００３３】
配線基板３９の電極４７は半導体チップ３０に形成している突起電極３３の配置に対応するように形成している。スルーホール内４０にはエポキシ樹脂４２が埋められており、配線基板３９のハンダボール４１搭載側から半導体チップ３０搭載側への水分の侵入を抑えることができる。
【００３４】
電極４７は半導体チップ３０の突起電極３３とを電気的に接続をするために、電極４７のＣｕ上にハンダ層４８を施している。このハンダ層４８には、ＳｎとＰｂとの比率が６：４の組成のハンダを用いている。
このハンダ層４８を溶融して、半導体チップ３０の突起電極３３と接続を行っている。ハンダ層の厚さは２００μｍ〜５００μｍ程度で形成している。
【００３５】
配線基板３９の半導体チップ３０を搭載する側は、前述の電極４７以外部分はソルダーレジスト３４で覆われている。
【００３６】
ハンダボール４１搭載側のパッド電極５２はハンダボール４１を搭載する際にハンダボール４１がパッド電極５２に対してハンダが充分に濡れ、かつ充分な密着強度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッキを施している。各金属層の厚さはＮｉ層の厚さが３〜５μｍ、Ａｕ層の厚さは０．０２μｍ〜０．０５μｍで形成している。
【００３７】
配線基板３９のハンダボール４１を搭載する側は、前述のパッド電極５２以外部分はソルダーレジスト３４で覆われている。
【００３８】
半導体装置については前述の半導体チップ３０、配線基板３９を含め図６を用いて説明する。半導体チップ１上の各突起電極３３と配線基板３９上の電極４７との電気的接続は電極４７上に形成したハンダ層４８を溶融し、突起電極３３と電極４７との接続する。電極４７とパッド電極５２とはスルーホールを介して電気的に接続している。
【００３９】
半導体チップ３０と配線基板３９とのあいだには、接続部の信頼性向上および半導体チップ３０および配線基板３９に形成されている回路の保護のために封止樹脂３２で封止している。封止樹脂３２には熱硬化性のエポキシ系樹脂を使用している。
【００４０】
さらに、配線基板３９のパッド電極５２には、ハンダボール４１を形成している。このハンダボール４１には、ＳｎとＰｂとの比率が６：４の組成のハンダを用いている。
このハンダボール４１を介してこの半導体装置と外部の配線基板との電気的接続を行っている。
【００４１】
〔第３の参考例である半導体装置の構造説明：図１１〜図１５〕
つぎに、本発明の配線基板を用いた第３の参考例である半導体装置の構成の説明を行う。
本発明の第３の参考例については、図１１〜図１５を用いて構造を説明する。図１１は半導体装置の断面図であり、図１２は半導体チップ７０の突起電極７１側から見た平面図であり、図１３は半導体チップ７０の断面図であり、図１４は配線基板８０の半導体チップ７０搭載側から似た平面図であり、図１５は配線基板８０の断面図である。
【００４２】
半導体チップ７０は図１２と図１３とを用いて説明する。
シリコン基板８４上に電子回路を形成し、その回路の外部端子としてＡｌなどで電極８６が形成されている。電極８６の上に配線基板８０の電極８７との電気的接続を行うためにＳｎとＰｂとの比率が６：４の組成のハンダで突起電極７１を形成している。
【００４３】
Ａｌの電極８６上に、ハンダの突起電極７１を形成するためにバリアメタル層８５を蒸着法やスパッタリング法を用いて形成したのちに、その上にハンダの突起電極７１をメッキによって形成する。
バリアメタル層８５は電極８６と突起電極７１のそれぞれの金属の相互拡散を防止するために形成している。
【００４４】
半導体チップ７０の電極８６以外の部分は窒化シリコン膜等の無機膜か前述の無機膜にさらにその上にポリイミド等の有機膜による保護膜７３で覆われ、外部とは電気的に絶縁されている。
【００４５】
配線基板８０については図１１と図１５とを用いて説明する。
配線基板８０のハンダボール８２搭載側にはＢＴレジンガラス布やエポキシ樹脂ガラス布等の基材７６上に弾性率が０．５〜５ｋｇｆ／ｍｍ２の緩和層７７を形成し、その上に配線やハンダボール８２を搭載するパッド電極８１を形成している。
【００４６】
配線基板８０の電極８７は半導体チップ７０に形成している突起電極７１の配置に対応するように形成している。スルーホール７９内にはエポキシ樹脂８３が埋められており、配線基板８０のハンダボール８２搭載側から半導体チップ７０搭載側への水分の侵入を抑えることができる。
【００４７】
電極８７は半導体チップ７０のハンダで形成した突起電極７１が充分に濡れ、しかも充分な密着強度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッキを施している。
それぞれの金属層の厚さは、Ｎｉ層の厚さが３μｍ〜５μｍ、Ａｕ層の厚さは０．０２μｍ〜０．０５μｍで形成している。
【００４８】
配線基板８０の半導体チップ７０を搭載する側は、前述の電極８７以外部分はソルダーレジスト７４で覆われている。
【００４９】
ハンダボール８２搭載側のパッド電極８１はハンダボール８２を搭載する際にハンダボール８２がパッド電極８１に対してハンダが充分に濡れ、かつ充分な密着強度を確保するために、Ｃｕ上にＡｕ／Ｎｉメッキを施している。
それぞれの金属層の厚さは、Ｎｉ層の厚さが３μｍ〜５μｍ、Ａｕ層の厚さは０．０２μｍ〜０．０５μｍで形成している。
【００５０】
配線基板８０のハンダボール８２を搭載する側は前述のパッド電極８１以外部分はソルダーレジスト７４で覆われている。
【００５１】
半導体装置については前述の半導体チップ７０、配線基板８０を含め図１１を用いて説明する。
半導体チップ７０上の各突起電極７１と配線基板８０上のハンダを溶融し、突起電極７１と電極８７とを接続する。電極８７とパッド電極８１とはスルーホールを介して電気的に接続している。
【００５２】
半導体チップ７０と配線基板８０とのあいだには、接続部の信頼性向上および半導体チップ７０および配線基板８０に形成されている回路の保護のために封止樹脂７２で封止している。
封止樹脂７２には熱硬化性のエポキシ系樹脂を使用している。
【００５３】
さらに、配線基板７０のパッド電極８１には、ハンダボール８２を形成している。このハンダボール８２には、ＳｎとＰｂとの比率が６：４の組成のハンダを用いている。
このハンダボール８２を介してこの半導体装置と外部の配線基板との電気的接続を行っている。
【００５４】
〔本発明の配線基板の製造方法：図１６〜図２２〕
つぎに、さきに説明した本発明の第２の参考例に用いた配線基板の製造方法について説明する。図１６〜図２２は本発明の配線基板の製造工程を示す断面図であり、以下これらの図面を用いて説明する。
【００５５】
図１６は配線基板のベースになる基材１００である。この基材１００は厚さが０．２〜０．６ｍｍ程度のＢＴレジンガラス布やエポキシ樹脂ガラス布等を使用する。
基材１００の両面は、その基材１００上に形成する緩和層１０１を密着をよくするために、粗化処理、触媒活性化処理を行う。
【００５６】
両面を粗化処理、触媒活性化処理をおこなった基材１００上にフィルム状の厚さ３０μｍ〜５０μｍの緩和層１０１および緩和層１０１との密着をよくするために表面処理を施した厚さ１８μｍのＣｕ箔１０２を配し、両側より加圧および温度をかけて積層成形する。
これによって基材１００の両面に緩和層１０１を形成した図１７に示す両面板ができる。
【００５７】
両面板に複数のスルーホール１０３をドリル加工あるいはレーザー加工のよって形成する。スルーホール１０３内にＣｕメッキを施すために触媒活性化処理を行い、Ｃｕメッキを行う。これによって図１８に示すようなスルーホール１０３が形成できる。
【００５８】
つぎに図１９に示すようなスルーホール１０３内にエポキシ樹脂１０４充填する。このエポキシ樹脂１０４の充填方法は、スクリーン印刷法を用いて、基板の上面に液状のエポキシ樹脂１０４を供給し、スキージによるスルーホール１０３内への塗り込み行う。塗り込み後エポキシ樹脂１０４を熱硬化し、硬化後基板表面を研磨する。この方法でスルーホール１０３内にエポキシ樹脂１０４を完全に充填できる。
【００５９】
つぎに配線を形成するために、基板両面に感光性樹脂を塗布し、所定の露光マスクを介し露光、現像を行い、配線に必要な部分のみエッチングレジスト膜を形成する。その後Ｃｕのエッチングを行い不要なＣｕ層を除去し、さらにエッチングレジストを除去する。これによって図２０に示すような配線が形成できる。
【００６０】
つぎに電極１０６、パッド電極１０７を形成するために、両面にソルダーレジスト１０８となる感光性樹脂を塗布し、所定のマスクを介し露光、現像を行い、電極１０６、パッド電極１０７のみが露出するようにソルダーレジスト１０８を形成する。
その後、ハンダの濡れ性と密着強度を確保するためにソルダーレジスト１０８をマスクにして、電極１０６、パッド電極１０７上にＡｕ／Ｎｉメッキを行う。各金属層の厚さはＮｉ層の厚さが３μｍ〜５μｍ、Ａｕ層の厚さは０．０２μｍ〜０．０５μｍで形成している。これによって図２１に示すような電極、パッド電極が形成できる。
【００６１】
さらに、電極１０６は、半導体チップの突起電極と電気的に接続をするために、電極１０６上にハンダ層１０９を施している。このハンダ層１０９はスクリーン印刷法を用いて形成する。電極１０６部分のみ開口している所定のメタルマスクを使い、そのマスク上にソルダーペーストを供給し、スキージングすることでマスクの開口部のみソルダーペーストがマスクを通過し、電極１０６部分にソルダーペーストが供給できる。
その後、ハンダの融点よりも高い温度に基板を通過させることによりハンダ層１０９が形成できる。ハンダ層１０９には、ＳｎとＰｂとの比率が６：４の組成のハンダを用い、ハンダ層１０９の厚さは２０μｍから５０μｍ程度で形成している。これで図２２に示すように、第２の参考例に用いた本発明の配線基板が完成する。
他の参考例に用いた配線基板についても前述に示した製造方法の工程あるいは材料を一部削除することで作成できる。
【００６２】
【発明の効果】
以上説明したように、本発明によって、半導体チップを配線基板上に搭載し、ハンダボールを介して外部の配線基板と電気的に接続を行う半導体装置において、配線基板内に半導体チップおよび外部の配線基板との接続により発生する応力を緩和する緩和層を形成した配線基板を製造できる。
このことによって、半導体装置単体の信頼性および外部の配線基板を接続した際の接続信頼性を向上することができる。今後半導体チップの出力端子の増加に伴い、半導体装置の突起端子の体積が小さくなっても半導体装置の接続信頼性を損なうことはない。
【００６３】
また、配線基板の製造においては、既存の製造装置を使用することが可能なので、生産上有利である。
【図面の簡単な説明】
【図１】 本発明の第１の参考例である半導体装置を示す断面図である。
【図２】 本発明の第１の参考例における半導体チップを示す平面図である。
【図３】 本発明の第１の参考例における半導体チップを示す断面図である。
【図４】 本発明の第１の参考例における配線基板を示す平面図である。
【図５】 本発明の第１の参考例における配線基板を示す断面図である。
【図６】 本発明の第２の参考例である半導体装置を示す断面図である。
【図７】 本発明の第２の参考例における半導体チップを示す平面図である。
【図８】 本発明の第２の参考例における半導体チップを示す断面図である。
【図９】 本発明の第２の参考例における配線基板を示す平面図である。
【図１０】 本発明の第２の参考例における配線基板を示す断面図である。
【図１１】 本発明の第３の参考例である半導体装置を示す断面図である。
【図１２】 本発明の第３の参考例における半導体チップを示す平面図である。
【図１３】 本発明の第３の参考例における半導体チップを示す断面図である。
【図１４】 本発明の第３の参考例における配線基板を示す平面図である。
【図１５】 本発明の第３の参考例における配線基板を示す断面図である。
【図１６】 本発明の配線基板の製造方法における配線基板の基材を示す断面図である。
【図１７】 第２の参考例における本発明の配線基板の製造方法において緩和層を形成した状態を示す断面図である。
【図１８】 第２の参考例における本発明の配線基板の製造方法においてスルーホールを形成した状態を示す断面図である。
【図１９】 第２の参考例における本発明の配線基板の製造方法においてスルーホール内にエポキシ樹脂を充填した状態を示す断面図である。
【図２０】 第２の参考例における本発明の配線基板の製造方法において配線を形成した状態を示す断面図である。
【図２１】 第２の参考例における本発明の配線基板の製造方法において電極、パッド電極を形成した状態を示す断面図である。
【図２２】 第２の参考例における本発明の配線基板の製造方法においてハンダ層を形成した状態を示す断面図である。
【図２３】 従来技術における半導体装置を示す断面図である。
【図２４】 従来技術における半導体装置を示す断面図である。
【符号の説明】
１ 半導体チップ
２ 封止樹脂
７ 緩和層
１０ パッド電極
１１ ハンダボール
１６ 電極
１７ 配線基板
１９ 電極
３３ 突起電極
４８ ハンダ層[0001]
BACKGROUND OF THE INVENTION
  In the present invention, a semiconductor chip is mounted on a wiring board, the semiconductor chip and the wiring board are electrically connected, sealed with resin so as to cover the connection portion, and connected to the external wiring board on the wiring board. Semiconductor device provided with solder bump terminals for performingUsed forThe present invention relates to a method of manufacturing a wiring board on which a semiconductor chip is mounted.
[0002]
[Prior art]
  In recent years, with the increase in functionality of semiconductor devices, the number of external terminals of semiconductor devices tends to increase.JustA semiconductor device such as QFP tends to have an increased external size even if the terminal pitch of external terminals is reduced.
  On the other hand, a semiconductor device in which electrode terminals such as BGA or CSP can be arranged on the array can increase the number of external terminals and can have a smaller outer size than QFP. Examples of such a semiconductor device include a semiconductor device using a wiring board, for example, Japanese Patent Laid-Open No. 6-349973, and a semiconductor device not using a wiring board, for example, Japanese Patent Laid-Open No. 2-49460.
[0003]
A structure of a semiconductor device in which electrode terminals using a wiring board are formed on an array will be described with reference to FIG.
FIG. 23 is a cross-sectional view showing the semiconductor device disclosed in the above-mentioned Japanese Patent Laid-Open No. 6-349973.
[0004]
An alloy-based protruding electrode 122 is formed on the semiconductor chip 120. An electrode 123 formed so as to correspond to the arrangement of the protruding electrodes 122 of the semiconductor chip 120 is formed on the wiring substrate 126, and a pad electrode 124 is formed on the other surface so as to be connected to an external wiring substrate. .
The semiconductor chip 120 and the wiring substrate 126 are electrically connected by a protruding electrode 122 formed on the semiconductor chip 120 and sealed with a resin 121 so as to cover the semiconductor chip 120. An alloy-type protruding terminal 125 is formed on the pad electrode on the other surface of the wiring board 126.
[0005]
A structure of a semiconductor device in which electrode terminals not using a wiring board are formed on the array will be described with reference to FIG.
FIG. 24 is a cross-sectional view showing the semiconductor device disclosed in Japanese Patent Laid-Open No. 2-49460.
[0006]
An electrode 131 is formed on the main surface of the semiconductor chip 130, and this electrode functions as a part of the protruding terminal 135 for connection to an external wiring board. A passivation film is formed on the surface of the semiconductor chip 130 so that a part of the surface of the electrode 131 is exposed. A protruding terminal 135 for connection to an external wiring board is formed on a part of the surface of the electrode 131. A part of the protruding terminal 135 is exposed and sealed with a resin 132 so as to cover the entire semiconductor chip.
[0007]
[Problems to be solved by the invention]
However, when the output terminals of the semiconductor chip increase, the interval between the protruding terminals formed in an array has to be reduced, thereby reducing the volume of the protruding terminals.
As a result, in the semiconductor device as described above formed directly on the projecting terminal on the wiring board or the semiconductor device, when connected to the external wiring board, the interval between the external wiring board and the semiconductor device becomes narrower, and a temperature cycle test or the like. The stress applied to the connection portion generated by the input to the environmental test increases, and the thermal fatigue life of the semiconductor device decreases. The semiconductor device having a poor connection is broken at the base of the protruding terminal.
[0008]
Further, in the structure of the semiconductor device in which the semiconductor chip shown in FIG. 23 is mounted face-down on the wiring board, the electrical connection between the semiconductor chip and the wiring board is made by an alloy-type protruding electrode formed on the semiconductor chip. As described above, when the output terminals of the semiconductor chip are increased, the interval between the protruding electrodes must be reduced, and the volume of the protruding electrodes is reduced.
As a result, when the semiconductor chip is mounted on the wiring board, the distance between the semiconductor chip and the wiring board is narrowed, and the stress on the connected protruding electrode generated when the semiconductor device alone is put into an environmental test such as a temperature cycle test. As a result, the thermal fatigue life of the protruding electrode connected to the semiconductor chip decreases.
[0009]
    (Object of invention)
  The first object of the present invention is to solve the above-mentioned problems, and even if the volume of the projecting terminal is reduced as the output terminal of the semiconductor chip is increased, an external wiring board is provided.ContactA semiconductor device that does not impair connection reliability by relieving stress on the connection generated by the connectionCan be realized,It is to provide a method of manufacturing a wiring board on which a semiconductor chip is mounted.
[0010]
  Another object of the present invention is to provide a structure of a semiconductor device in which a semiconductor chip is mounted face-down on a wiring board, in addition to the above-described object, even if the volume of the protruding electrode decreases as the output terminal of the semiconductor chip increases. , Wiring boardContactA semiconductor device that does not impair connection reliability by relieving stress on the protruding electrodes generated by continuingUsed forAn object of the present invention is to provide a method for manufacturing a wiring board on which a semiconductor chip is mounted.
[0011]
[Means for Solving the Problems]
  To achieve the above-mentioned object, the present inventionHalf ofThe method described below is adopted as a method of manufacturing a wiring board on which a conductor chip is mounted.
[0012]
  Semiconductor of the present inventionThe manufacturing method of the wiring board on which the chip is mounted is BT resin glass cloth or epoxy resin.
The elastic modulus is 0.5 to 5 kgf / mm on both sides of the base substrate which is a glass resin glass cloth. 2 A step of obtaining a laminated molded plate by placing Cu foil on the outer sides of both the film-like relaxed layer and the relaxed layer, pressurizing and heating from both sides, and a through-hole penetrating the laminated molded plate A step of forming, a step of forming a wiring on the Cu foil including the through hole, and a pad for electrical connection between an electrode for electrical connection with an electrode of a semiconductor chip and an external wiring substrate And a step of forming an electrode.
[0013]
  Semiconductor of the present inventionA method of manufacturing a wiring board on which a chip is mounted is such that a Cu foil is disposed on one side of a base substrate such as a BT resin glass cloth or an epoxy resin glass cloth, and an elastic modulus is 0.5 to 5 kgf / mm 2 A step of providing a film-shaped relaxation layer and a Cu foil thereon, pressurizing and heating from both sides to obtain a laminated molded plate, and forming a through-hole penetrating the laminated molded plate; A step of forming a wiring on the Cu foil including the through hole, an electrode for electrical connection with the electrode of the semiconductor chip on the one surface, and an external wiring substrate on the other surface And a step of forming a pad electrode for connection.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, the present invention will be described with reference to the drawings.Half ofAn optimum embodiment of the method for manufacturing a wiring board on which a conductor chip is mounted will be described.
  First of all of the present inventionUsing a wiring boardThe structure of the semiconductor device will be described.
[0016]
    [FirstReference exampleDescription of structure of semiconductor device: FIGS. 1 to 5]
  The present inventionIt is a first reference example using the wiring board ofAn embodiment of a structure of a semiconductor device will be described with reference to FIGS. FIG.Half2 is a cross-sectional view of the conductor device, FIG. 2 is a plan view seen from the electrode 16 side of the semiconductor chip 1, FIG. 3 is a cross-sectional view of the semiconductor chip 1, and FIG. FIG. 5 is a cross-sectional view of the wiring board 17.
[0017]
The semiconductor chip 1 will be described with reference to FIGS. An electronic circuit is formed on the silicon substrate 14, and an electrode 16 is formed of Al or Au as an external terminal of the circuit. The material or surface treatment of the electrode 16 is selected in consideration of the material and bondability of the wire 8 when connecting the wiring substrate 17 with the wire 8. The portions other than the electrodes 16 of the semiconductor chip 1 are covered with an inorganic film such as a silicon nitride film or the above-described inorganic film and a protective film 15 made of an organic film such as polyimide, and are electrically insulated from the outside. .
[0018]
The wiring board 17 will be described with reference to FIGS. A die attach pattern 12 is formed in an area 18 where the back surface of the semiconductor chip 1 of the wiring substrate 17 is mounted, and also serves to dissipate heat generated from the power supply ground and the semiconductor chip 1 when the semiconductor chip 1 is mounted. ing.
A plurality of thermal via holes 21 are formed in the die attach pattern 12. The thermal via hole 21 serves to release the heat generated from the semiconductor chip 1 to the solder ball surface of the wiring board 17 and to electrically connect the die attach pattern 12 and the pad electrode 10 of the wiring board 17.
Further, the epoxy resin 9 is buried in the thermal via hole 21 and the other through holes 13, so that intrusion of moisture from the solder ball 11 mounting side of the wiring board 17 to the semiconductor chip 1 mounting side can be suppressed.
[0019]
The electrode 19 is an electrode for connecting the electrode 16 of the semiconductor chip 1 with the wire 8, and Au / Ni plating is performed on Cu. In consideration of the bondability of the wire 8, the Ni layer is formed with a thickness of 3 μm to 15 μm, and the Au layer is formed with a thickness of 0.3 μm to 1 μm.
[0020]
The side of the wiring substrate 17 on which the semiconductor chip 1 is mounted is covered with the solder resist 4 except for the die attach pattern 12 and the electrode 19 described above.
[0021]
The solder ball mounting side of the wiring board 17 has an elastic modulus of 0.5 to 5 kgf / mm on a base material 6 such as a BT resin glass cloth or an epoxy resin glass cloth.2 The relaxation layer 7 is formed, and the pad electrode 10 on which the wiring and the solder ball 11 are mounted is formed thereon.
[0022]
When the solder ball 11 is mounted on the pad electrode 10, the solder ball 11 is plated with Au / Ni on Cu so that the solder ball 11 is sufficiently wetted with respect to the pad electrode 10 and sufficient adhesion strength is secured. . Each of the metal layers is formed such that the Ni layer has a thickness of 3 μm to 5 μm and the Au layer has a thickness of 0.02 μm to 0.05 μm.
[0023]
The side of the wiring board 17 on which the solder balls 11 are mounted is covered with the solder resist 5 except for the pad electrode 10 described above.
[0024]
The semiconductor device will be described with reference to FIG. 1 including the semiconductor chip 1 and the wiring board 17 described above. The semiconductor chip 1 is fixed on the die attach pattern 12 on the wiring substrate 17 using an adhesive 3. Since the adhesive 3 contains Ag filler in the epoxy resin, the electrical connection to the power supply ground when the semiconductor chip 1 is mounted on the die attach pattern 12 and the heat generated from the semiconductor chip 1 are applied to the die attach pattern. 12 can dissipate heat.
[0025]
The electrical connection between each electrode 16 on the semiconductor chip 1 and the electrode 19 on the wiring board 17 is made by an Au wire 8. The wire diameter of Au is about 0.03 mm to 0.05 mm. The electrode 19 and the pad electrode 10 are electrically connected through a through hole.
[0026]
The semiconductor chip 1, the wires 8, and the electrodes 19 of the wiring board 17 are sealed with a sealing resin 2 for shielding and protection. A thermosetting epoxy resin is used for the sealing resin 2.
[0027]
Further, solder balls 11 are formed on the pad electrodes 10 of the wiring board 17. For the solder ball 11, solder having a composition of Sn: Pb in a ratio of 6: 4 is used.
The semiconductor device and an external wiring board are electrically connected via the solder ball 11.
[0028]
    [SecondReference exampleDescription of structure of semiconductor device: FIGS. 6 to 10]
  Next, the present inventionUsing the wiring boardSecondReference exampleThe structure of the semiconductor device will be described.
  The present inventionIt is the 2nd reference example using the wiring board ofAn embodiment of a structure of a semiconductor device will be described with reference to FIGS. FIG.Half7 is a cross-sectional view of the conductor device, FIG. 7 is a plan view of the semiconductor chip 30 viewed from the protruding electrode 33 side, FIG. 8 is a cross-sectional view of the semiconductor chip 30, and FIG. FIG. 10 is a cross-sectional view of the wiring board 39. FIG.
[0029]
The semiconductor chip 30 will be described with reference to FIGS.
An electronic circuit is formed on the silicon substrate 45, and an electrode 46 is formed of Al or the like as an external terminal of the circuit. A protruding electrode 33 of Cu or Au is formed on the electrode 46 for electrical connection with the electrode 47 of the wiring board 39.
[0030]
After the barrier metal layer 43 is formed by vapor deposition or sputtering in order to form the Cu or Au bump electrode 33 on the Al electrode 46, the Cu or Au bump electrode 33 is formed thereon by plating. . The barrier metal layer 43 is formed to prevent mutual metal diffusion of the electrode 46 and the protruding electrode 33.
[0031]
The portions other than the electrode 46 of the semiconductor chip 30 are covered with an inorganic film such as a silicon nitride film or the above-described inorganic film and a protective film 44 made of an organic film such as polyimide thereon, and are electrically insulated from the outside. Yes.
[0032]
The wiring board 39 will be described with reference to FIGS.
On both sides of the wiring board 39 on the semiconductor chip 30 mounting side and the solder ball 41 mounting side, the elastic modulus is 0.5 to 5 kgf / mm on the base material 37 such as BT resin glass cloth or epoxy resin glass cloth.2 The relaxation layer 35 is formed, and the pad electrode 52 on which the wiring, the electrode 47 and the solder ball 41 are mounted is formed thereon.
The elastic modulus of the metal used for the protruding electrode 33 is 130 × 10 Cu.Five kgf / mm2 And Au is 78 × 10Four kgf / mm2 And solder is 32 × 10Four kgf / mm2Therefore, the stress generated due to the difference in the linear expansion coefficient between the semiconductor chip 30 and the wiring board is concentrated on the root of the protruding electrode 33, so that the semiconductor chip 30 on the wiring board 39 is relaxed. A relaxation layer 35 is also formed on the mounting side.
[0033]
The electrodes 47 of the wiring board 39 are formed so as to correspond to the arrangement of the protruding electrodes 33 formed on the semiconductor chip 30. An epoxy resin 42 is buried in the through hole 40, so that moisture can be prevented from entering from the solder ball 41 mounting side of the wiring board 39 to the semiconductor chip 30 mounting side.
[0034]
The electrode 47 is provided with a solder layer 48 on Cu of the electrode 47 in order to electrically connect the protruding electrode 33 of the semiconductor chip 30. For the solder layer 48, solder having a composition of Sn: Pb in a ratio of 6: 4 is used.
The solder layer 48 is melted and connected to the protruding electrode 33 of the semiconductor chip 30. The solder layer has a thickness of about 200 μm to 500 μm.
[0035]
On the side of the wiring substrate 39 on which the semiconductor chip 30 is mounted, the portion other than the electrode 47 is covered with the solder resist 34.
[0036]
When the solder ball 41 is mounted, the pad electrode 52 on the side where the solder ball 41 is mounted has a solder ball 41 that is sufficiently wetted with respect to the pad electrode 52 and has sufficient adhesion strength. Ni plating is applied. The thickness of each metal layer is 3-5 μm for the Ni layer, and 0.02 μm-0.05 μm for the Au layer.
[0037]
The side of the wiring board 39 on which the solder balls 41 are mounted is covered with the solder resist 34 except for the pad electrodes 52 described above.
[0038]
The semiconductor device will be described with reference to FIG. 6 including the semiconductor chip 30 and the wiring substrate 39 described above. For the electrical connection between each protruding electrode 33 on the semiconductor chip 1 and the electrode 47 on the wiring substrate 39, the solder layer 48 formed on the electrode 47 is melted and the protruding electrode 33 and the electrode 47 are connected. The electrode 47 and the pad electrode 52 are electrically connected through a through hole.
[0039]
Between the semiconductor chip 30 and the wiring board 39, sealing is performed with a sealing resin 32 in order to improve the reliability of the connecting portion and protect the circuits formed on the semiconductor chip 30 and the wiring board 39. As the sealing resin 32, a thermosetting epoxy resin is used.
[0040]
Further, solder balls 41 are formed on the pad electrodes 52 of the wiring board 39. For the solder ball 41, solder having a composition of Sn: Pb in a ratio of 6: 4 is used.
The semiconductor device and an external wiring board are electrically connected via the solder ball 41.
[0041]
    [ThirdReference exampleDescription of structure of semiconductor device: FIGS. 11 to 15]
  Next, the present inventionUsing the wiring boardThirdReference exampleThe structure of the semiconductor device will be described.
  The third of the present inventionReference exampleThe structure will be described with reference to FIGS. FIG.Half12 is a cross-sectional view of the conductor device, FIG. 12 is a plan view of the semiconductor chip 70 as viewed from the protruding electrode 71 side, FIG. 13 is a cross-sectional view of the semiconductor chip 70, and FIG. FIG. 15 is a cross-sectional view of the wiring board 80. FIG.
[0042]
  The semiconductor chip 70 is illustrated.12And figure13And will be described.
  An electronic circuit is formed on the silicon substrate 84, and an electrode 86 is formed of Al or the like as an external terminal of the circuit. In order to make electrical connection with the electrode 87 of the wiring board 80 on the electrode 86, the protruding electrode 71 is formed of solder having a composition of Sn: Pb of 6: 4.
[0043]
After the barrier metal layer 85 is formed on the Al electrode 86 by vapor deposition or sputtering in order to form the solder bump electrode 71, the solder bump electrode 71 is formed thereon by plating.
The barrier metal layer 85 is formed to prevent mutual diffusion of the metal of the electrode 86 and the protruding electrode 71.
[0044]
The portion other than the electrode 86 of the semiconductor chip 70 is covered with an inorganic film such as a silicon nitride film or the above-described inorganic film and a protective film 73 made of an organic film such as polyimide, and is electrically insulated from the outside. .
[0045]
  For wiring board 8011And figure15And will be described.
  The elastic modulus is 0.5 to 5 kgf / mm on a base material 76 such as BT resin glass cloth or epoxy resin glass cloth on the solder ball 82 mounting side of the wiring board 80.2A relaxation layer 77 is formed, and a pad electrode 81 on which wiring and solder balls 82 are mounted is formed thereon.
[0046]
The electrodes 87 of the wiring board 80 are formed so as to correspond to the arrangement of the protruding electrodes 71 formed on the semiconductor chip 70. An epoxy resin 83 is buried in the through hole 79, and moisture can be prevented from entering from the solder ball 82 mounting side of the wiring substrate 80 to the semiconductor chip 70 mounting side.
[0047]
The electrode 87 is plated with Au / Ni on Cu in order to sufficiently wet the protruding electrode 71 formed of solder of the semiconductor chip 70 and to secure sufficient adhesion strength.
As for the thickness of each metal layer, the thickness of the Ni layer is 3 μm to 5 μm, and the thickness of the Au layer is 0.02 μm to 0.05 μm.
[0048]
On the side of the wiring substrate 80 on which the semiconductor chip 70 is mounted, a portion other than the electrode 87 is covered with a solder resist 74.
[0049]
When the solder ball 82 is mounted, the pad electrode 81 on the mounting side of the solder ball 82 has a solder ball 82 that is sufficiently wetted with respect to the pad electrode 81 and has sufficient adhesion strength. Ni plating is applied.
As for the thickness of each metal layer, the thickness of the Ni layer is 3 μm to 5 μm, and the thickness of the Au layer is 0.02 μm to 0.05 μm.
[0050]
The side of the wiring board 80 on which the solder balls 82 are mounted is covered with a solder resist 74 except for the pad electrode 81 described above.
[0051]
  The semiconductor device will be described with reference to FIG. 11 including the semiconductor chip 70 and the wiring substrate 80 described above.
  Each protruding electrode 71 on the semiconductor chip 70 and the solder on the wiring substrate 80 are melted, and the protruding electrode 71 and the electrode 87TheConnecting. Electrode 87 and pad electrode81Is electrically connected through a through hole.
[0052]
The semiconductor chip 70 and the wiring board 80 are sealed with a sealing resin 72 in order to improve the reliability of the connecting portion and protect the circuits formed on the semiconductor chip 70 and the wiring board 80.
A thermosetting epoxy resin is used for the sealing resin 72.
[0053]
Further, solder balls 82 are formed on the pad electrodes 81 of the wiring board 70. For the solder ball 82, solder having a composition of Sn: Pb in a ratio of 6: 4 is used.
The semiconductor device and an external wiring board are electrically connected via the solder ball 82.
[0054]
    [Of the present inventionWiring board manufacturing method: FIGS. 16 to 22]
  Next, the second aspect of the present invention described above is used.Reference exampleA method for manufacturing the wiring board used in the above will be described. 16 to 22 are cross-sectional views showing the manufacturing process of the wiring board of the present invention, which will be described below with reference to these drawings.
[0055]
FIG. 16 shows a base material 100 serving as a base of the wiring board. This base material 100 uses a BT resin glass cloth or an epoxy resin glass cloth having a thickness of about 0.2 to 0.6 mm.
Both surfaces of the base material 100 are subjected to a roughening process and a catalyst activation process in order to improve the adhesion of the relaxation layer 101 formed on the base material 100.
[0056]
A thickness of 18 μm which is subjected to a surface treatment to improve the adhesion between the relaxation layer 101 having a thickness of 30 μm to 50 μm and the relaxation layer 101 on the substrate 100 subjected to the roughening treatment and the catalyst activation treatment on both sides. The Cu foil 102 is placed and laminated and molded by applying pressure and temperature from both sides.
Thus, the double-sided board shown in FIG. 17 in which the relaxing layers 101 are formed on both sides of the base material 100 can be obtained.
[0057]
A plurality of through holes 103 are formed in the double-sided plate by drilling or laser processing. In order to perform Cu plating in the through hole 103, a catalyst activation process is performed and Cu plating is performed. As a result, a through hole 103 as shown in FIG. 18 can be formed.
[0058]
Next, the epoxy resin 104 is filled into the through hole 103 as shown in FIG. As a filling method of the epoxy resin 104, a liquid epoxy resin 104 is supplied onto the upper surface of the substrate by using a screen printing method, and coating into the through hole 103 by a squeegee is performed. After coating, the epoxy resin 104 is thermally cured, and the substrate surface is polished after curing. By this method, the epoxy resin 104 can be completely filled in the through hole 103.
[0059]
Next, in order to form a wiring, a photosensitive resin is applied to both surfaces of the substrate, and exposure and development are performed through a predetermined exposure mask, and an etching resist film is formed only in a portion necessary for the wiring. Thereafter, Cu is etched to remove unnecessary Cu layers, and further the etching resist is removed. As a result, wiring as shown in FIG. 20 can be formed.
[0060]
  Next, in order to form the electrode 106 and the pad electrode 107, solder resist is formed on both sides.108A photosensitive resin is applied, and exposure and development are performed through a predetermined mask to form a solder resist 108 so that only the electrode 106 and the pad electrode 107 are exposed.
  Thereafter, Au / Ni plating is performed on the electrode 106 and the pad electrode 107 using the solder resist 108 as a mask in order to ensure solder wettability and adhesion strength. Each metal layer has a Ni layer thickness of 3 μm to 5 μm, and an Au layer thickness of 0.02 μm to 0.05 μm. Thereby, an electrode and a pad electrode as shown in FIG. 21 can be formed.
[0061]
  Further, the electrode 106 is a protruding electrode of the semiconductor chip.And DenA solder layer 109 is provided on the electrode 106 for air connection. The solder layer 109 is formed using a screen printing method. Use a predetermined metal mask that is open only on the electrode 106, and solder paste on the maskTheBy supplying and squeezing, the solder paste passes only through the mask through the mask and the solder paste is applied to the electrode 106.ButCan supply.
  Thereafter, the solder layer 109 can be formed by passing the substrate at a temperature higher than the melting point of the solder. The solder layer 109 is made of solder having a composition ratio of Sn and Pb of 6: 4, and the thickness of the solder layer 109 is about 20 μm to 50 μm. Now, as shown in FIG.Reference exampleUsed forOf the present inventionThe wiring board is completed.
  otherUsed for reference exampleFor the wiring board, the process or material of the manufacturing method described above is the same.CuttingCan be created.
[0062]
【The invention's effect】
  As explained above, the present inventionByA semiconductor device in which a semiconductor chip is mounted on a wiring board and electrically connected to an external wiring board via a solder ballLeaveA relaxation layer is formed in the wiring board to relieve stress generated by the connection between the semiconductor chip and the external wiring board.Can be manufactured.
  As a result, the reliability of the semiconductor device alone and the external wiring boardTheConnection reliability when connected can be improved. As the output terminals of semiconductor chips increase in the future, the volume of protruding terminals of semiconductor devicesButGetting smallerAlsoThe connection reliability of the semiconductor device is not impaired.
[0063]
Moreover, in manufacturing a wiring board, an existing manufacturing apparatus can be used, which is advantageous in production.
[Brief description of the drawings]
FIG. 1 shows the first of the present invention.Reference exampleIt is sectional drawing which shows a semiconductor device.
FIG. 2 shows the first of the present inventionReference exampleIt is a top view which shows the semiconductor chip in.
FIG. 3 shows the first of the present invention.Reference exampleIt is sectional drawing which shows the semiconductor chip in.
FIG. 4 shows the first of the present inventionReference exampleIt is a top view which shows the wiring board in.
FIG. 5 shows the first of the present inventionReference exampleIt is sectional drawing which shows the wiring board in.
FIG. 6 shows the second of the present invention.Reference exampleIt is sectional drawing which shows a semiconductor device.
FIG. 7 shows the second of the present invention.Reference exampleIt is a top view which shows the semiconductor chip in.
FIG. 8 shows the second of the present invention.Reference exampleIt is sectional drawing which shows the semiconductor chip in.
FIG. 9 shows the second of the present invention.Reference exampleIt is a top view which shows the wiring board in.
FIG. 10 shows the second of the present invention.Reference exampleIt is sectional drawing which shows the wiring board in.
FIG. 11 shows a third embodiment of the present invention.Reference exampleIt is sectional drawing which shows a semiconductor device.
FIG. 12 shows the third of the present inventionReference exampleIt is a top view which shows the semiconductor chip in.
FIG. 13 shows the third of the present invention.Reference exampleIt is sectional drawing which shows the semiconductor chip in.
FIG. 14 shows a third embodiment of the present invention.Reference exampleIt is a top view which shows the wiring board in.
FIG. 15 shows the third of the present invention.Reference exampleIt is sectional drawing which shows the wiring board in.
FIG. 16 shows the present invention.Arrangement ofIn the manufacturing method of a wire boardWiring boardIt is sectional drawing which shows a base material.
FIG. 17Of the present invention in the second reference exampleFor wiring board manufacturing methodsLeaveIt is sectional drawing which shows the state in which the relaxation layer was formed.
FIG. 18Of the present invention in the second reference exampleFor wiring board manufacturing methodsLeaveIt is sectional drawing which shows the state in which the through hole was formed.
FIG. 19Of the present invention in the second reference exampleFor wiring board manufacturing methodsLeaveIt is sectional drawing which shows the state which filled the through-hole with the epoxy resin.
FIG. 20Of the present invention in the second reference exampleFor wiring board manufacturing methodsLeaveIt is sectional drawing which shows the state which formed wiring.
FIG. 21Of the present invention in the second reference exampleFor wiring board manufacturing methodsLeaveIt is sectional drawing which shows the state in which the electrode and the pad electrode were formed.
FIG. 22Of the present invention in the second reference exampleFor wiring board manufacturing methodsLeaveIt is sectional drawing which shows the state in which the solder layer was formed.
FIG. 23 is a cross-sectional view showing a semiconductor device in the prior art.
FIG. 24 is a cross-sectional view showing a semiconductor device in the prior art.
[Explanation of symbols]
  1 Semiconductor chip
  2 Sealing resin
  7 Relaxation layer
  10 Pad electrode
  11 Solder balls
  16 electrodes
  17 Wiring board
  19 electrodes
  33 Projection electrode
  48 Solder layer

Claims (2)

ＢＴレジンガラス布やエポキシ樹脂ガラス布であるベース基材の両面に弾性率が０．５〜５ｋｇｆ／ｍｍ２であるフィルム状の緩和層と更にそれら緩和層の両方の外側にＣｕ箔を配し、両側より加圧および加温して積層成形板を得る工程と、該積層成形板を貫通するスルーホールを形成する工程と、該スルーホールを含め前記Ｃｕ箔に配線を形成する工程と、半導体チップの電極との電気的接続を行うための電極と外部の配線基板との電気的接続を行うためのパッド電極を形成する工程とを有することを特徴とする半導体チップを搭載する配線基板の製造方法。A film-like relaxation layer having an elastic modulus of 0.5 to 5 kgf / mm 2 on both sides of a base substrate such as a BT resin glass cloth or an epoxy resin glass cloth, and a Cu foil is arranged outside both the relaxation layers. A step of obtaining a laminated molded plate by pressing and heating from both sides, a step of forming a through hole penetrating the laminated molded plate, a step of forming a wiring in the Cu foil including the through hole, and a semiconductor And a step of forming a pad electrode for electrical connection between the electrode for electrical connection with the electrode of the chip and an external wiring substrate. Method. ＢＴレジンガラス布やエポキシ樹脂ガラス布であるベース基材の、一方の面にＣｕ箔を配し、他方の面に弾性率が０．５〜５ｋｇｆ／ｍｍ２であるフィルム状の緩和層と更にその上にＣｕ箔とを配し、両側より加圧および加温して積層成形板を得る工程と、該積層成形板を貫通するスルーホールを形成する工程と、該スルーホールを含め前記Ｃｕ箔に配線を形成する工程と、前記一方の面に半導体チップの電極との電気的接続を行うための電極と前記他方の面に外部の配線基板との電気的接続を行うためのパッド電極を形成する工程とを有することを特徴とする半導体チップを搭載する配線基板の製造方法。A base material such as a BT resin glass cloth or an epoxy resin glass cloth is provided with a Cu-like foil on one side and a film-like relaxation layer having an elastic modulus of 0.5 to 5 kgf / mm 2 on the other side, and A Cu foil is disposed thereon, pressurized and heated from both sides to obtain a laminated molded plate, a step of forming a through hole penetrating the laminated molded plate, and the Cu foil including the through hole Forming a wiring on the surface, forming an electrode for electrical connection with the electrode of the semiconductor chip on the one surface and a pad electrode for electrical connection with an external wiring substrate on the other surface A method of manufacturing a wiring board on which a semiconductor chip is mounted.
JP12676297A 1997-05-16 1997-05-16 Manufacturing method of wiring board mounting semiconductor chip Expired - Fee Related JP3795628B2 (en)

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US20210076491A1 (en) * 2018-05-25 2021-03-11 Toppan Printing Co.,Ltd. Glass circuit board and method of manufacturing same

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US20020030257A1 (en) * 1999-06-18 2002-03-14 Joseph M. Brand Semiconductor device utiling an encapsulant for locking a semiconductor die to circuit substrate
KR100584965B1 (en) 2003-02-24 2006-05-29 삼성전기주식회사 A package substrate, and its manufacturing method
JP2007019275A (en) * 2005-07-07 2007-01-25 Rohm Co Ltd Substrate, semiconductor device, and manufacturing method thereof
GB2444775B (en) * 2006-12-13 2011-06-08 Cambridge Silicon Radio Ltd Chip mounting
JP2015090891A (en) * 2013-11-05 2015-05-11 株式会社ザイキューブ Semiconductor device and manufacturing method of the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210076491A1 (en) * 2018-05-25 2021-03-11 Toppan Printing Co.,Ltd. Glass circuit board and method of manufacturing same
US11516911B2 (en) * 2018-05-25 2022-11-29 Toppan Printing Co., Ltd. Glass circuit board and stress relief layer

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