JPH07106503A - Semiconductor device package and semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a package for semiconductor device, which has a size close to chip size, by laminating three layers of a signal layer, a power supply layer and a grounding layer formed by metal foil through insulation sheets, with the grounding layer and the power supply layer connected to the outside with individual vias and common leads. CONSTITUTION:A signal layer 14, a grounding layer 16 and a power supply layer 18 are formed to predetermined pattens by applying etching process to metal foil. The signal layer 14 and grounding layer 16 are adhered by an insulation sheet 20, and also the grounding layer 16 and the power supply layer 18 are adhered with an insulation sheet 22. Also, a via 24 is formed from a through-hole in the insulation sheet 20 to the grounding layer 16, and also a via 26 is formed from a through-hole in the insulation sheets 20 and 22 to the power supply layer 18. In this way, the grounding layer 16 and the power supply layer 18 can be connected to the external portion by means of the vias 24 and 26 and common leads 30 and 32. Therefore, the number of leads 30 and 32 can be reduced and instead the signal layer 14 can be made denser accordingly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package and a semiconductor device.

[0002]

2. Description of the Related Art Various packages for mounting semiconductor chips have been developed. In these packages, as represented by a lead frame, a semiconductor chip is mounted on a stage part, and a lead part electrically connected to the semiconductor chip via a wire or the like is formed around the semiconductor chip. Is common.

[0003]

However, there is a tendency for semiconductor chips to become larger and larger in size these days, and if the lead portions are arranged around the semiconductor chips as described above, the entire semiconductor device becomes large and there is a demand for downsizing. Against. Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device package that can be made into a size close to a chip size and can be miniaturized. Another object of the present invention is to provide a semiconductor device having excellent electrical characteristics.

[0004]

The present invention has the following constitution in order to achieve the above object. That is, in the semiconductor device package according to the present invention, at least three layers of a signal layer, a power supply layer, and a ground layer, which are formed of metal foil, are laminated with an insulator sheet interposed therebetween, and the signal layer is formed on the insulator sheet. A plurality of inner leads wired to the inner leads and outer leads for external connection that are integrally connected to the inner leads. From the power supply layer and the ground layer, the insulation sheet is penetrated to the signal layer. Multiple power vias exposed at
It is characterized in that a grounding via is led out and a selected via of the vias is connected to a lead of the signal layer. It is preferable to wire the inner leads of the signal layer so that a plurality of semiconductor chips can be mounted. Furthermore, in the present invention, at least three layers of a signal layer, a power supply layer, and a ground layer are laminated with an insulating sheet interposed therebetween, and the signal layer is formed by processing a metal plate, and has a predetermined pattern on the insulating sheet. And a plurality of outer leads for external connection that are integrally connected to the inner leads, the power supply layer and the ground layer are formed of a metal foil, and the power supply layer and the contact layer are connected to each other. A plurality of power supply vias and grounding vias, which are exposed between the inner leads of the signal layer through the insulating sheet, are led out from the ground layer, and selected vias of the vias are leads of the signal layer. It is characterized by being connected to. In the semiconductor device according to the present invention, the semiconductor chip is such that the signal terminal, the power supply terminal, and the grounding terminal of the semiconductor chip are bumped on the inner lead of the signal layer of the semiconductor device package, the power supply via, and the grounding via. It is characterized by being connected and mounted via.

[0005]

According to the semiconductor device package of the present invention, its size can be made substantially the same as the size of the semiconductor chip to be mounted, so that the size can be reduced. Further, since the ground layer and the power supply layer can be connected to the outside by the respective vias and the common lead, the number of leads can be reduced, and the signal layer can be made dense accordingly, so that the number of pins can be increased. Further, according to the semiconductor device of the present invention, since the package has a multi-layer structure having a ground layer and a power supply layer having a large area separately from the signal layer, crosstalk can be suppressed as a strip line for the signal layer. Since the inductance of the power supply system is low, the power supply noise can be reduced and the high frequency characteristics are particularly excellent.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a cross-sectional explanatory view of a semiconductor device 10. Reference numeral 12 represents a package, 14 is a signal layer thereof, 16 is a ground layer, and 18 is a power supply layer. Signal layer 14,
The ground layer 16 and the power supply layer 18 are formed in a predetermined pattern by etching a metal foil such as a copper foil.
The signal layer 14 and the ground layer 16 are adhered by an insulating sheet 20 having heat resistance and adhesiveness. The ground layer 16 and the power supply layer 18 are also adhered by the same insulating sheet 22. The signal layer 14 is formed by etching a metal foil adhered on the insulator sheet 20, and the ground layer 16 and the power supply layer 18 are separated from each other by the insulator sheet 2.
It is formed by etching a metal foil attached to both surfaces of No. 2, and thereafter, both sheets of the insulating sheets 20 and 22 are overlapped and cured to be integrated. A through hole reaching the ground layer 16 is formed in the insulating sheet 20, and a conductive paste is filled in the through hole to form a via 24. The via 24 exposed on the insulator sheet 20 is connected to the land 25 formed on the insulator sheet 20. Further, a through hole reaching the power supply layer 18 is formed in the insulating sheets 20 and 22, and a conductive paste is filled in the through hole to form a via 26. The via 26 exposed on the insulator sheet 20 is formed by the insulator sheet 20.
It is connected to the land 27 formed above.

FIG. 2 is a plan view showing a wiring example of the signal layer 14 and the lands 25 and 27 formed on the insulating sheet 20. The signal layer 14 includes inner leads 14 a wired on the insulation sheet 20 and outer leads 14 b protruding outside the insulation sheet 20. The inner leads 14a are routed on the insulating sheet 20 according to the arrangement pattern of the signal terminals formed on the semiconductor chip 28 to be mounted. Further, the via 24 is provided according to the pattern of the ground terminal of the semiconductor chip 28,
The via 26 is provided according to the pattern of the power supply terminal of the semiconductor chip 28. As shown in FIG. 2, the selectively selected via 24 a of the vias 24 is formed of the insulating sheet 20.
The lead 30 formed on the upper side enables connection to the outside. Similarly, the via 2 selectively selected from the vias 26
As shown in FIG. 2, 6a can be connected to the outside by a lead 32 formed on the insulating sheet 20.

The package 10 formed as described above
In addition, the semiconductor chip 28 has inner leads 1 of the signal layer corresponding to the signal terminal, the power supply terminal, and the ground terminal, respectively.
4a, the vias 24 and 26 are aligned and connected via bumps 34 and mounted, and the semiconductor device 10 is completed.
An adhesive layer 36 is interposed between the semiconductor chip 28 and the insulator sheet 20 for insulation. The adhesive layer 36 may be an insulating layer such as a solder resist.
In the above embodiment, an insulating sheet (not shown) may be attached to the lower surface side of the power supply layer 18.

According to the package 10 of the above-described embodiment, the size thereof can be made substantially the same as the size of the semiconductor chip 28, so that the size can be reduced. Further, the ground layer 16 and the power supply layer 18 include the vias 24 and 26 and the common lead 30,
Since it can be connected to the outside by means of 32, the number of leads 30, 32 can be reduced, and the signal layer 14 can be made denser by that much, so that a large number of pins can be accommodated. Further, since the package 10 has a multi-layer structure having the ground layer 16 and the power supply layer 18 having a large area separately from the signal layer 14, the signal layer 14 can be suppressed as a strip line from crosstalk, and can be used for the power supply system. In particular, since the inductance is low, the power supply noise can be reduced, and the electrical characteristics are particularly excellent in high frequency characteristics. If the signal layer 14, the power supply layer 18, and the ground layer 16 are laminated in this order (not shown), by using an insulating sheet having a large dielectric constant between the power supply layer 18 and the ground layer 16, a so-called It has an electrical characteristic that a decoupling capacitor can be formed and power supply noise can be reduced.

The signal layer 14 can also be formed in multiple layers of two or more. The inner leads 14a may be wired so that a plurality of semiconductor chips can be mounted on the insulating sheet 20. Further, as shown by the broken line in FIG.
By covering the side surface of the package 10 and further the upper surface of the semiconductor chip 28 with the resin 38 and sealing with the resin 38, it is possible to prevent ingress of moisture and the like and ensure airtightness. In the above-described embodiment, an example of the type in which the outer leads 14b are directly mounted on the substrate is shown. However, as shown in FIG. 3, the thick outer leads 40 made of a metal plate are soldered to the outer leads 14b. Fix this outer lead 40
May be exposed to the outside, and the whole may be sealed with the sealing resin 38. By using the thick outer lead 40, deformation of the outer lead 40 can be prevented.

FIG. 4 shows another embodiment. The same members as those in the above embodiment are designated by the same reference numerals. 14 is a signal layer, 1
Reference numeral 6 is a ground layer, and 18 is a power supply layer, which are also formed by laminating insulating sheets 20 and 22. Ground layer 1
6. The power supply layer 18 is formed by etching a metal foil as in the above embodiment, while the signal layer 14 is formed by pressing or etching a normal lead frame, that is, a metal plate. The same land 2 as described above is formed by etching a metal foil on the insulator sheet 20.
5, 27 are formed in a predetermined arrangement (FIG. 5). Vias 24 connected to the ground layer 16 are connected to the land 25,
Vias 26 connected to the power supply layer 18 are connected to the lands 27. Bumps 34 are formed on the lands 25 and 27.

The signal layer 14 made of a lead frame formed of a metal plate as described above is laminated on the insulator sheet 20, and some of the vias 24 have bumps 34 on the grounding lead 30, as shown in FIG. Connected through via 2
Some of 6 are connected to the power supply lead 32 via bumps 34. As shown in the figure, the vias 24 and 26 are arranged so as to be led out to the space portion between the inner leads 14a. Also, the inner lead 1 of the signal layer 14
The bumps 34 are also formed on the tip of the 4a so as to have the same height as the bumps 34 on the lands 25 and 27.
The semiconductor chip 36 is connected to the corresponding terminals via the bumps 34 in the same manner as described above, and then sealed with the sealing resin 38 to complete the semiconductor device. Also in the present embodiment, the same operational effects as described above are exhibited.

Although the present invention has been variously described with reference to the preferred embodiments, the present invention is not limited to these embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.

[0014]

According to the semiconductor device package of the present invention, the size thereof can be made substantially the same as the size of the semiconductor chip to be mounted, so that the size can be reduced. Further, since the ground layer and the power supply layer can be connected to the outside by the respective vias and the common lead, the number of leads can be reduced, and the signal layer can be made dense accordingly, so that the number of pins can be increased. Also,
According to the semiconductor device of the present invention, since the package has a multi-layered structure having a ground layer and a power supply layer having a large area separately from the signal layer, crosstalk can be suppressed as a strip line for the signal layer, and the power supply can be suppressed. Since the system has a low inductance, power supply noise can be reduced, and the system has electrical characteristics that are particularly excellent in high frequency characteristics.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a semiconductor device.

FIG. 2 shows a plan view of the package.

FIG. 3 is a sectional view showing another embodiment.

FIG. 4 is a sectional view showing still another embodiment.

5 is a partial cross-sectional view showing a via structure connected to a ground layer and a power supply layer of the embodiment shown in FIG.

FIG. 6 is a partial plan view showing a lead-out portion of a via of the embodiment shown in FIG.

[Explanation of symbols]

 10 semiconductor device 12 package 14 signal layer 16 ground layer 18 power supply layer 20, 22 insulating sheet 24, 26 via 25, 27 land 28 semiconductor chip 30, 32 lead 34 bump 38 sealing resin

Claims (4)

[Claims] 1. At least three layers of a signal layer, a power supply layer, and a ground layer, which are formed of a metal foil, are laminated with an insulating sheet interposed therebetween, and the signal layer has a plurality of wiring lines formed on the insulating sheet. A plurality of power sources having inner leads and outer leads for external connection that are integrally connected to the inner leads, and exposed from the power supply layer and the ground layer to the signal layer through the insulating sheet. A semiconductor device package, characterized in that a power via and a ground via are led out, and a selected via of the vias is connected to a lead of the signal layer. 2. The semiconductor device package according to claim 1, wherein the inner leads of the signal layer are wired so that a plurality of semiconductor chips can be mounted. 3. At least a signal layer, a power layer, and a ground layer
Layers are laminated via an insulating sheet, and the signal layer is formed by processing a metal plate, and a plurality of inner leads wired in a predetermined pattern on the insulating sheet, and integrated with the inner leads. An outer lead for external connection to be connected to, the power supply layer and the ground layer is formed of a metal foil, from the power supply layer and the ground layer, through the insulator sheet of the signal layer A semiconductor device package, wherein a plurality of power supply vias and grounding vias exposed between inner leads are led out, and selected vias of the vias are connected to leads of the signal layer. 4. The inner lead of the signal layer of the semiconductor device package according to claim 1, 2 or 3, a power supply via,
A semiconductor device in which a signal terminal, a power supply terminal, and a grounding terminal of a semiconductor chip are connected to a grounding via via bumps, respectively.