JPS61225827A - Mounting structure of semiconductor element - Google Patents

Mounting structure of semiconductor element

Info

Publication number
JPS61225827A
JPS61225827A JP60067590A JP6759085A JPS61225827A JP S61225827 A JPS61225827 A JP S61225827A JP 60067590 A JP60067590 A JP 60067590A JP 6759085 A JP6759085 A JP 6759085A JP S61225827 A JPS61225827 A JP S61225827A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor elements
semiconductor
wiring board
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60067590A
Other languages
Japanese (ja)
Inventor
Osamu Motosawa
本沢　修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60067590A priority Critical patent/JPS61225827A/en
Publication of JPS61225827A publication Critical patent/JPS61225827A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize high density mounting of semiconductor elements by a method wherein the semiconductor elements are arranged and joined on both sides of a wiring board in such a manner that the semiconductor elements overlap upon each other at least partially in the cross section. CONSTITUTION:A semiconductor element 1 is fixed in the recessed part of a wiring board 8 with fixing adhesive and, after wire bonding, molding 2 is performed. Then another semiconductor element 1 is joined with the wiring board 8 in a face-down manner. This arrangement and junction are made in such a manner that the two semiconductor elements overlap upon each other at least partially in the cross section. As a result, a large number of semiconductor elements can be mounted without increasing the surface area of the wiring board.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子の回路基板への取り付は構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure for mounting a semiconductor element to a circuit board.

〔発明の概要〕[Summary of the invention]

本発明は半導体素子の回路基板への取り付は方法に関し
、回路基材を介在し、該回路基材両面に半導体装置し、
且つ該半導体素子の一部分でも断面的に重なる様、配置
接合することにより、高密度実装化に寄与するものであ
る。The present invention relates to a method for attaching a semiconductor element to a circuit board, in which a circuit board is interposed, a semiconductor device is mounted on both sides of the circuit board, and
Further, by arranging and bonding the semiconductor elements such that even a portion of the semiconductor elements overlap in cross section, it contributes to high-density packaging.

〔従来の技術〕[Conventional technology]

従来の半導体素子実装構造は第３図である。 A conventional semiconductor element mounting structure is shown in FIG.

第５図に於いて、１は半導体素子、３はボンディングワ
イヤー、７は工ａ固定用接着剤、２はモールド剤である
。８は回路基材・４は８の回路基材に接合している配線
導体、５は電子機器用部品でアリ、チップ抵抗、チップ
コンデンサー等はその代表的な部品である。また５の電
子機器用部品は６０半田付等により配線導体に接合され
ている。In FIG. 5, 1 is a semiconductor element, 3 is a bonding wire, 7 is an adhesive for fixing the workpiece a, and 2 is a molding agent. 8 is a circuit base material, 4 is a wiring conductor bonded to the circuit base material 8, and 5 is a component for electronic equipment, typical of which are dovetails, chip resistors, chip capacitors, etc. Further, the electronic device component 5 is joined to the wiring conductor by 60 soldering or the like.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体素子の実装構造は、回路基材を介在し、
該回路基材両面に半導体素子を配置し、且つ半導体素子
の一部分でもが断面的に重なるよう配置、接合すること
を特徴とする。The semiconductor element mounting structure of the present invention includes a circuit substrate,
It is characterized in that semiconductor elements are arranged on both sides of the circuit substrate, and the semiconductor elements are arranged and bonded so that even some of the semiconductor elements overlap in cross section.

〔実施例〕〔Example〕

以下、本発明について実施例に基づいて詳細に説明する
。第１図は本発明の半導体素子が断面的にほぼ重なり合
う場合の半導体素子実装断面図である。１は半導体素子
、２はモールド剤、５はボンディングワイヤー、７はＩ
Ｃ固定用接着剤、８は回路基材、４は８の回路基材に接
合している配線導体、５は抵抗コンデンサ等の電子機器
用部品であり、回路基板に面実装されている０６は半田
付である。また９は４の配線導体より突出している部分
又は１の半導体素子より突出している部分を示す。製造
方法としては半導体素子をワイヤーボンディング後モー
ルドを行う。その後他方の半導体素子を７エースダウン
法によ゛り回路基板に接合する。このように行えば回路
基板平面サイズを大きくすることなく、半導体の高密度
実装が可能となる。Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a cross-sectional view of semiconductor element mounting in the case where the semiconductor elements of the present invention substantially overlap in cross section. 1 is a semiconductor element, 2 is a molding agent, 5 is a bonding wire, 7 is I
C fixing adhesive, 8 is a circuit base material, 4 is a wiring conductor bonded to the circuit base material 8, 5 is a component for electronic equipment such as a resistor capacitor, and 06 is surface mounted on the circuit board. It is soldered. Further, 9 indicates a portion protruding from the wiring conductor 4 or a portion protruding from the semiconductor element 1. As a manufacturing method, the semiconductor element is wire-bonded and then molded. Thereafter, the other semiconductor element is bonded to the circuit board by the 7 ace down method. By doing so, high-density packaging of semiconductors becomes possible without increasing the planar size of the circuit board.

また第２図は本発明による工Ｏ実装構造の他の例である
。１は半導体素子、２はモールド剤１３はボンディング
ワイヤー、４は８０回路基材に接合している配線導体で
ある、１０は半田バンプ又は金バンブ等である。１１は
ＴＡＢ方式の場合のリードパターンであり、１２の半田
又は溶着等により固定される０製造工程としては半導体
素子をワイヤーボンディング後、該半導体裏面方向に回
路基材を介在しＴＡＢ方式又はフィリップチップ方式等
より実装される半導体素子を接合する方法もありその効
果は高密度実装に効果を大にするＯ尚ここに挙げた実施
例はあくまでも一実施例にすぎないものである。Further, FIG. 2 shows another example of the O mounting structure according to the present invention. 1 is a semiconductor element, 2 is a molding agent 13 is a bonding wire, 4 is a wiring conductor bonded to the 80 circuit substrate, and 10 is a solder bump, a gold bump, or the like. 11 is a lead pattern in the case of TAB method, and it is fixed by soldering or welding etc. in 12.The manufacturing process is after wire bonding the semiconductor element, and then inserting a circuit board toward the back side of the semiconductor to form the TAB method or Philips chip. There is also a method of bonding semiconductor elements that are mounted by various methods, and the effect thereof is great for high-density mounting.The embodiment described here is merely one embodiment.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、回路基板平面サイズ
を大きくすることなく、沢山の半導体素子を登載可能と
なり、高密度実装に対応できる効果を有する。As described above, according to the present invention, it is possible to mount a large number of semiconductor elements without increasing the planar size of the circuit board, and it has the effect of being able to handle high-density packaging.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例の半導体素子（ＩＣ）実装断面
図であり、第２図は本発明の他の実施例の半導体素子（
工Ｃ）実装断面図である０まだ第３図は従来のワイヤー
ボンディング方式による半導体素子（工ａ）実装断面図
である。 １・・・半導体素子（ＩＣ等） ２・・・モールド剤 ６・・・ボンディングワイヤー ４・・・回路基材に接合している配線導体５・・・電子
機器用部品 ６・・・半田付部 ７・・・工Ｃ固定用接着剤 ８・・・回路基材 ９・・・配線導体より突出している部分又は半導体素子
より突出している部分 １０・・・半田バンプ又は金バンプ等 １１・・・ＴＡＢ方式の場合のリードパターン１２・・
・半田又は溶着等 才２ＮFIG. 1 is a sectional view of a semiconductor device (IC) packaged according to an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device (IC) according to another embodiment of the present invention.
Fig. 3 is a sectional view of a semiconductor element (Step A) mounted by the conventional wire bonding method. 1... Semiconductor element (IC, etc.) 2... Molding agent 6... Bonding wire 4... Wiring conductor bonded to circuit base material 5... Parts for electronic equipment 6... Soldering Part 7...Adhesive for fixing work C 8...Circuit base material 9...Part protruding from the wiring conductor or the part protruding from the semiconductor element 10...Solder bumps, gold bumps, etc. 11...・Lead pattern 12 for TAB method...
・Soldering or welding 2N

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の実装構造に於いて回路基材を介在し、該回
路基材両面に、半導体素子を配置し、且つ該半導体素子
の一部分でも断面的に重なる様配置、接合することを特
徴とする半導体素子の実装構造。A semiconductor characterized in that a circuit substrate is interposed in the mounting structure of a semiconductor element, semiconductor elements are arranged on both sides of the circuit substrate, and the semiconductor elements are arranged and bonded so that even a portion of the semiconductor elements overlap in cross section. Mounting structure of the element.
JP60067590A 1985-03-29 1985-03-29 Mounting structure of semiconductor element Pending JPS61225827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60067590A JPS61225827A (en) 1985-03-29 1985-03-29 Mounting structure of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60067590A JPS61225827A (en) 1985-03-29 1985-03-29 Mounting structure of semiconductor element

Publications (1)

Publication Number Publication Date
JPS61225827A true JPS61225827A (en) 1986-10-07

Family

ID=13349279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60067590A Pending JPS61225827A (en) 1985-03-29 1985-03-29 Mounting structure of semiconductor element

Country Status (1)

Country Link
JP (1) JPS61225827A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995003683A1 (en) * 1993-07-19 1995-02-02 Oakleigh Systems, Inc. Space-saving memory module
US5523608A (en) * 1992-09-01 1996-06-04 Sharp Kabushiki Kaisha Solid state imaging device having a solid state image sensor and its peripheral IC mounted on one package
JP2016083009A (en) * 2014-10-23 2016-05-19 オリンパス株式会社 Mounting structure, imaging module, and endoscope apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523608A (en) * 1992-09-01 1996-06-04 Sharp Kabushiki Kaisha Solid state imaging device having a solid state image sensor and its peripheral IC mounted on one package
WO1995003683A1 (en) * 1993-07-19 1995-02-02 Oakleigh Systems, Inc. Space-saving memory module
US5412538A (en) * 1993-07-19 1995-05-02 Cordata, Inc. Space-saving memory module
JP2016083009A (en) * 2014-10-23 2016-05-19 オリンパス株式会社 Mounting structure, imaging module, and endoscope apparatus

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