JPH06283561A - Package of semiconductor device - Google Patents

Package of semiconductor device

Info

Publication number
JPH06283561A
JPH06283561A JP5091869A JP9186993A JPH06283561A JP H06283561 A JPH06283561 A JP H06283561A JP 5091869 A JP5091869 A JP 5091869A JP 9186993 A JP9186993 A JP 9186993A JP H06283561 A JPH06283561 A JP H06283561A
Authority
JP
Japan
Prior art keywords
holes
semiconductor
package
flip chip
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5091869A
Other languages
Japanese (ja)
Inventor
Takeshi Ikeda
毅 池田
Akira Okamoto
明 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP5091869A priority Critical patent/JPH06283561A/en
Publication of JPH06283561A publication Critical patent/JPH06283561A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a package of semiconductor device capable of being manufactured at extremely low cost. CONSTITUTION:Linearly arrayed through holes 11 and wiring patterns 12 concentrated from respective through holes 11 on the position for mounting a semiconductor flip chip 2 are formed on a printed-wiring substrate 1 so as to junction respective end parts 13 of the concentrated wiring patterns 12 with the terminals of the semiconductor flip chip 2 through the intermediary of a bump 21. Besides, after coating the semiconductor chip 2 with a synthetic resin 14, the printed- wiring substrate 1 is cut off as if dividing itself along almost central line of the linearly arrayed respective through holes 11 to turn the through holes 10 of the cut-off respective halves into terminals. Furthermore, respective end parts 13 of the wiring patterns 12 are connected to the terminals of the semiconductor flip chip 2 by wire-bonding step.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置のパッケ
ージに関し、特に、廉価に製造できるように構成したも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package, and more particularly to a semiconductor device package which can be manufactured at low cost.

【0002】[0002]

【従来の技術】半導体素子を封止するパッケージとし
て、リードフレームを使用したセラミック・パッケージ
や合成樹脂でモールドしたパッケージ、バンプを有する
半導体フリップ・チップをテープキャリアに接合したパ
ッケージなど各種のパッケージが従来より提案されてい
る。
2. Description of the Related Art As a package for sealing a semiconductor element, various packages such as a ceramic package using a lead frame, a package molded with a synthetic resin, a package in which a semiconductor flip chip having bumps is bonded to a tape carrier are conventionally available. More suggested.

【0003】[0003]

【発明が解決しようとする課題】しかし、このような従
来の半導体装置のパッケージにおいては、半導体チップ
のコストよりもパッケージに占めるコストの方が高くな
る場合が多く、廉価で大量生産に適したパッケージの出
現が望まれていた。
However, in such a conventional semiconductor device package, the cost of the semiconductor chip is often higher than the cost of the semiconductor chip, and the package is inexpensive and suitable for mass production. Was expected.

【0004】[0004]

【課題を解決するための手段】印刷配線基板に、線状に
配列された複数のスルーホール、および、半導体フリッ
プ・チップを載置する位置へ各スルーホールより集中す
る配線パターンを形成し、集中した配線パターンの各先
端部と半導体チップの端子を接続し、半導体チップを合
成樹脂でコーテイングしたのち、線状に配列された各ス
ルーホールのほぼ中心に沿って分割するように印刷配線
基板を切断し、分割された各スルーホールを端子とす
る。
SOLUTION: A printed wiring board is formed with a plurality of linearly arranged through holes and a wiring pattern concentrated from the through holes at a position where a semiconductor flip chip is mounted, Connect each tip of the wiring pattern to the terminal of the semiconductor chip, coat the semiconductor chip with synthetic resin, and cut the printed wiring board so that it is divided along almost the center of each through hole arranged linearly. The divided through holes are used as terminals.

【0005】[0005]

【実施例】この発明の半導体装置のパッケージは、図6
の側面図に示すように、主として半導体チップの表面
に、電極となる接続部をハンダなどで盛り上がらせて形
成したバンプ21を有する半導体フリップ・チップ2の封
止に適している。次に、この発明のパッケージを製造工
程順に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device package according to the present invention is shown in FIG.
As shown in the side view of FIG. 1, it is mainly suitable for sealing the semiconductor flip chip 2 having the bumps 21 formed on the surface of the semiconductor chip by swelling the connection parts to be electrodes with solder or the like. Next, the package of the present invention will be described in the order of manufacturing steps.

【0006】(第1実施例)図1の平面図および図2
(a)の断面図に示すように、印刷配線基板1に、方形の
平面15を囲むように複数のスルーホール11を設け、これ
らの各スルーホール11より平面15の中央に向かって配線
パターン12を形成し、これら中央に集中した配線パター
ン12の各端部13は、半導体フリップ・チップ2のバンプ
21と対応するように位置付けられているものを用意す
る。
(First Embodiment) A plan view of FIG. 1 and FIG.
As shown in the sectional view of (a), the printed wiring board 1 is provided with a plurality of through holes 11 so as to surround a rectangular plane 15, and the wiring pattern 12 is formed from each of these through holes 11 toward the center of the plane 15. And the end portions 13 of the wiring pattern 12 concentrated in the center are bumps of the semiconductor flip chip 2.
Prepare the one positioned so as to correspond to 21.

【0007】このような複数のスルーホール11および配
線パターン12よりなり、点線で区切られた複数の基本パ
ターンを印刷配線基板1の縦横方向に平面状に繰り返し
形成する。
A plurality of basic patterns composed of such a plurality of through holes 11 and wiring patterns 12 and separated by dotted lines are repeatedly formed in a plane shape in the vertical and horizontal directions of the printed wiring board 1.

【0008】そして、図2(b)の断面図に示すように、
各基本パターンの配線パターン12が集中した中央部に、
半導体フリップ・チップ2を反転させて載置する。この
とき、配線パターン12の各端部13に半導体フリップ・チ
ップ2のバンプ21を位置合わせして載置し、ハンダ付け
して接続する。
Then, as shown in the sectional view of FIG.
In the central part where the wiring patterns 12 of each basic pattern are concentrated,
The semiconductor flip chip 2 is inverted and placed. At this time, the bumps 21 of the semiconductor flip chip 2 are aligned and placed on each end portion 13 of the wiring pattern 12, and soldered and connected.

【0009】次に、図2(c)の断面図に示すように、印
刷配線基板1の各スルーホール11の部分をマスクして樹
脂の流入を防止したのち、半導体フリップ・チップ2を
含む全表面を覆うように合成樹脂14をコーテイングする
コーテイングされた合成樹脂14が硬化してから、第1図
の点線で示すスルーホール11のほぼ中心に沿って切断す
ることにより、図2(d)の断面図および図3の斜視図に
示すように、切断された各半分のスルーホール10が、そ
れぞれ端子となるパッケージが形成される。
Next, as shown in the sectional view of FIG. 2 (c), after masking the through holes 11 of the printed wiring board 1 to prevent the resin from flowing in, the entire semiconductor flip chip 2 including The synthetic resin 14 is coated so as to cover the surface. After the coated synthetic resin 14 is cured, the synthetic resin 14 is cut substantially along the center of the through hole 11 shown by the dotted line in FIG. As shown in the cross-sectional view and the perspective view of FIG. 3, each of the cut through holes 10 is a terminal package.

【0010】(第2実施例)載置する半導体チップに比
して印刷配線基板が大きい場合には、印刷配線基板の全
表面を覆うように合成樹脂でコーテイングする必要はな
い。その場合には、図4(a)に示すように、各基本パタ
ーンの配線パターン12が集中した中央部にレジストを塗
布したのち、スルーホール11および残余の配線パターン
12にハンダ・メッキを施し、レジストを剥離した印刷配
線基板1を作成する。なお、ハンダ・メッキを必要とし
ない場合には、この工程は省略できる。
(Second Embodiment) When the printed wiring board is larger than the semiconductor chip to be mounted, it is not necessary to coat it with a synthetic resin so as to cover the entire surface of the printed wiring board. In that case, as shown in FIG. 4A, after the resist is applied to the central portion where the wiring patterns 12 of each basic pattern are concentrated, the through holes 11 and the remaining wiring patterns are formed.
Solder plating is applied to 12 and the printed wiring board 1 with the resist removed is prepared. If solder plating is not required, this step can be omitted.

【0011】そして、図4(b)の断面図に示すように、
印刷配線基板1の配線パターン12が集中した中央部に、
半導体フリップ・チップ2を載置し、半導体フリップ・
チップ2の各バンプ21と配線パターン12の各端部13を接
続する。
Then, as shown in the sectional view of FIG.
In the central part where the wiring patterns 12 of the printed wiring board 1 are concentrated,
Place the semiconductor flip chip 2 and
Each bump 21 of the chip 2 and each end 13 of the wiring pattern 12 are connected.

【0012】次に、図4(c)の断面図に示すように、少
なくとも半導体フリップ・チップ2を含む表面を覆うよ
うに、合成樹脂14をコーテイングして硬化させたのち、
スルーホール11のほぼ中心に沿って切断することによ
り、図4(d)に示すように、切断された各半分のスルー
ホール10が、それぞれ端子となるパッケージが形成され
る。
Next, as shown in the sectional view of FIG. 4C, a synthetic resin 14 is coated and cured so as to cover at least the surface including the semiconductor flip chip 2, and
By cutting along substantially the center of the through hole 11, as shown in FIG. 4D, a package is formed in which each of the cut through holes 10 serves as a terminal.

【0013】(第3実施例)以上で説明した各実施例に
おいては、半導体フリップ・チップ2を載置する方形の
平面15を囲むように複数のスルーホール11を設けている
が、スルーホール11の配列は、このような方形に限るこ
となく、線形に配列してデュアル・インライン・パッケ
ージ(DIP)またはシングル・インライン・パッケー
ジ(SIP)のように、側面に半分のスルーホールより
なる端子を設けてもよいのである。
(Third Embodiment) In each of the embodiments described above, a plurality of through holes 11 are provided so as to surround a rectangular plane 15 on which the semiconductor flip chip 2 is mounted. The arrangement is not limited to such a square, and the terminals are formed by arranging linearly and forming a half-through hole on the side surface like a dual in-line package (DIP) or a single in-line package (SIP). May be.

【0014】なお、バンプを設けていない半導体チップ
を封止する場合には、半導体チップの端子と配線パター
ンの各先端部との接続をワイヤ・ボンディングにより行
なえばよいのである。
When a semiconductor chip having no bumps is sealed, the terminals of the semiconductor chip and each tip of the wiring pattern may be connected by wire bonding.

【0015】また、この発明のパッケージは、半導体チ
ップの封止に限ることなく、セラミック、ガラスなどの
基板に形成された小さい電子回路素子の封止など、各種
の電子部品の封止に適用することができる。
The package of the present invention is not limited to the sealing of semiconductor chips, but is also applicable to the sealing of various electronic components such as the sealing of small electronic circuit elements formed on a substrate such as ceramic or glass. be able to.

【0016】以上で説明した各実施例により封止された
半導体装置または類似装置は、表面実装に適している。
すなわち、図5の断面図に示すように、実装すべき印刷
配線基板3の配線パターン31に合わせて接着剤4で仮止
めしたのち、半分のスルーホール10と配線パターン31と
をハンダ5により接続して固定する。
The semiconductor device or similar device sealed by each of the embodiments described above is suitable for surface mounting.
That is, as shown in the cross-sectional view of FIG. 5, the wiring pattern 31 of the printed wiring board 3 to be mounted is temporarily fixed with the adhesive 4 and then the half through hole 10 and the wiring pattern 31 are connected by the solder 5. And fix it.

【0017】[0017]

【発明の効果】以上の実施例に基づく説明から明らかな
ように、この発明の半導体装置のパッケージによると、
高価な設備や材料を要することなく、極めて廉価に製造
することができる。
As is clear from the description based on the above embodiments, according to the semiconductor device package of the present invention,
It can be manufactured at extremely low cost without requiring expensive equipment and materials.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の半導体装置のパッケージにおいて使
用する印刷配線基板の配線パターンの一例を示す平面
図、
FIG. 1 is a plan view showing an example of a wiring pattern of a printed wiring board used in a package of a semiconductor device of the present invention,

【図2】この発明の一実施例を製造工程順に示す断面
図、
FIG. 2 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps,

【図3】図2の実施例によってパッケージされた半導体
装置を示す斜視図、
3 is a perspective view showing a semiconductor device packaged according to the embodiment of FIG.

【図4】この発明の他の実施例を製造工程順に示す断面
図、
FIG. 4 is a sectional view showing another embodiment of the present invention in the order of manufacturing steps,

【図5】図2の実施例によってパッケージされた半導体
装置を表面実装した状態を示す断面図、
5 is a sectional view showing a state in which the semiconductor device packaged according to the embodiment of FIG. 2 is surface-mounted;

【図6】この発明によってパッケージされる半導体フリ
ップ・チップを示す側面図である。
FIG. 6 is a side view showing a semiconductor flip chip packaged according to the present invention.

【符号の説明】[Explanation of symbols]

1 印刷配線基板 10 切断された半分のスルーホール(端子) 11 スルーホール 12 配線パターン 13 配線パターンの端部 14 コーテイングされた合成樹脂 15 半導体フリップ・チップを囲む平面 2 半導体フリップ・チップ 21 バンプ 3 実装する印刷配線基板 4 接着剤 5 ハンダ 1 Printed Wiring Board 10 Cut Half Hole (Terminal) 11 Through Hole 12 Wiring Pattern 13 End of Wiring Pattern 14 Coated Synthetic Resin 15 Plane Surrounding Semiconductor Flip Chip 2 Semiconductor Flip Chip 21 Bump 3 Mounting Printed wiring board 4 adhesive 5 solder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 印刷配線基板に、線状に配列された複数
のスルーホール、および、半導体チップを載置する位置
へ各スルーホールより集中する配線パターンを形成し、
集中した上記配線パターンの各先端部と上記半導体チッ
プの端子を接続し、上記半導体チップを合成樹脂でコー
テイングしたのち、線状に配列された上記各スルーホー
ルを分割するように上記印刷配線基板を切断し、分割さ
れた各スルーホールを端子とすることを特徴とする半導
体装置のパッケージ。
1. A printed wiring board is provided with a plurality of linearly arranged through holes, and a wiring pattern concentrated from the through holes to a position where a semiconductor chip is mounted,
After connecting the respective tips of the concentrated wiring pattern to the terminals of the semiconductor chip and coating the semiconductor chip with a synthetic resin, the printed wiring board is divided so as to divide the through holes arranged in a line. A package of a semiconductor device, wherein each through hole obtained by cutting and dividing is used as a terminal.
【請求項2】 半導体チップを含む印刷配線基板の全表
面を合成樹脂でコーテイングし、コーテイングされた合
成樹脂とともに各スルーホールを分割するように上記印
刷配線基板を切断することを特徴とする請求項1に記載
の半導体装置のパッケージ。
2. The printed wiring board including a semiconductor chip is coated on its entire surface with a synthetic resin, and the printed wiring board is cut so as to divide each through hole together with the coated synthetic resin. 1. The semiconductor device package according to 1.
JP5091869A 1993-03-29 1993-03-29 Package of semiconductor device Pending JPH06283561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5091869A JPH06283561A (en) 1993-03-29 1993-03-29 Package of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5091869A JPH06283561A (en) 1993-03-29 1993-03-29 Package of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06283561A true JPH06283561A (en) 1994-10-07

Family

ID=14038571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5091869A Pending JPH06283561A (en) 1993-03-29 1993-03-29 Package of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06283561A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715348A3 (en) * 1994-11-29 1998-07-15 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6459152B1 (en) * 1999-10-27 2002-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
JP2007173738A (en) * 2005-12-26 2007-07-05 Fuji Xerox Co Ltd Wiring board and flip-chip mounting structure
JP2010278480A (en) * 2010-09-14 2010-12-09 Rohm Co Ltd Semiconductor device
US8405227B2 (en) 2004-09-28 2013-03-26 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
JP2013191898A (en) * 2013-07-04 2013-09-26 Rohm Co Ltd Semiconductor device
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715348A3 (en) * 1994-11-29 1998-07-15 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6459152B1 (en) * 1999-10-27 2002-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
US7094630B2 (en) 1999-10-27 2006-08-22 Renesas Technology Corp. Method of fabricating semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
US10818628B2 (en) 2004-09-28 2020-10-27 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US8405227B2 (en) 2004-09-28 2013-03-26 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11355462B2 (en) 2004-09-28 2022-06-07 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US8754535B2 (en) 2004-09-28 2014-06-17 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9117774B2 (en) 2004-09-28 2015-08-25 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9721865B2 (en) 2004-09-28 2017-08-01 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9831204B2 (en) 2004-09-28 2017-11-28 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10522494B2 (en) 2004-09-28 2019-12-31 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
JP2007173738A (en) * 2005-12-26 2007-07-05 Fuji Xerox Co Ltd Wiring board and flip-chip mounting structure
JP2010278480A (en) * 2010-09-14 2010-12-09 Rohm Co Ltd Semiconductor device
JP2013191898A (en) * 2013-07-04 2013-09-26 Rohm Co Ltd Semiconductor device

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