KR200172710Y1 - Chip sized package - Google Patents

Chip sized package Download PDF

Info

Publication number
KR200172710Y1
KR200172710Y1 KR2019970016156U KR19970016156U KR200172710Y1 KR 200172710 Y1 KR200172710 Y1 KR 200172710Y1 KR 2019970016156 U KR2019970016156 U KR 2019970016156U KR 19970016156 U KR19970016156 U KR 19970016156U KR 200172710 Y1 KR200172710 Y1 KR 200172710Y1
Authority
KR
South Korea
Prior art keywords
package
chip
lead frame
semiconductor chip
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR2019970016156U
Other languages
Korean (ko)
Other versions
KR19990002582U (en
Inventor
홍성학
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR2019970016156U priority Critical patent/KR200172710Y1/en
Publication of KR19990002582U publication Critical patent/KR19990002582U/en
Application granted granted Critical
Publication of KR200172710Y1 publication Critical patent/KR200172710Y1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/465—Bumps or wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 고안은 칩 크기의 패키지를 개시한다. 개시된 본 고안의 칩 크기의 패키지는 도전성 범프가 형성된 다수개의 본딩 패드들이 구비되어 있는 반도체 칩과, 상기 칩의 본딩 패드에 형성된 도전성 범프에 의해 전기적으로 연결되어 칩의 크기로의 신호 전달 경로를 이루며, 직선의 형태이고, 그의 일부분에는 디프레스 공정에 의하여 형성된 돌출부를 갖는 리드 프레임과, 상기 반도체 칩과 이에 연결된 리드 프레임을 봉지하며, 상기 리드 프레임의 돌출부 표면이 그의 외부로 노출되도록 형성된 패키지 몸체로 이루어지며, 노출된 리드 프레임의 돌출부에 솔더 볼을 부착시키고, 이를 이용하여 기판에 실장하도록 된 것을 특징으로 한다.The present invention discloses a chip sized package. The disclosed chip size package is electrically connected by a semiconductor chip having a plurality of bonding pads having conductive bumps formed thereon, and conductive bumps formed on the bonding pads of the chip to form a signal transmission path to the size of the chip. A lead body having a protrusion formed by a depressing process, a portion of the lead frame and a lead frame connected to the semiconductor chip, the package body being configured to expose the protrusion surface of the lead frame to the outside thereof. The solder ball is attached to the protrusion of the exposed lead frame and is mounted on the substrate using the solder ball.

Description

칩 크기의 패키지Chip sized package

본 고안은 반도체 장치에 관한 것으로, 특히, 칩 크기의 패키지에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a chip sized package.

최근, 각종 전기, 전자 제품의 크기가 소형화되는 추세에 따라 한정된 크기의 기판에 보다 많은 수의 칩을 실장하으로써 소형이면서도 고용량을 달성하고자 하는 연구가 전개되고 있으며, 이에 따라, 기판 상에 실장되는 반도체 패키지의 크기 및 두께가 점차 감소되고 있는 실정이다.Recently, as the size of various electric and electronic products is miniaturized, researches for achieving a small size and high capacity by mounting a larger number of chips on a limited size substrate have been developed. The size and thickness of semiconductor packages are gradually decreasing.

그 한 예로서, 제1도는 반도체 패키지의 경, 박, 단, 소화를 이룬 엘오씨(LOC)구조의 칩 크기의 패키지(CSP : Chip Size Package)를 도시한 도면으로서, 도시된 바와 같이, 반도체 칩(1)의 액티브면에는 이 칩(1)의 외부로의 신호 전달 경로를 이루는 다수개의 리드(2)들이 록(LOC) 테이프(3)에 의해 부착되고 이러한 리드(2)들은 상기 반도체 칩(1)의 액티브면에 구비된 다수개의 본딩 패드들(1a)과 금속 와이어(4)에 의해 전기적으로 접속된다. 또한, 반도체 칩(1) 및 이에 금속 와이어에 의해 전기적으로 연결된 리드들(2)은 이들을 보호하기 위한 실링 레진(5)에 의해 감싸져 있다.As an example, FIG. 1 is a diagram illustrating a chip size package (CSP) having a light, thin, short, and digestible LOC structure of a semiconductor package. On the active side of the chip 1 a plurality of leads 2 forming a signal transmission path to the outside of the chip 1 are attached by a lock (LOC) tape 3 and these leads 2 are connected to the semiconductor chip. It is electrically connected by the metal wire 4 and the plurality of bonding pads 1a provided on the active surface of (1). In addition, the semiconductor chip 1 and the leads 2 electrically connected thereto by a metal wire are surrounded by a sealing resin 5 for protecting them.

한편, 상기와 같은 구조에서 레진(5)에 의해 성형되는 패키지 몸체의 바닥면 양측으로 리드(2)의 일부가 노출되어 있으며, 이와 같이 패키지로부터 그의 외부로 노출된 리드(2)를 이용하여 기판에 실장하도록 되어 있다.On the other hand, a part of the lid 2 is exposed to both sides of the bottom surface of the package body formed by the resin 5 in the structure as described above, the substrate using the lid 2 exposed to the outside from the package in this way It is intended to be mounted on.

상기에서 칩 크기의 패키지는 통상적으로 알려지고 있는 반도체 패키지, 즉, 칩의 전체면을 수지로 몰딩하여 구성하는 반도체 패키지에 비하여 몰딩 두께 및 크기를 작게 할 수 있기 때문에 패키지의 경박단소형화를 이룰 수 있으며, 이에 따라, 실장 효율을 향상수 있고, 최근의 전기, 전자 제품의 소형화 추세에 유리하게 대응할 수 있는 장점을 가진다.Since the chip size package can reduce the thickness and size of the package compared to a semiconductor package known in general, that is, a semiconductor package formed by molding the entire surface of the chip with resin, the package can be made light and small in size. As a result, the mounting efficiency can be improved, and the present invention can advantageously cope with the recent trend of miniaturization of electric and electronic products.

그러나, 상기와 같은 종래 기술에 따른 칩 크기의 패키지는 반도체 칩과 리드들은 금속 와이어에 의해 전기적으로 연결되기 때문에 금속 와이어의 루프로 인한 전체적인 패키지의 두께를 감소시키는데 한계가 있다. 또한, 패키지의 외부로 노출된 리드부분을 이용하여 기판에 실장시키고자 할 때, 솔더링이 잘못된 경우에는 기판과 리드의 밀착성으로 인하여 재가공 공정이 어려운 문제점이 있었다.However, the chip sized package according to the related art has a limitation in reducing the overall thickness of the package due to the loop of the metal wire because the semiconductor chip and the leads are electrically connected by the metal wire. In addition, when mounting on the substrate using the lead portion exposed to the outside of the package, when soldering is wrong, there was a problem that the reprocessing process is difficult due to the adhesion of the substrate and the lead.

따라서, 본 고안의 목적은 반도체 칩과 리드와의 전기적 연결시 반도체 칩의 본드 패드 상에 도전성 범프를 형성하고, 이를 이용하여 반도체 칩과 리드를 전기적으로 연결함으로써 전체적인 패키지의 두께를 감소시킬 수 있는 칩 크기의 패키지를 제공하는 데 있다.Therefore, an object of the present invention is to form a conductive bump on the bond pad of the semiconductor chip when the electrical connection between the semiconductor chip and the lead, it is possible to reduce the thickness of the overall package by electrically connecting the semiconductor chip and the lead using the same To provide a chip-sized package.

또한, 본 고안의 목적은 패키지의 외부로 노출된 리드 부분에서 솔더 볼을 형성하고, 이를 이용하여 패키지를 기판 상에 실장시킴으로써, 솔더링 공정에서 불량이 발생될지라도 손쉽게 재가공 공정을 실시할 수 있는 칩 크기의 패키지를 제공하는 데 있다.In addition, an object of the present invention is to form a solder ball in the lead portion exposed to the outside of the package, by using it to mount the package on the substrate, even if a defect occurs in the soldering process can be easily reworked chip To provide a package of size.

제1도는 종래 기술에 따른 칩 크기의 패키지를 설명하기 위한 도면.1 is a view for explaining a chip sized package according to the prior art.

제2도는 본 고안에 따른 칩 크기의 패키지를 설명하기 위한 도면.2 is a view for explaining a chip size package according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체 칩 12 : 리드 프레임11: semiconductor chip 12: lead frame

13 : Au 범프 14 : 패키지 몸체13: Au Bump 14: Package Body

15 : 솔더 볼15: solder ball

상기와 같은 목적은 달성하기 위한 본 고안의 칩 크기의 패키지는 도전성 범프가 형성된 다수개의 본딩 패드들이 구비되어 있는 반도체 칩과, 상기 칩의 본딩 패드에 형성된 도전성 범프에 의해 전기적으로 연결되어 칩의 외부로의 신호 전달경로를 이루며, 직선의 형태이고, 그의 일부분에는 디프레스 공정에 의하여 형성된 돌출부를 갖는 리드 프레임과, 상기 반도체 칩과 이에 연결된 리드 프레임을 봉지하며, 상기 리드 프레임의 돌출부 표면이 그의 외부로 노출되도록 형성된 패키지 몸체로 이루어지며, 노출된 리드 프레임의 돌출부에 솔더 볼을 부착시키고, 이를 이용하여 기판에 실장하도록 된 것을 특징으로 한다.In order to achieve the above object, a chip size package of the present invention includes a semiconductor chip having a plurality of bonding pads having conductive bumps formed thereon, and electrically connected to each other by a conductive bump formed on the bonding pads of the chip. And a lead frame having a protrusion formed by a depressing process and a part of the semiconductor chip and a lead frame connected thereto, the surface of the protrusion of the lead frame being formed on the outside thereof. The package body is formed so as to be exposed, and the solder ball is attached to the protrusion of the exposed lead frame, it is characterized in that it is mounted on the substrate by using it.

본 고안에 따르면, 범프를 사용하여 반도체 칩과 리드 프레임을 연결하기 때문에 금속 와이어를 이용하여 칩과 리드 프레임을 연결하는 통상의 패키지에 비해 상기 패키지의 전체적인 두께를 더욱 얇게 할 수 있다.According to the present invention, since the bumps are used to connect the semiconductor chip and the lead frame, the overall thickness of the package can be made thinner than that of the conventional package connecting the chip and the lead frame using the metal wire.

[실시예]EXAMPLE

이하, 도 2을 참조하여 본 고안을 보다 상세하게 설명한다.Hereinafter, the present invention will be described in more detail with reference to FIG. 2.

도 2는 본 고안에 따른 칩 크기의 패키지를 설명하기 위한 도면으로서, 도시된 바와 같이, 집적회로가 구비된 반도체 칩(11)은 그의 본드 패드(도시되지 않음)상에 도전성 범프(13)가 형성되어 있으며, 도전성 범프(13)로서는 Au와 같은 금속이 사용되고, 약 50μm 미만의 두께로 형성된다. 또한, 반도체 칩(11)과 연결되어 상기 반도체 칩(11)의 외부와 신호 전달 경로를 이루는 리드 프레임(12)은 일직선의 형태로 제작되며, 특히, 디프레스(DEPRESS) 공정에 의해 그의 소정 부분에 돌출부가 구비되도록 제작된다.FIG. 2 is a view for explaining a chip size package according to the present invention. As illustrated, the semiconductor chip 11 having an integrated circuit includes a conductive bump 13 formed on a bond pad (not shown) thereof. A metal such as Au is used as the conductive bump 13, and is formed to a thickness of less than about 50 µm. In addition, the lead frame 12, which is connected to the semiconductor chip 11 and forms a signal transmission path with the outside of the semiconductor chip 11, is manufactured in a straight line shape, and in particular, a predetermined portion thereof by a depress process. It is manufactured to be provided with a protrusion.

상기와 같이 돌출부가 구비된 리드 프레임(12)은 반도체 칩(11)의 본드 패드에 형성된 Au범프(13)에 의해 상기 반도체 칩(11)과 전기적으로 연결되어 상기 반도체 칩(11)의 외부와의 신호 전달 경로를 이룬다. 여기서, 반도체 칩(11)과 리드 프레임(13)은 Au범프(13)에 의해 전기적으로 연결되기 때문에 금속 와이어에 의해 반도체 칩과 리드 프레임을 연결하는 통상의 반도체 패키지에 비해 전체적인 패키지의 두께를 감소시키게 된다.As described above, the lead frame 12 having the protrusion is electrically connected to the semiconductor chip 11 by Au bumps 13 formed on the bond pads of the semiconductor chip 11, and the outside of the semiconductor chip 11. Signal transduction path. Here, since the semiconductor chip 11 and the lead frame 13 are electrically connected by the Au bumps 13, the thickness of the overall package is reduced as compared with a conventional semiconductor package connecting the semiconductor chip and the lead frame by metal wires. Let's go.

계속해서, 반도체 칩(11)과 그의 본드 패드에 형성된 Au범프(13)에 의해 전기적으로 연결된 리드 프레임(2)은 레진(Resin)에 의해 봉지되어 패키지 몸체(14)를 이루게 되며, 이때, 반도체 몸체(14)는 리드 프레임(12)의 돌출부 표면이 그의 외부로 노출되도록 형성된다.Subsequently, the lead frame 2 electrically connected by the semiconductor chip 11 and the Au bumps 13 formed on the bond pads thereof is sealed by a resin to form the package body 14. The body 14 is formed such that the protrusion surface of the lead frame 12 is exposed to the outside thereof.

또한, 패키지 몸체(14)로부터 노출된 리드 프레임(12)의 돌출부에는 솔더 볼(15)이 형성되며, 후속 공정인 패키지를 기판 상에 붙이는 실장 공정에서 상기와 같이 리드 프레임(12)의 돌출부에 형성시킨 솔더 볼(15)를 이용하여 소정의 회로 패턴이 구비된 인쇄회로기판(도시되지 않음)상에 상기와 같은 칩 크기의 패키지가 실장되도록 한다.In addition, the solder ball 15 is formed in the protrusion of the lead frame 12 exposed from the package body 14, and the protrusion of the lead frame 12 as described above in the mounting process of attaching the package on the substrate, which is a subsequent process. The formed solder ball 15 is used to mount the package of the chip size on a printed circuit board (not shown) provided with a predetermined circuit pattern.

상기에서, 칩 크기의 패키지는 솔더볼을 사용하여 상기 패키지를 기판 상에 실장시키기 때문에 기판과 패키지 사이에 솔더볼의 두께만큼의 간격을 유지할 수 있다. 따라서, 리드를 기판 상에 직접 솔더링 하는 종래의 패키지에 비해 솔더링 공정의 불량이 발생된 경우에서도 재가공 공정이 가능하며, 손쉽게 패키지의 교체 작업을 실시할 수 있게 된다.In the above-described package, the chip size package may maintain the thickness of the solder ball between the substrate and the package because the package is mounted on the substrate using solder balls. Therefore, the reprocessing process is possible even when a defect in the soldering process occurs compared to the conventional package in which the lead is directly soldered onto the substrate, and the package can be easily replaced.

이상에서와 같이, 본 고안의 칩 크기의 패키지는 도전성 범프를 사용하여 반도체 칩과 리드 프레임을 연결하기 때문에 전체적으로 더 얇은 패키지를 제조할 수 있으며, 솔더 볼을 이용하여 인쇄회로기판에 상기 패키지를 실장함으로써 솔더 볼의 높이만큼 기판과 패키지와의 간격을 유지시켜 패키지의 열방출 능력을 향상시킬 수 있다. 또한, 기판상에 패키지를 실장시키기 위하여 솔더 볼을 이용하기 때문에 실장 불량을 줄이고, 패키지를 교환하는 등의 재작업이 용이하다.As described above, the chip size package of the present invention can manufacture a thinner package as a whole by connecting a semiconductor chip and a lead frame using conductive bumps, and mount the package on a printed circuit board using solder balls. As a result, the gap between the substrate and the package is maintained by the height of the solder ball, thereby improving the heat dissipation capability of the package. In addition, since solder balls are used to mount the package on the substrate, it is easy to reduce mounting defects and to rework the package.

한편, 여기에서는 본 고안의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 실용신안등록 청구의 범위는 본 고안의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Therefore, the utility model registration claims will be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

다수개의 본딩 패드가 구비된 반도체 칩 ; 상기 반도체 칩의 본딩 패드에 형성된 도전성 범프 ; 상기 반도체 칩의 본딩 패드 형성면가 대향, 배치되어, 상기 도전성 범프를 매개로 반도체 칩의 본딩 패드에 전기적으로 연결되며, 하부를 향해 돌출부가 형성된 리드 프레임 ; 상기 리드 프레임의 돌출부만이 노출되도록, 전체 결과물을 봉지하는 패키지 몸체 ; 및 상기 패키지 몸체로부터 노출된 리드 프레임의 돌출부에 형성된 솔더 볼을 포함하는 것을 특징으로하는 칩 크기의 패키지.A semiconductor chip having a plurality of bonding pads; Conductive bumps formed on the bonding pads of the semiconductor chip; A lead frame having a bonding pad forming surface of the semiconductor chip facing and disposed to be electrically connected to the bonding pad of the semiconductor chip via the conductive bumps, and having a protrusion formed downward; A package body encapsulating the entire resultant so that only the protrusion of the lead frame is exposed; And solder balls formed on protrusions of the lead frame exposed from the package body. 제1항에 있어서, 상기 도전성 범프의 재질은 금인 것을 특징으로 하는 칩 크기의 패키지.The chip sized package of claim 1, wherein the conductive bump is made of gold. 제2항에 있어서, 상기 금 재질의 범프 높이는 50μm 미만인 것을 특징으로 하는 칩 크기의 패키지.The chip size package of claim 2, wherein the bump height of the gold material is less than 50 μm.
KR2019970016156U 1997-06-27 1997-06-27 Chip sized package Expired - Fee Related KR200172710Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019970016156U KR200172710Y1 (en) 1997-06-27 1997-06-27 Chip sized package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019970016156U KR200172710Y1 (en) 1997-06-27 1997-06-27 Chip sized package

Publications (2)

Publication Number Publication Date
KR19990002582U KR19990002582U (en) 1999-01-25
KR200172710Y1 true KR200172710Y1 (en) 2000-03-02

Family

ID=19504276

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019970016156U Expired - Fee Related KR200172710Y1 (en) 1997-06-27 1997-06-27 Chip sized package

Country Status (1)

Country Link
KR (1) KR200172710Y1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583494B1 (en) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 Semiconductor Package

Also Published As

Publication number Publication date
KR19990002582U (en) 1999-01-25

Similar Documents

Publication Publication Date Title
KR0169820B1 (en) Chip scale package with metal wiring substrate
KR100194747B1 (en) Semiconductor device
US6864588B2 (en) MCM package with bridge connection
US7015591B2 (en) Exposed pad module integrating a passive device therein
US6894904B2 (en) Tab package
KR0157857B1 (en) Semiconductor package
KR19990024255U (en) Stacked Ball Grid Array Package
KR200172710Y1 (en) Chip sized package
KR100331070B1 (en) Structure of chip size semiconductor package and fabricating method thereof
KR100260996B1 (en) Array type semiconductor package using a lead frame and its manufacturing method
KR100230921B1 (en) Structure and manufacturing method of CSP (Chip Scale Package)
JP3545171B2 (en) Semiconductor device
KR100251860B1 (en) Structure of csp and its making method
KR100216845B1 (en) Structure and manufacturing method of CSP (Chip Scale Package)
KR100226106B1 (en) Ball Grid Array Semiconductor Package Using Lead Frame and Manufacturing Method Thereof
KR20030033706A (en) Flipchip Package
KR20030025481A (en) flip-chip semiconductor package and method of manufacturing thereof
KR200313831Y1 (en) Bottom Lead Package
KR20000001410A (en) Ball grid array pacakge
KR20020031881A (en) A semiconductor package and it's manufacture method
KR20000002808A (en) Ball grid array package and manufacturing method thereof
KR950000516B1 (en) Semiconductor assembly device
KR100230922B1 (en) A structure of csp and manufacturing method thereof
KR19980082181A (en) Lead-on chip type chip scale semiconductor package structure and manufacturing method
KR100225238B1 (en) Structure of csp and making method thereof

Legal Events

Date Code Title Description
A201 Request for examination
R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

UA0108 Application for utility model registration

St.27 status event code: A-0-1-A10-A12-nap-UA0108

UA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-UA0201

UG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-UG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
UE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-UE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
UE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-UE0701

REGI Registration of establishment
UR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-UR0701

UR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-UR1002

Fee payment year number: 1

UG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-UG1601

UN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-UN2301

St.27 status event code: A-5-5-R10-R11-asn-UN2301

UN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-UN2301

St.27 status event code: A-5-5-R10-R11-asn-UN2301

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 4

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 5

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 6

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 7

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 8

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20081125

Year of fee payment: 10

UR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-UR1001

Fee payment year number: 10

LAPS Lapse due to unpaid annual fee
UC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-UC1903

Not in force date: 20091214

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

UC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-UC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20091214

UN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-UN2301

St.27 status event code: A-5-5-R10-R11-asn-UN2301

UN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-UN2301

St.27 status event code: A-5-5-R10-R11-asn-UN2301

UN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-UN2301

St.27 status event code: A-5-5-R10-R11-asn-UN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000