JPH04359457A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04359457A JPH04359457A JP3134423A JP13442391A JPH04359457A JP H04359457 A JPH04359457 A JP H04359457A JP 3134423 A JP3134423 A JP 3134423A JP 13442391 A JP13442391 A JP 13442391A JP H04359457 A JPH04359457 A JP H04359457A
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- bare
- chip
- circuit board
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 239000011347 resin Substances 0.000 claims abstract description 22
- 238000007789 sealing Methods 0.000 claims abstract description 14
- 239000000853 adhesive Substances 0.000 claims abstract description 12
- 230000001070 adhesive effect Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 4
- 230000010354 integration Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 19
- 238000010586 diagram Methods 0.000 description 14
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000000605 extraction Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000010396 two-hybrid screening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】［発明の目的］[Object of the invention]
【０００２】0002
【産業上の利用分野】本発明は、半導体装置およびその
製造方法にかかり、特に複数のベアＩＣチップを両面基
板に実装して小形・高密度化を図ったＣＯＢ構造に関す
るものである[Industrial Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a COB structure in which a plurality of bare IC chips are mounted on a double-sided substrate to achieve compactness and high density.
【０００３】。[0003].
【従来の技術】近年、ＣＯＢ（Ｃｈｉｐ ｏｎ ｂ
ｏａｒｄ）などの高密度実装における軽薄短小高機能化
の傾向は高まる一方である。[Prior Art] In recent years, COB (Chip on b)
The trend toward lighter, thinner, shorter, and more sophisticated devices in high-density packaging, such as the OARD), continues to increase.
【０００４】高機能化という点に着目すると、限られた
寸法の混成集積回路内により多くの品種を複数個並べて
搭載し接続するには困難な状況にある。[0004] When focusing on high functionality, it is difficult to mount and connect a plurality of products of various types in a hybrid integrated circuit having a limited size.
【０００５】図１１には全体図、図１２は要部拡大図、
図１３は斜視図を示す。この半導体装置では、プリント
基板１の表面に６つの多品種のベアＩＣチップ（チップ
コーティング前のＩＣチップ）６を搭載し、ボンディン
グワイヤ７を介してベアＩＣチップの電極と基板の配線
パターンとの相互接続配線を行い、パッケージ８内に封
止を行うようにしたものである。９および１０はリード
端子（配線パターン）である。FIG. 11 is an overall view, FIG. 12 is an enlarged view of main parts,
FIG. 13 shows a perspective view. In this semiconductor device, six bare IC chips of various types (IC chips before chip coating) 6 are mounted on the surface of a printed circuit board 1, and the electrodes of the bare IC chips and the wiring pattern of the board are connected via bonding wires 7. Interconnection wiring is performed and sealing is performed within the package 8. 9 and 10 are lead terminals (wiring patterns).
【０００６】このように長さの決められた混成集積回路
内にパッケージ内に多品種のベアＩＣチップを複数個並
べて実装した場合、その種類および数が限られるばかり
でなく、混成集積回路内におけるベアＩＣチップの占有
面積が大きくなり、ワイヤボンディングが難しくなると
いう問題がある。[0006] When a plurality of bare IC chips of various types are mounted side by side in a package in a hybrid integrated circuit with a predetermined length as described above, not only the types and number of bare IC chips are limited, but also the number of bare IC chips in the hybrid integrated circuit is limited. There is a problem that the bare IC chip occupies a large area, making wire bonding difficult.
【０００７】ところでさらに高密度化しようとする場合
は、両面実装が望ましい。[0007] However, when attempting to achieve even higher density, double-sided mounting is desirable.
【０００８】しかしながら、この従来の構造の場合プリ
ント基板１裏面に部品等が実装されていると、ワイヤボ
ンディングの際に基板をクランプすることが不可能とな
るため、ベアベアチップを複数個実装する場合は図１１
，図１２，図１３に示したようにプリント基板片面にし
か実装できない等の不具合がある。However, in this conventional structure, if components etc. are mounted on the back side of the printed circuit board 1, it is impossible to clamp the board during wire bonding. is Figure 11
, as shown in FIGS. 12 and 13, there are problems such as the fact that it can only be mounted on one side of a printed circuit board.
【０００９】また、従来技術で両面実装を行った例とし
ては、図１４（ａ） および（ｂ） ，図１５に示すよ
うに、パッケ―ジタイプのＩＣ１１を使用する方法があ
る。このようにパッケ―ジタイプのＩＣ１１を使用する
ことにより、プリント基板１の両面に実装ができる。１
０はリード端子である。Further, as an example of double-sided mounting using conventional technology, there is a method using a package type IC 11, as shown in FIGS. 14(a) and 14(b) and FIG. 15. By using the package type IC 11 in this manner, it can be mounted on both sides of the printed circuit board 1. 1
0 is a lead terminal.
【００１０】この両面実装型の半導体装置は、片面にし
かベアＩＣチップが実装できない図１１，図１２，図１
３に示したような混成集積回路に比べ、厚さが厚くなる
上、パッケ―ジタイプのＩＣ１１を両面に実装している
ため、ものによっては混成集積回路イズが、片面実装型
混成集積回路とほぼ同等レベルもしくは大きくなってし
まうことがある。[0010] In this double-sided mounting type semiconductor device, a bare IC chip can only be mounted on one side.
Compared to the hybrid integrated circuit shown in 3, it is thicker and the package type IC11 is mounted on both sides, so in some cases the hybrid integrated circuit size is almost the same as that of a single-sided mounted hybrid integrated circuit. It may be the same level or even larger.
【００１１】また両面実装型の半導体装置の他の例とし
て、図１６に示すように、プリント基板１の表面にベア
ＩＣチップを実装するとともに、裏面にはチップコンデ
ンサ３０，チップ抵抗３１，ＳＯＰ（Ｓｍａｌｌ Ｏ
ｕｔｌｉｎｅ Ｐａｋｋａｇｅ）３２等のパッケージ
ングのなされた表面実装部品を搭載したものも提案され
ている。しかしながら、従来の実装構造によると、ワイ
ヤボンディングに際してのクランプができないため、片
面にしかベアＩＣチップ６を搭載することができない。
したがって、これらのベアＩＣチップ６が搭載されてい
る表面でほとんど実装占有面積が決まり、裏面にはチッ
プコンデンサ３０，チップ抵抗３１，ＳＯＰ（Ｓｍａｌ
ｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）３２等の表
面実装部品が搭載されているにすぎず、かなりのすき間
が生じ、高密度に実装することが出来ない等の問題があ
る。As another example of a double-sided mounting type semiconductor device, as shown in FIG. Small O
A device equipped with surface mount components packaged such as Utline Package) 32 has also been proposed. However, according to the conventional mounting structure, the bare IC chip 6 can only be mounted on one side because clamping cannot be performed during wire bonding. Therefore, most of the mounting area is determined by the surface on which these bare IC chips 6 are mounted, and the chip capacitor 30, chip resistor 31, and SOP (Small) are mounted on the back surface.
1 Outline Package) 32 and other surface mount components are mounted thereon, and there are problems such as considerable gaps are created and high-density mounting is not possible.
【００１２】そこでこの問題を解決すべく、ただ単に両
面にベアＩＣチップ６を実装しようとすると最初に裏面
に搭載された部品（ベアＩＣチップ，コンデンサ，抵抗
，ＳＯＰ等）の領域だけはボンディングステ―ジ１７の
方でザグリを入れて逃がさなければならず、さらに表面
にベアＩＣチップ６を搭載してワイヤボンディングを行
なう際、このザグリを入れた領域（部分）はしっかりと
クランプができない。つまり、このザグリを入れた部分
に相当する反対側（表面）の部分に配線パターン４が配
設される場合はこの配線パターン４へのワイヤボンディ
ングは十分プリント基板１上の配線パターン４を押え付
けてクランプすることができないため、熱と超音波エネ
ルギ―を効率良く、伝達できずボンディング性が著しく
悪く品質が大幅に低下する等の問題が生じる。Therefore, in order to solve this problem, if one attempts to simply mount the bare IC chip 6 on both sides, only the area of the components (bare IC chip, capacitor, resistor, SOP, etc.) mounted on the back side is covered by the bonding step. - It is necessary to make a counterbore in the groove 17 to release it, and furthermore, when the bare IC chip 6 is mounted on the surface and wire bonding is performed, the area (portion) where the counterbore is made cannot be firmly clamped. In other words, if the wiring pattern 4 is placed on the opposite side (front surface) corresponding to the counterbore area, wire bonding to this wiring pattern 4 will sufficiently press down the wiring pattern 4 on the printed circuit board 1. Since it is not possible to clamp the bonding material using the bonding method, heat and ultrasonic energy cannot be efficiently transmitted, leading to problems such as extremely poor bonding properties and a significant drop in quality.
【００１３】この問題は、ワイヤボンディング方式の実
装構造に限定されることなく、フリップチップなどのフ
ェイスダウンボンディング方式すなわちボンディングワ
イヤを用いることなく実装を行うダイレクトボンディン
グ方式の実装構造においても、ボンディングに際しての
十分なクランプができなかったり、表面の平坦性が悪く
なったりして、十分に高精度の位置決めを行うことがで
きないという問題があった。[0013] This problem is not limited to wire bonding type mounting structures, but also in face-down bonding type mounting structures such as flip chips, that is, direct bonding type mounting structures in which mounting is performed without using bonding wires. There has been a problem in that sufficient clamping cannot be performed or the surface flatness deteriorates, making it impossible to perform positioning with sufficiently high precision.
【００１４】[0014]
【発明が解決しようとする問題点】このようにワイヤボ
ンディングに際しては、プリント基板，ベアＩＣチップ
，金ワイヤに対して熱と超音波を効率良くまた均一に伝
え安定かつ良好な接合強度を確保しなければならない。
そのためプリント基板をボンディングステ―ジに密着さ
せ、押え治具でしっかり固定させる必要がある。従って
、ボンディングステ―ジの基板接触面は凹凸のない平坦
な面になるような構造となっているために、プリント基
板裏面に部品等が実装されていることは許されず、ワイ
ヤボンディング方法によりベアＩＣチップを複数個実装
する場合でもプリント基板片面にしか実装できず、実装
密度が上がらないという問題点があった。[Problems to be Solved by the Invention] In wire bonding, it is necessary to efficiently and uniformly transmit heat and ultrasonic waves to printed circuit boards, bare IC chips, and gold wires to ensure stable and good bonding strength. There must be. Therefore, it is necessary to bring the printed circuit board into close contact with the bonding stage and firmly fix it with a holding jig. Therefore, since the board contact surface of the bonding stage is structured to be a flat surface with no irregularities, it is not allowed to have components mounted on the back side of the printed circuit board, and the wire bonding method is used to Even when multiple IC chips are mounted, there is a problem in that they can only be mounted on one side of a printed circuit board, and the mounting density cannot be increased.
【００１５】また、ただ単に両面にベアＩＣチップを実
装して高密度化をはかろうとすると、先に表面に実装さ
れた部品は裏面にベアＩＣチップを搭載してワイヤボン
ディングする際はじゃまになり、この部分だけは逃げが
必要となる。[0015] Also, if you try to increase the density by simply mounting bare IC chips on both sides, the components mounted on the front side will get in the way when the bare IC chips are mounted on the back side and wire bonding is performed. Therefore, only this part requires escape.
【００１６】これはワイヤボンディング方式の実装のみ
ならず、ワイヤレス（ダイレクト）ボンディング方式の
実装においても大きな問題となっていた。[0016] This has been a major problem not only in the implementation of the wire bonding method but also in the implementation of the wireless (direct) bonding method.
【００１７】本発明は、前記実情に鑑みてなされたもの
で、小形でしかも高密度実装を行うことのできる両面実
装構造を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a double-sided mounting structure that is compact and capable of high-density mounting.
【００１８】[0018]
【問題点を解決するための手段】そこで本発明の第１で
は、配線パターンの形成されたプリント基板の両面にそ
れぞれ少なくとも１個のベアＩＣチップを搭載し、両面
を樹脂封止した半導体装置において、プリント基板の表
面または裏面の少なくとも一方に、当該面に搭載される
ベアＩＣチップの高さよりも高い樹脂封止用の枠を配設
するようにしている。[Means for Solving the Problems] Accordingly, the first aspect of the present invention provides a semiconductor device in which at least one bare IC chip is mounted on each side of a printed circuit board on which a wiring pattern is formed, and both sides are sealed with resin. A frame for resin sealing that is higher than the height of the bare IC chip mounted on the printed circuit board is disposed on at least one of the front surface and the back surface of the printed circuit board.
【００１９】望ましくはリード引き出し端子は、枠の形
成された面の反対側の面の所定の領域に配設する。Preferably, the lead extraction terminal is provided in a predetermined area on the surface opposite to the surface on which the frame is formed.
【００２０】さらにこの枠は、搭載部品およびその周辺
部品のいずれよりも高くなるように形成する必要がある
。Furthermore, this frame needs to be formed higher than both the mounted component and its surrounding components.
【００２１】本発明の第２では、プリント基板表面に、
少なくとも１個のベアＩＣチップを搭載し、前記プリン
ト基板の配線パターンに結線し、この面に、樹脂封止用
の枠を取付けた後、このプリント基板の裏面に少なくと
も１個のベアＩＣチップを搭載し、配線パターンに結線
するようにしている。In the second aspect of the present invention, on the surface of the printed circuit board,
After mounting at least one bare IC chip and connecting it to the wiring pattern of the printed circuit board, and attaching a resin sealing frame to this surface, at least one bare IC chip is mounted on the back surface of the printed circuit board. It is installed and connected to the wiring pattern.
【００２２】本発明の第３では、配線パターンの形成さ
れたプリント基板表面に少なくとも１つのベアＩＣチッ
プを搭載し、このベアＩＣチップと配線パターンとを接
続するとともに、まわりを樹脂封止してなる混成集積回
路を裏面側が相対向するように絶縁性の接着部材を介し
て貼着するようにしている。In the third aspect of the present invention, at least one bare IC chip is mounted on the surface of the printed circuit board on which the wiring pattern is formed, the bare IC chip and the wiring pattern are connected, and the surrounding area is sealed with resin. The hybrid integrated circuits are attached via an insulating adhesive member so that their back sides face each other.
【００２３】望ましくは、端部で、両プリント基板をは
さみ込むように形成されたリード引き出し端子を設置し
、このリード引き出し端子は表面および裏面の配線パタ
ーンと接続されるようになっている。Preferably, a lead-out terminal formed to sandwich both printed circuit boards is installed at the end, and this lead-out terminal is connected to the wiring patterns on the front and back sides.
【００２４】また望ましくは、端部で、両プリント基板
の間にをはさみ込まれるように形成されたリード引き出
し端子を配設し、表面および裏面の配線パターンと接続
するようにしている。Preferably, a lead lead terminal is provided at the end so as to be sandwiched between the two printed circuit boards, and is connected to the wiring patterns on the front and back surfaces.
【００２５】[0025]
【作用】上記第１の構成によれば、表面に部品の高さよ
り高い枠を取付け、しかも裏面の配線パターンは表面の
枠の領域内にあるようにして両面に複数個のベアＩＣチ
ップを実装するようにしているので、従来の片面ベアＩ
Ｃチップ実装に比べて実装面積の縮小化を図ることがで
きる。また従来の両面ベアＩＣチップ実装に比べてボン
ディング性に優れ品質向上が期待できる。[Operation] According to the first configuration, a frame higher than the height of the component is attached to the front surface, and a plurality of bare IC chips are mounted on both sides with the wiring pattern on the back side being within the area of the front frame. Therefore, the conventional single-sided bear I
The mounting area can be reduced compared to C chip mounting. Furthermore, compared to conventional double-sided bare IC chip mounting, bonding properties are excellent and quality improvement can be expected.
【００２６】また、リード引き出し端子は、枠の形成さ
れた面の反対側の面の所定の領域に配設することにより
、平坦性を良好に維持したまま、裏面側（枠の形成され
た面の反対側の面）の実装を行うことができる。[0026] Furthermore, by disposing the lead extraction terminal in a predetermined area on the surface opposite to the surface on which the frame is formed, the lead extraction terminal can be placed on the back side (the surface on which the frame is formed) while maintaining good flatness. (opposite surface) can be implemented.
【００２７】さらにこの枠は、搭載部品およびその周辺
部品のいずれよりも高くなるように形成することにより
、裏面側の実装に際しボンディングステージに密着性よ
く装着することができる。Furthermore, by forming this frame so that it is higher than both the mounted component and its surrounding components, it can be attached to the bonding stage with good adhesion during mounting on the back side.
【００２８】本発明の第２の方法によれば、プリント基
板表面に、少なくとも１個のベアＩＣチップを搭載し、
前記プリント基板の配線パターンに結線し、プリント基
板の裏面にベアＩＣチップを搭載し、結線するに先立ち
、この表面に、樹脂封止用の枠を取付けるようにしてい
るため、この枠によってベアチップＩＣが保護されると
共に表面の平坦性を保つことが可能となり、裏面側の実
装に際し、表面側をボンディングステージに密着性よく
装着することができ、高精度で確実な実装を行うことが
できる。According to the second method of the present invention, at least one bare IC chip is mounted on the surface of the printed circuit board,
Before wiring is connected to the wiring pattern of the printed circuit board, a bare IC chip is mounted on the back side of the printed circuit board, and a frame for resin sealing is attached to this surface before wiring. It is possible to protect the surface and maintain the flatness of the surface, and when mounting the back side, the front side can be attached to the bonding stage with good adhesion, making it possible to perform highly accurate and reliable mounting.
【００２９】ここで、結線方法としては、ワイヤボンデ
ィング、ダイレクトボンディングのいずれをも適用可能
である。また、表面側の樹脂封止は、裏面側のチップの
搭載の前でも後でも良い。[0029] As the connection method, either wire bonding or direct bonding can be applied. Furthermore, the resin sealing on the front side may be performed before or after mounting the chip on the back side.
【００３０】本発明の第３によれば、ベアＩＣチップを
１枚のプリント基板に片面実装し、もう１枚のプリント
基板も同様にベアＩＣチップを用いて片面実装し、その
後２枚のプリント基板の実装されていない片面同志を絶
縁性の接着剤又はシ―トを介し貼り合わせることにより
、疑似的な両面ＣＯＢ構造の混成集積回路を提供できる
ため、従来の片面のみにベアＩＣチップを実装するＣＯ
Ｂ構造の混成集積回路及びパッケ―ジタイプのＩＣで構
成された両面構造の混成集積回路と比較した場合大幅な
小形化，高密度化を計ることができる。According to the third aspect of the present invention, a bare IC chip is mounted on one side of one printed circuit board, another printed circuit board is similarly mounted on one side using bare IC chips, and then two printed circuit boards are mounted. By bonding the unmounted sides of the board together using an insulating adhesive or sheet, it is possible to provide a hybrid integrated circuit with a pseudo-double-sided COB structure, making it possible to mount bare IC chips on only one side of the conventional board. CO
When compared with a B-structure hybrid integrated circuit and a double-sided structure hybrid integrated circuit composed of package-type ICs, it is possible to significantly reduce the size and increase the density.
【００３１】[0031]
【実施例】次に、本発明の実施例について、図面を参照
しつつ詳細に説明する。Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００３２】図１は、本発明の一実施例であって、図１
（ａ） は断面図、図１（ｂ） は（Ｃ方向から見た）
上面図、図１（ｃ） は（Ｄ方向から見た）下面図、図
１（ｄ） は側面図を示す。FIG. 1 shows an embodiment of the present invention.
(a) is a cross-sectional view, and Figure 1 (b) is (viewed from direction C)
FIG. 1(c) is a top view, FIG. 1(c) is a bottom view (as seen from direction D), and FIG. 1(d) is a side view.
【００３３】この半導体装置では、プリント基板１の表
面および裏面にベアＩＣチップ６を搭載し、これらを囲
むようにエポキシ樹脂からなる枠９を配設したことを特
徴とするものである。This semiconductor device is characterized in that bare IC chips 6 are mounted on the front and back surfaces of a printed circuit board 1, and a frame 9 made of epoxy resin is disposed to surround them.
【００３４】すなわち、金の配線パターン４の形成され
たプリント基板１の表面に２つ裏面に１つの他品種のベ
アＩＣチップ６を搭載し、ボンディングワイヤ７を介し
てチップの電極（ボンディングパッド）２０と配線パタ
ーン４との間で相互に接続配線を行い、チップコーティ
ング樹脂８によって封止を行うようにしたものである。
１９は圧着ボールである。また前記配線パターン４には
、ガラエピを基材としてＣｕ箔にＮｉめっきをし、その
後金めっきを施して形成されている外部接続用のリード
引き出し端子１０が接続されている。That is, two bare IC chips 6 of different types are mounted on the front surface of the printed circuit board 1 on which the gold wiring pattern 4 is formed, and one bare IC chip 6 of another type is mounted on the back surface, and the electrodes (bonding pads) of the chips are mounted via bonding wires 7. 20 and the wiring pattern 4 are connected to each other and sealed with a chip coating resin 8. 19 is a press-bonded ball. Further, a lead extraction terminal 10 for external connection is connected to the wiring pattern 4, which is formed by using glass epitaxial glass as a base material and plating Cu foil with Ni and then plating with gold.
【００３５】３０はコンデンサ，３１は抵抗，３２はＳ
ＯＰであり、いずれも配線パターン４上に半田あるいは
銀ペーストなどの導電性接着剤で固着されている。30 is a capacitor, 31 is a resistor, 32 is S
Both are OP, and are fixed onto the wiring pattern 4 with solder or a conductive adhesive such as silver paste.
【００３６】次に、この半導体装置の実装方法について
説明する。Next, a method for mounting this semiconductor device will be explained.
【００３７】まず、両面に所定の配線パターン４の形成
されたプリント基板１を用意する。ついで、必要に応じ
て、スクリーン印刷法等を用いて、コンデンサ，抵抗，
ＳＯＰなどを接続する領域の配線パターン上に半田パタ
ーン（図示せず）を形成し、コンデンサ，抵抗，ＳＯＰ
などをリフロー半田付けする。First, a printed circuit board 1 having a predetermined wiring pattern 4 formed on both sides is prepared. Then, if necessary, capacitors, resistors,
A solder pattern (not shown) is formed on the wiring pattern in the area where the SOP etc. will be connected, and the capacitor, resistor, SOP etc.
etc. for reflow soldering.
【００３８】この後、まずプリント基板１の表面側のチ
ップ搭載領域にベアＩＣチップ６を銀ペーストなどを用
いて固着する（ダイボンディング）。After that, first, the bare IC chip 6 is fixed to the chip mounting area on the front side of the printed circuit board 1 using silver paste or the like (die bonding).
【００３９】そして、図２乃至図４に示す方法でワイヤ
ボンディングを行う。Then, wire bonding is performed by the method shown in FIGS. 2 to 4.
【００４０】ワイヤボンディングは次のようにして行わ
れる。Wire bonding is performed as follows.
【００４１】まずに銀ペ―スト５を介してベアＩＣチッ
プ６を実装したプリント基板１をヒ―タ内蔵（図示され
ていない）の加熱されたボンディングステ―ジ１７上に
載せ位置決めをする。First, the printed circuit board 1 on which the bare IC chip 6 is mounted via the silver paste 5 is placed on a heated bonding stage 17 with a built-in heater (not shown) and positioned.
【００４２】この後、押え治具１５にてプリント基板１
をクランプする。この段階が終了するとワイヤボンティ
ングが開始される。After that, the printed circuit board 1 is held down using the holding jig 15.
to clamp. Once this stage is complete, wire bonding begins.
【００４３】まず、図２に示すようにキャピラリ―１２
に金ワイヤ７を通した後に電気ト―チ棒１４から高電圧
を印加し、放電させて金ワイヤ７の１部を溶融し、金ボ
―ル２１を作る。First, as shown in FIG.
After passing the gold wire 7 through, a high voltage is applied from the electric torch rod 14 to cause discharge and melt a part of the gold wire 7 to form a gold ball 21.
【００４４】次に図４に示すように、超音波ホ―ン１３
に取付けたキャピラリ―１２を降下させ、ボンディング
ステージ１７上にクランプされたプリント基板１上のベ
アＩＣチップ６の所定の電極２０に圧着させると同時に
超音波発振器（図示しない）から超音波エネルギ―をキ
ャピラリ―１２に伝達させ接合させる。これをファ―ス
トボンディングという（図２）。Next, as shown in FIG. 4, the ultrasonic horn 13
The capillary 12 attached to the bonding stage 17 is lowered and crimped onto a predetermined electrode 20 of the bare IC chip 6 on the printed circuit board 1 clamped on the bonding stage 17. At the same time, ultrasonic energy is applied from an ultrasonic oscillator (not shown). It is transmitted to the capillary 12 and joined. This is called first bonding (Figure 2).
【００４５】このファ―ストボンディングが終了すると
、キャピラリ―１２を上昇させＸＹテ―ブル（図示しな
い）上に搭載されているボンディングヘッド（図示しな
い）をプリント基板１の配線パターン４に移動させ、図
３に示すように再度キャピラリ―１２を降下させプリン
ト基板１の所定のリ―ド端子４に金ワイヤ７を圧着させ
ると同時に超音波発振器（図示しない）からの超音波エ
ネルギ―を印加させ接合させる。これをセカンドボンデ
ィングという。When this first bonding is completed, the capillary 12 is raised and the bonding head (not shown) mounted on the XY table (not shown) is moved to the wiring pattern 4 of the printed circuit board 1. As shown in FIG. 3, the capillary 12 is lowered again and the gold wire 7 is crimped onto the predetermined lead terminal 4 of the printed circuit board 1. At the same time, ultrasonic energy from an ultrasonic oscillator (not shown) is applied to bond the gold wire. let This is called second bonding.
【００４６】その後、キャピラリ―１２を上昇させ、途
中で下クランパ―２２を閉じ、金ワイヤ７をプリント基
板１の配線パターン４より切断する。Thereafter, the capillary 12 is raised, the lower clamper 22 is closed midway, and the gold wire 7 is cut from the wiring pattern 4 of the printed circuit board 1.
【００４７】このようにしてワイヤボンディングの１サ
イクルが終了する。In this way, one cycle of wire bonding is completed.
【００４８】この工程を繰り返して、複数のベアＩＣチ
ップ６の電極２０とプリント基板１の配線パターン４を
金ワイヤ７にて結線する。このボンディング方法を熱圧
着超音波併用ボ―ルボンディングと言う。This process is repeated to connect the electrodes 20 of the plurality of bare IC chips 6 to the wiring pattern 4 of the printed circuit board 1 using the gold wire 7. This bonding method is called thermocompression ultrasonic ball bonding.
【００４９】このようにして表面に搭載されているベア
ＩＣチップ６の電極２０とプリント基板１の配線パター
ン４とを金ワイヤで結線した後、ベアＩＣチップ６のま
わりをチップコ―ティング樹脂８を用いて封止する。After the electrodes 20 of the bare IC chip 6 mounted on the surface and the wiring pattern 4 of the printed circuit board 1 are connected with gold wire in this way, a chip coating resin 8 is applied around the bare IC chip 6. Use to seal.
【００５０】つまり、この装置のボンディングステ―ジ
１７の面はクランプのために凹凸のない平らな面になる
ような構造になっている。That is, the surface of the bonding stage 17 of this device is structured so that it becomes a flat surface without irregularities for clamping.
【００５１】続いて、コンデンサ３０，チップ抵抗３１
は半田パターン上に載置し加熱することにより固着する
。Next, the capacitor 30 and the chip resistor 31
is placed on the solder pattern and fixed by heating.
【００５２】そして図１に示すようにあらかじめ形成さ
れたポリイミド製の枠９を絶縁性接着剤を用いて固着し
、枠の上端をつなぐ面とプリント基板表面とが平行とな
るようにする。Then, as shown in FIG. 1, a preformed polyimide frame 9 is fixed using an insulating adhesive so that the surface connecting the upper ends of the frame is parallel to the surface of the printed circuit board.
【００５３】この後、このプリント基板を裏返しボンデ
ィングステージにこの枠９が密着するように設置する。
このボンディングステ―ジ１７の面はクランプのために
凹凸のない平らな面になっているが、枠のためにプリン
ト基板裏面が平衡度を保つように良好に密着性よくボン
ディングステ―ジ１７に載置される。Thereafter, the printed circuit board is turned over and placed on the bonding stage so that the frame 9 is in close contact with it. The surface of this bonding stage 17 is a flat surface with no irregularities due to the clamping, but because of the frame, the back side of the printed circuit board is placed on the bonding stage 17 with good adhesion so as to maintain balance. It will be placed.
【００５４】そして同様にして、プリント基板１の裏面
側のチップ搭載領域にベアＩＣチップ６を銀ペーストな
どを用いて固着する（ダイボンディング）。Similarly, the bare IC chip 6 is fixed to the chip mounting area on the back side of the printed circuit board 1 using silver paste or the like (die bonding).
【００５５】そして、また同様に図２乃至図４に示した
通常の方法でワイヤボンディングを行う。Then, wire bonding is similarly performed using the usual method shown in FIGS. 2 to 4.
【００５６】続いて、ＳＯＰ３２を裏面側の半田パター
ン上に載置し加熱することにより固着する（リフロー半
田付け）。Subsequently, the SOP 32 is placed on the solder pattern on the back side and fixed by heating (reflow soldering).
【００５７】そしてプリント基板の裏面側にもあらかじ
め形成されたポリイミド製の枠９を絶縁性接着剤を用い
て固着する。A polyimide frame 9 previously formed is also fixed to the back side of the printed circuit board using an insulating adhesive.
【００５８】そして最後に、エポキシ樹脂を枠９内に充
填し、チップコーティング樹脂８から露呈する端部の領
域Ｒの配線パターン４に接続するようにリードフレーム
１０を嵌合し、半田ディップして接続する。Finally, the frame 9 is filled with epoxy resin, the lead frame 10 is fitted so as to be connected to the wiring pattern 4 in the end region R exposed from the chip coating resin 8, and dipped with solder. Connecting.
【００５９】このリードフレームは図５（ａ） および
（ｂ） に平面図およびそのＡ−Ａ断面図を示すように
４２アロイから構成され、先端が断面コの字状をなすよ
うに形成され、他端をタイバーＴで一体的に形成されて
おり、プリント基板との接続後、タイバーＴを切除する
ようになっている。なお、この基板との接続部は、プリ
ント基板の配線パターンと良好に接続するようにさせる
ため、やや先端の間隔が狭くなるように形成されており
、プリント基板を挟んで嵌め、良好に接合できる。As shown in FIGS. 5(a) and 5(b), which are a plan view and a sectional view taken along the line A-A, this lead frame is made of 42 alloy, and the tip is formed to have a U-shaped cross section. The other end is integrally formed with a tie bar T, and the tie bar T is cut off after connection with a printed circuit board. In addition, in order to make a good connection with the wiring pattern of the printed circuit board, the connection part with this board is formed so that the distance between the tips is slightly narrower, so that it can be fitted by sandwiching the printed circuit board and bonded well. .
【００６０】このようにして、両面ＣＯＢ構造が完成す
る。In this way, a double-sided COB structure is completed.
【００６１】この方法によれば、プリント基板の両面に
ベアＩＣチップ６が信頼性よく実装でき、プリント基板
１の縮小化及び高密度化を図ることができる。According to this method, the bare IC chips 6 can be reliably mounted on both sides of the printed circuit board, and the printed circuit board 1 can be made smaller and more dense.
【００６２】なお、前記実施例では、樹脂封止は両面の
ベアチップ搭載後に行うようにしたが、表面に搭載した
のち、一旦表面側の樹脂封止を行い、裏面側のチップを
搭載するようにしてもよい。In the above embodiment, resin sealing was performed after mounting bare chips on both sides, but after mounting on the front side, resin sealing was performed on the front side, and then the chip on the back side was mounted. You can.
【００６３】また、前記実施例では枠は両面に形成した
が、片面のみでもよい。Further, in the above embodiment, the frame was formed on both sides, but it may be formed on only one side.
【００６４】さらにまた、各面での実装はベアＩＣチッ
プ、他の実装部品の順に行ったが、その逆でもよいこと
はいうまでもない。Furthermore, although the mounting on each surface was carried out in the order of the bare IC chip and the other mounted components, it goes without saying that the reverse may be used.
【００６５】実施例２
次に、本発明の第２の実施例について説明する。図６（
ａ） および（ｂ） は全体平面図および断面図，図７
（ａ） および（ｂ） は要部拡大平面図および断面図
，図８は分解構造図，図９は斜視図である。Embodiment 2 Next, a second embodiment of the present invention will be described. Figure 6 (
a) and (b) are overall plan and cross-sectional views, Figure 7
(a) and (b) are an enlarged plan view and a sectional view of the main parts, FIG. 8 is an exploded structural view, and FIG. 9 is a perspective view.
【００６６】この半導体装置は、それぞれの金の配線パ
ターン４の形成された厚さ０．８ｍｍのプリント基板１
ａ，１ｂ表面にそれぞれ３こづつのベアＩＣチップ６を
搭載し、このベアＩＣチップと配線パターンとを接続す
るとともに、各ベアＩＣチップ６のまわりを樹脂封止し
て、２つの混成集積回路を形成し、これらのプリント基
板１ａ，１ｂの裏面側が相対向するように絶縁性の接着
部材２を介して貼着し、実施例１と同様に端部の領域Ｒ
の配線パターン４に接続するようにリードフレーム１０
を嵌合し、半田ディップして接続したものである。ここ
で金の配線パターン４は、表面を膜厚０．５μｍ の金
めっき層で被覆したものである。This semiconductor device consists of a printed circuit board 1 with a thickness of 0.8 mm on which each gold wiring pattern 4 is formed.
Three bare IC chips 6 are mounted on each of the surfaces of a and 1b, and the bare IC chips and wiring patterns are connected, and the surroundings of each bare IC chip 6 are sealed with resin to form two hybrid integrated circuits. These printed circuit boards 1a and 1b are pasted via an insulating adhesive member 2 so that their back sides face each other, and the edge area R is formed in the same way as in Example 1.
The lead frame 10 is connected to the wiring pattern 4 of
are fitted and connected by solder dipping. Here, the surface of the gold wiring pattern 4 is coated with a gold plating layer having a thickness of 0.5 μm.
【００６７】ここで１ａ，１ｂはプリント基板、２は両
プリント基板を接続するための絶縁性接着剤、３は金メ
ッキされたパタ―ンでありベアＩＣチップをダイボンデ
ィングするためのアイランド（ダイパッド）である。４
は金の配線パタ―ンである。６はベアＩＣチップであり
、銀ペ―スト５を介してアイランドにダイボンディング
される。このダイボンディングされたベアＩＣチップか
らプリント基板の配線パターン（ボンディングパッド）
４に、金ワイヤ７にてワイヤボンディングを行う。
８はダイボンディングされたベアＩＣチップとワイヤボ
ンディングされた金ワイヤの保護のための樹脂である。
１０は外部接続用のリ―ドフレ―ムであり、２枚のプリ
ント基板を挟持する。Here, 1a and 1b are printed circuit boards, 2 is an insulating adhesive for connecting both printed boards, and 3 is a gold-plated pattern, which is an island (die pad) for die-bonding a bare IC chip. It is. 4
is the gold wiring pattern. 6 is a bare IC chip, which is die-bonded to the island via silver paste 5. The wiring pattern (bonding pad) from this die-bonded bare IC chip to the printed circuit board
4, wire bonding is performed using gold wire 7. 8 is a resin for protecting the die-bonded bare IC chip and the wire-bonded gold wire. 10 is a lead frame for external connection, which sandwiches two printed circuit boards.
【００６８】次に、この半導体装置の製造方法について
説明する。Next, a method for manufacturing this semiconductor device will be explained.
【００６９】まず、両面に所定の配線パターン４の形成
されたプリント基板１を用意する。ついで、各プリント
基板１ａ，１ｂの表面のチップ搭載領域にベアＩＣチッ
プ６をシルバーペーストなどを用いて固着する（ダイボ
ンディング）。First, a printed circuit board 1 having a predetermined wiring pattern 4 formed on both sides is prepared. Next, the bare IC chip 6 is fixed to the chip mounting area on the surface of each printed circuit board 1a, 1b using silver paste or the like (die bonding).
【００７０】そして、実施例１に図２乃至図４に示した
方法でそれぞれに対しワイヤボンディングを行う。[0070] Then, wire bonding is performed on each of them by the method shown in FIGS. 2 to 4 in Example 1.
【００７１】このようにしてそれぞれ片面実装のなされ
た各プリント基板１ａ，１ｂの裏面側が向かい合うよう
に絶縁性接着剤を介して固着する。In this way, the printed circuit boards 1a and 1b, each mounted on one side, are fixed with an insulating adhesive so that their back surfaces face each other.
【００７２】そして最後に、プリント基板の１端部の領
域Ｒの配線パターン４に接続するようにリードフレーム
１０を嵌合し、半田ディップして接続する。Finally, the lead frame 10 is fitted so as to be connected to the wiring pattern 4 in the region R at one end of the printed circuit board, and the connection is made by dipping with solder.
【００７３】このリードフレームは実施例１で示したの
と同様に、４２アロイから構成され、先端が断面コの字
状をなすように形成され、他端をタイバーＴで一体的に
形成されており、プリント基板との接続後、タイバーＴ
を切除する。[0073] This lead frame is made of 42 alloy, as shown in Example 1, and the tip is formed to have a U-shaped cross section, and the other end is integrally formed with a tie bar T. After connecting with the printed circuit board, connect the tie bar T.
to remove.
【００７４】このようにして、擬両面ＣＯＢ構造が完成
する。In this way, a quasi-double-sided COB structure is completed.
【００７５】かかる構造をとることにより、複数個のベ
アＩＣチップを実装する場合でも両面実装を高密度に行
うことが可能になるため従来例に比較しかなりの小形化
をはかることが可能となる。[0075] By adopting such a structure, even when mounting a plurality of bare IC chips, double-sided mounting can be performed with high density, so it is possible to achieve considerable miniaturization compared to the conventional example. .
【００７６】また、通常の片面実装構造の半導体装置を
実装すれば良いため、実装方法を何等変更することなく
、容易に実装可能である。Furthermore, since it is sufficient to mount a semiconductor device having a normal single-sided mounting structure, it is possible to easily mount the semiconductor device without changing the mounting method in any way.
【００７７】なお、この実施例では、配線パターンはプ
リント基板の表面側にのみ形成したが、裏面側にも形成
しスルーホールを介して接続するようにしてもよく、こ
れにより回路設計に自由度が増し、高密度化に際しても
製造が容易で信頼性の高い半導体装置を得ることができ
る。In this example, the wiring pattern was formed only on the front side of the printed circuit board, but it may also be formed on the back side and connected via through holes, which increases the degree of freedom in circuit design. Therefore, a semiconductor device that is easy to manufacture and has high reliability even when the density is increased can be obtained.
【００７８】また、前記実施例ではリード端子１０は、
２枚のプリント基板を挾み込むようにして装着したが、
図１０に断面図を示すように、スルーホールＨを介して
表面側の配線パターンと接続するようにプリント基板の
裏面側にも配線パターン４ｓを形成し、この配線パター
ン４ｓに接続するようにリード端子１０を２枚のプリン
ト基板の間に挾み込むようにしても良い。Further, in the above embodiment, the lead terminal 10 is
I installed it by sandwiching two printed circuit boards, but
As shown in the cross-sectional view in FIG. 10, a wiring pattern 4s is also formed on the back side of the printed circuit board so as to be connected to the wiring pattern on the front side through the through hole H, and a lead is connected to the wiring pattern 4s. The terminal 10 may be sandwiched between two printed circuit boards.
【００７９】なお、この例では２枚のプリント基板を重
ねるようにしているため、基板の厚さは薄いほうが望ま
しく、また薄い基板を用いて多層構造にしても良いこと
は言うまでもない。[0079] In this example, two printed circuit boards are stacked one on top of the other, so it is desirable that the thickness of the substrate be thin, and it goes without saying that a multilayer structure may be formed using thin substrates.
【００８０】また、各実施例において、チップと配線パ
ターンとの間の接続はワイヤボンディングによって行う
ようにしたが、必ずしもワイヤボンディングを用いる必
要はなく、フリップチップ、ＴＡＢ方式などのワイヤレ
ス（ダイレクト）ボンディングを用いたものにも適用可
能である。Furthermore, in each embodiment, the connection between the chip and the wiring pattern was made by wire bonding, but it is not necessarily necessary to use wire bonding, and wireless (direct) bonding such as flip chip or TAB method may be used. It is also applicable to those using
【００８１】[0081]
【発明の効果】以上説明したように、本発明の第１では
、プリント基板の少なくとも一方の面に、部品の高さよ
り高い枠を取付け、両面に複数個のベアチップを実装し
た構造であるため、実装が容易でかつ小形化、高密度化
が可能となる。As explained above, the first aspect of the present invention has a structure in which a frame higher than the height of the component is attached to at least one side of the printed circuit board, and a plurality of bare chips are mounted on both sides. It is easy to implement, and allows for miniaturization and high density.
【００８２】本発明の第２の方法によれば、プリント基
板表面に、少なくとも１個のベアＩＣチップを搭載し、
前記プリント基板の配線パターンに結線したのち、プリ
ント基板の裏面にベアＩＣチップを搭載し結線するに先
立ち、この表面側に、樹脂封止用の枠を取付けるように
しているため、ボンディングステージに密着性よく装着
することができ、高精度で確実な実装を行うことができ
る。According to the second method of the present invention, at least one bare IC chip is mounted on the surface of the printed circuit board,
After wiring is connected to the wiring pattern of the printed circuit board, a bare IC chip is mounted on the back of the printed circuit board, and prior to wiring, a frame for resin sealing is attached to the front side of the printed circuit board, so that it is tightly attached to the bonding stage. It can be mounted easily and can be mounted with high precision and reliability.
【００８３】本発明の第３では、ベアＩＣチップを使用
して片面実装されたＣＯＢ構造の２枚の実装プリント基
板を用いて絶縁性の接着剤及びプレ―トを介し貼り合せ
疑似的な両面ＣＯＢ構造の混成集積回路としたため、大
幅な小形・高密度化を行うことが可能となる。In the third aspect of the present invention, two printed circuit boards of a COB structure mounted on one side using a bare IC chip are bonded together via an insulating adhesive and a plate to create a pseudo double-sided structure. Since it is a hybrid integrated circuit with a COB structure, it is possible to significantly reduce the size and increase the density.
【図１】本発明の第１の実施例の混成集積回路を示す図
。FIG. 1 is a diagram showing a hybrid integrated circuit according to a first embodiment of the present invention.
【図２】ワイヤボンディング工程を示す図。FIG. 2 is a diagram showing a wire bonding process.
【図３】ワイヤボンディング工程を示す図。FIG. 3 is a diagram showing a wire bonding process.
【図４】ワイヤボンディング工程を示す図。FIG. 4 is a diagram showing a wire bonding process.
【図５】本発明の第１の実施例に用いられるリードフレ
ームを示す図。FIG. 5 is a diagram showing a lead frame used in the first embodiment of the present invention.
【図６】本発明の第２の実施例の混成集積回路を示す図
。FIG. 6 is a diagram showing a hybrid integrated circuit according to a second embodiment of the present invention.
【図７】同混成集積回路の要部拡大図。FIG. 7 is an enlarged view of the main parts of the hybrid integrated circuit.
【図８】同分解構造図。FIG. 8 is an exploded structural diagram.
【図９】同斜視図[Fig. 9] Perspective view
【図１０】本発明の他の実施例を示す図。FIG. 10 is a diagram showing another embodiment of the present invention.
【図１１】従来例の混成集積回路を示す図。FIG. 11 is a diagram showing a conventional hybrid integrated circuit.
【図１２】従来例の混成集積回路を示す図。FIG. 12 is a diagram showing a conventional hybrid integrated circuit.
【図１３】従来例の混成集積回路を示す図。FIG. 13 is a diagram showing a conventional hybrid integrated circuit.
【図１４】従来例の混成集積回路を示す図。FIG. 14 is a diagram showing a conventional hybrid integrated circuit.
【図１５】従来例の混成集積回路を示す図。FIG. 15 is a diagram showing a conventional hybrid integrated circuit.
【図１６】従来例の混成集積回路を示す図。FIG. 16 is a diagram showing a conventional hybrid integrated circuit.
１ａ，１ｂ プリント基板
２ 絶縁性接着剤
３ ダイパッド
４，４ｓ 配線パターン
５ 銀ペ―スト
６ ベアＩＣチップ
７ 金ワイヤ
８ チップコ―ティング樹脂
９ 枠
１０ 外部接続用リ―ドフレ―ム
１２ キャピラリ―
１３ 超音波ホ―ン
１４ 電気ト―チ棒
１５ 押え治具
１７ ボンディングステ―ジ
１９ 圧着ボ―ル
２０ ベアＩＣチップの電極（ボンディングパッド）
２１ 金ボ―ル
２２ 下クランパ
３０ コンデンサ
３１ 抵抗
３２ ＳＯＰ
Ｔ タイバー1a, 1b Printed circuit board 2 Insulating adhesive 3 Die pads 4, 4s Wiring pattern 5 Silver paste 6 Bare IC chip 7 Gold wire 8 Chip coating resin 9 Frame 10 External connection lead frame 12 Capillary 13 Super Sonic horn 14 Electric torch rod 15 Holding jig 17 Bonding stage 19 Crimp ball 20 Bare IC chip electrode (bonding pad)
21 Gold ball 22 Lower clamper 30 Capacitor 31 Resistor 32 SOP T Tie bar
Claims (4)
されたプリント基板と、前記プリント基板表面に搭載さ
れ、前記配線パターンに接続された少なくとも１個の第
１のベアＩＣチップと、前記プリント基板裏面に搭載さ
れ、前記配線パターンに接続された少なくとも１個の第
２のベアＩＣチップと前記プリント基板の表面または裏
面の少なくとも一方に配設され、当該面に搭載されるベ
アＩＣチップの高さよりも高い樹脂封止用の枠とを具備
し、前記プリント基板の表面および裏面が樹脂封止され
ていることを特徴とする半導体装置。1. A printed circuit board having a wiring pattern formed on its front and back surfaces, at least one first bare IC chip mounted on the front surface of the printed circuit board and connected to the wiring pattern, and a back surface of the printed circuit board. at least one second bare IC chip mounted on the substrate and connected to the wiring pattern and arranged on at least one of the front surface or the back surface of the printed circuit board, and the height is higher than the height of the bare IC chip mounted on the surface. 1. A semiconductor device comprising: a high resin sealing frame; and the front and back surfaces of the printed circuit board are sealed with resin.
のベアＩＣチップを搭載し、前記プリント基板の配線パ
ターンに結線する第１の搭載工程と、プリント基板の裏
面に少なくとも１個のベアＩＣチップを搭載し、前記プ
リント基板の配線パターンに結線する第２の搭載工程と
、前記プリント基板の表面および裏面のベアＩＣチップ
を樹脂封止する樹脂封止工程とを含む半導体装置の実装
方法において、前記第２の搭載工程に先立ち、前記プリ
ント基板の表面側に、樹脂封止用の枠を取付ける工程を
含むようにしたことを特徴とする半導体装置の製造方法
。2. A first mounting step of mounting at least one bare IC chip on the surface of the printed circuit board and connecting it to the wiring pattern of the printed circuit board, and mounting at least one bare IC chip on the back surface of the printed circuit board. In the method for mounting a semiconductor device, the semiconductor device mounting method includes a second mounting step of mounting and connecting to a wiring pattern of the printed circuit board, and a resin sealing step of resin-sealing bare IC chips on the front and back surfaces of the printed circuit board. A method for manufacturing a semiconductor device, comprising the step of attaching a frame for resin sealing to the front side of the printed circuit board prior to the second mounting step.
のプリント基板表面に少なくとも１つのベアＩＣチップ
を搭載し、前記ベアＩＣチップと前記第１の配線パター
ンとを接続するとともに、前記ベアＩＣチップのまわり
を樹脂封止してなる第１の混成集積回路と、第２の配線
パターンの形成された第２のプリント基板表面に少なく
とも１つのベアＩＣチップを搭載し、前記ベアＩＣチッ
プと前記第２の配線パターンとを接続するとともに、前
記ベアＩＣチップのまわりを樹脂封止してなる第２の混
成集積回路とを具備し、前記第１および第２のプリント
基板の裏面側が相対向するように絶縁性の接着部材を介
して貼着せしめられていることを特徴とする半導体装置
。Claim 3: A first wiring pattern on which a first wiring pattern is formed.
A first hybrid integration comprising: mounting at least one bare IC chip on the surface of a printed circuit board, connecting the bare IC chip and the first wiring pattern, and sealing the bare IC chip with resin; At least one bare IC chip is mounted on the surface of a second printed circuit board on which a circuit and a second wiring pattern are formed, the bare IC chip and the second wiring pattern are connected, and the bare IC chip is connected to the second wiring pattern. and a second hybrid integrated circuit whose periphery is sealed with resin, and the first and second printed circuit boards are attached via an insulating adhesive member so that their back sides face each other. A semiconductor device characterized by:
その端部で、両者をはさみ込むように設置され、第１お
よび第２の配線パターンとの接続のなされたリ―ド端子
を具備したことを特徴とする請求項（３） 記載の半導
体装置。4. The first and second printed circuit boards are provided at their ends with lead terminals installed to sandwich them and connected to the first and second wiring patterns. The semiconductor device according to claim 3, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134423A JP2974819B2 (en) | 1991-06-05 | 1991-06-05 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134423A JP2974819B2 (en) | 1991-06-05 | 1991-06-05 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04359457A true JPH04359457A (en) | 1992-12-11 |
| JP2974819B2 JP2974819B2 (en) | 1999-11-10 |
Family
ID=15128040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3134423A Expired - Fee Related JP2974819B2 (en) | 1991-06-05 | 1991-06-05 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2974819B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213516A (en) * | 1995-01-31 | 1996-08-20 | Nec Corp | Semiconductor device and manufacture thereof |
| US5784264A (en) * | 1994-11-28 | 1998-07-21 | Nec Corporation | MCM (Multi Chip Module) carrier with external connection teminals BGA (Ball Grid Array) type matrix array form |
| KR100505391B1 (en) * | 1997-12-16 | 2005-11-14 | 주식회사 하이닉스반도체 | Semiconductor and manufacture method |
-
1991
- 1991-06-05 JP JP3134423A patent/JP2974819B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5784264A (en) * | 1994-11-28 | 1998-07-21 | Nec Corporation | MCM (Multi Chip Module) carrier with external connection teminals BGA (Ball Grid Array) type matrix array form |
| JPH08213516A (en) * | 1995-01-31 | 1996-08-20 | Nec Corp | Semiconductor device and manufacture thereof |
| KR100505391B1 (en) * | 1997-12-16 | 2005-11-14 | 주식회사 하이닉스반도체 | Semiconductor and manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2974819B2 (en) | 1999-11-10 |
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