JPS6148928A - Hybrid ic circuit - Google Patents
Hybrid ic circuitInfo
- Publication number
- JPS6148928A JPS6148928A JP59170838A JP17083884A JPS6148928A JP S6148928 A JPS6148928 A JP S6148928A JP 59170838 A JP59170838 A JP 59170838A JP 17083884 A JP17083884 A JP 17083884A JP S6148928 A JPS6148928 A JP S6148928A
- Authority
- JP
- Japan
- Prior art keywords
- printed
- printed pattern
- hole
- pattern
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はハイブリッド集積回路に係り、特に軽量、薄形
化を図ったハイブリッド集積回路に関する〔発明の背景
〕
従来のハイブリッド集積回路として、例えば、第１図に
示すものがあり、所定の大きさのセラミック基板１０上
に回路図に従って、その接続線に該当するパターン（金
属箔）を配設し、各パターン間にモノリシックＩＣ１２
、コンデンサ１４及び印刷抵抗１６等をボンディングに
よって接続した構成となっている。外部回路との接続は
図示せぬビンによってなされ、セラミック基板１０の側
部に突出して設けられる。各素子を固定して振動を防止
し且つ絶縁を維持するために、第２図に示すように素子
装着面にエポキシ樹脂１８等で被覆される。更に、必要
に応じてパッケージが被着される。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a hybrid integrated circuit, and particularly relates to a hybrid integrated circuit that is lightweight and thin. [Background of the Invention] As a conventional hybrid integrated circuit, for example, 1, a pattern (metal foil) corresponding to the connection line is arranged on a ceramic substrate 10 of a predetermined size according to the circuit diagram, and a monolithic IC 12 is placed between each pattern.
, a capacitor 14, a printed resistor 16, etc. are connected by bonding. Connection with an external circuit is made by a not-shown vial, which is provided protruding from the side of the ceramic substrate 10. In order to fix each element, prevent vibration, and maintain insulation, the element mounting surface is coated with epoxy resin 18 or the like, as shown in FIG. Furthermore, a package is applied as required.
しかし、従来のハイブリッド集積回路によれば、厚みを
有する基板上に素子を載置し、ワイヤ１７をボンディン
グ後更にその上方から樹脂１８によって固定する構造が
とられているため、全体の厚みが大きくなり、狭いスペ
ース例えば内視鏡挿入部内に組込むことができない不都
合がある。However, according to the conventional hybrid integrated circuit, the device is mounted on a thick substrate, and the wire 17 is bonded and then fixed with resin 18 from above, so the overall thickness is large. Therefore, there is a disadvantage that it cannot be installed in a narrow space, for example, in an endoscope insertion section.
本発明は、このような事情に鑑みてなされたもので、全
体の厚みを薄くできるようにしたハイブリッド集積回路
を提案することを目的としている〔発明の概要〕
本発明は、前記目的を達成するために、表面に結線用の
パターンが設けられた素子を、所定のプリントパターン
が施されたサブストレートに設置し、装着した素子の厚
み相当の厚みを有すると共に各素子の上面が露出可能な
開口を有すると共にスルーホールが所定位置に設けられ
たセラミック等の絶縁材を介挿して、該絶縁材及び各素
子の上面にプリントパターンが下面に配設されると共に
該パターンに接続されたスルーホールを存するフィルム
を設置し、スルーホール内にハンダ又はコンダクティブ
エポキシ樹脂を流し込むようにしたものである。The present invention has been made in view of the above circumstances, and aims to propose a hybrid integrated circuit that can reduce the overall thickness. [Summary of the Invention] The present invention achieves the above-mentioned object. In order to do this, an element with a wiring pattern on its surface is installed on a substrate with a predetermined printed pattern, and an opening with a thickness equivalent to the thickness of the mounted element and through which the top surface of each element can be exposed is installed. An insulating material such as ceramic having a through hole provided at a predetermined position is inserted, and a printed pattern is disposed on the lower surface of the insulating material and the upper surface of each element, and the through hole connected to the pattern is inserted. The existing film is installed, and solder or conductive epoxy resin is poured into the through hole.
以下、添付図面に従って本発明に係るハイブリッド集積
回路の好ましい実施例を詳説する。Hereinafter, preferred embodiments of a hybrid integrated circuit according to the present invention will be described in detail with reference to the accompanying drawings.
第３図は本発明の一実施例を示す組立斜視図である。FIG. 3 is an assembled perspective view showing an embodiment of the present invention.
素子２０の各々は、その種類を問わず同一高さに設定し
、各々の表面には結線用のプリントパターン２２が設け
られる。これら素子２０の底面を接着剤等によって所定
位置に固定設置するセラミック等の材料を用いたサブス
トレート２４の表面には、素子２０を含んで所望の回路
を構成するためのプリントパターン２６が予め設けられ
ている。このサブストレート２４のプリント面には、素
子２０の高さと同一の厚みを有し、サブストレート２４
に装着した素子２０の表面を露出させる開口２８及びプ
リントパターン２６と素子２０のプリントパターン２６
を電気的に接続する為のスルーホール３２の設けられた
セラミック等による介挿板３０が、接着剤等を用いて被
着される。更に、介挿板３０及び素子２０のプリントパ
ターン２２の上面には、スルーホール３２に対応するス
ルーホール３４、及び該スルーホール３４を囲み、素子
２０のプリントパターン２２に接触して電気的に接続さ
れ翼プリントパターン３６が下面に形成されたフィルム
４０が接着剤等を用いて貼り合わせられる。Each of the elements 20 is set at the same height regardless of its type, and a printed pattern 22 for connection is provided on each surface. A printed pattern 26 for configuring a desired circuit including the elements 20 is provided in advance on the surface of a substrate 24 made of a material such as ceramic, on which the bottom surface of the elements 20 is fixed in a predetermined position with an adhesive or the like. It is being The printed surface of this substrate 24 has the same thickness as the height of the element 20, and
The opening 28 and printed pattern 26 for exposing the surface of the element 20 attached to the element 20 and the printed pattern 26 of the element 20
An intervening plate 30 made of ceramic or the like and provided with through holes 32 for electrical connection is attached using an adhesive or the like. Further, on the upper surface of the insertion plate 30 and the printed pattern 22 of the element 20, there is a through hole 34 corresponding to the through hole 32, and a hole surrounding the through hole 34 and in contact with the printed pattern 22 of the element 20 for electrical connection. A film 40 having a wing print pattern 36 formed on its lower surface is bonded together using an adhesive or the like.
以上の構成において、その組立方法を説明すると、先ず
、所望の回路構成に従って表面にプリントパターン２６
が形成されたサブストレート２４のパターン面の所定の
位置に所定の素子２０を接着剤等を用いて固定する。つ
いで方向を合わせて、素子２０の表面のプリントパター
ン２２が開口２８より露出するように介挿板３０を、サ
ブストレート２４のプリント面に重ね合せる。この重ね
合せ面に予め接着剤が塗付されているため、両者は固着
される。更に、内面に接着剤のめ付されたスルーホール
３４をスルーホール３２に位置合せをして介挿板３０の
表面にフィルム４０を接着し、一体化されたハイブリッ
ド回路の厚み方向の両側から所定の圧力を加えて、各部
材を密着させる。こののち第４図に示すようにスルーホ
ール３４からハンダ５０（或いはコンダクティブエポキ
シ樹脂）を流し込んで、プリントパターン２６と３６を
電気的に接続する。このスルーホール３４及び３２への
ハンダ流し込みによって、従来のワイヤボンディングに
相当する作業を行なったことになる。以上の処理により
完成したハイブリッド回路は第４図の如くとなり、厚み
を薄くできるばかりか、樹脂による盛り付けが不要にな
る。特に、本発明は装置や機器と一体的に組込まれるカ
スタムＩＣに適している。To explain how to assemble the above configuration, first, the printed pattern 26 is printed on the surface according to the desired circuit configuration.
A predetermined element 20 is fixed at a predetermined position on the patterned surface of the substrate 24 using an adhesive or the like. Then, the inserting plate 30 is superimposed on the printed surface of the substrate 24 so that the printed pattern 22 on the surface of the element 20 is exposed through the opening 28 with the directions aligned. Since the overlapping surfaces are coated with adhesive in advance, the two are fixed. Furthermore, the through holes 34 fitted with adhesive on the inner surface are aligned with the through holes 32, and the film 40 is adhered to the surface of the insertion plate 30. Apply pressure to bring each member into close contact. Thereafter, as shown in FIG. 4, solder 50 (or conductive epoxy resin) is poured through the through hole 34 to electrically connect the printed patterns 26 and 36. By pouring the solder into the through holes 34 and 32, an operation equivalent to conventional wire bonding is performed. The hybrid circuit completed by the above processing becomes as shown in Fig. 4, which not only allows the thickness to be reduced, but also eliminates the need for mounting with resin. In particular, the present invention is suitable for custom ICs that are integrated into devices and equipment.
以上説明したように本発明に係るハイブリッド集積回路
によれば、表面にプリントパターンが形成された素子の
両側にプリントパターン面を配設し、両パターン面間に
配設したスルーホールによって回路を構成するようにし
たため、全体の厚みを小さくし、小型化を図ることがで
きる。As explained above, according to the hybrid integrated circuit according to the present invention, printed pattern surfaces are arranged on both sides of an element having a printed pattern formed on the surface, and a circuit is configured by a through hole arranged between both pattern surfaces. As a result, the overall thickness can be reduced and downsizing can be achieved.
第１図は従来のハイブリッド集積回路を示す斜視図、第
２図は該回路の断面図、第３図は本発明の一実施例を示
す組立斜視図、第４図は第３図の実施例の断面図である
。
２０・・・素子、 ２２．２６．３６・・・プリントパ
ターン、 ２４・・・サブストレート、 ２８・・
・開口、 ３０・・・介’ｔｒ＋Ｆｉ、３２．３４・・
・スルーホール、 ４０・・・フィルム、 ５０・・
・ハンダ。FIG. 1 is a perspective view showing a conventional hybrid integrated circuit, FIG. 2 is a sectional view of the circuit, FIG. 3 is an assembled perspective view showing an embodiment of the present invention, and FIG. 4 is an embodiment of the embodiment shown in FIG. FIG. 20...Element, 22.26.36...Print pattern, 24...Substrate, 28...
・Opening, 30...Interval+Fi, 32.34...
・Through hole, 40...Film, 50...
・Solder.
Claims (1)
成された基材と、統一された高さを有し前記基材のプリ
ント面の所定位置に固定設置されると共に表面にプリン
トパターンが設けられた素子と、該素子の高さと同一の
厚み及び前記素子のプリントパターン面が露出する開口
を有すると共に該プリントパターンに接続される第１の
スルーホールが設けられて前記基材に被着される介挿板
と、前記素子のプリントパターンに接触するプリントパ
ターン及び前記第１のスルーホールに対応する第２のス
ルーホールが設けられて前記素子の表面及び前記介挿板
の表面に設置されるフィルムと、前記第１のスルーホー
ルと前記第２のスルーホール内に流入されて各パターン
を電気的に接続する接続部材とを設けたことを特徴とす
るハイブリッド集積回路。(1) A base material on which a printed pattern corresponding to a desired circuit is formed on one side, a base material having a uniform height, fixedly installed at a predetermined position on the printed surface of the base material, and a printed pattern provided on the surface. a first through-hole connected to the printed pattern, the element having the same thickness as the height of the element, and an opening through which a printed pattern surface of the element is exposed, and is attached to the base material. a second through hole corresponding to the first through hole and a printed pattern that contacts the printed pattern of the element, and is installed on the surface of the element and the surface of the insertion plate. 1. A hybrid integrated circuit comprising: a film; and a connecting member that flows into the first through hole and the second through hole to electrically connect each pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59170838A JPS6148928A (en) | 1984-08-16 | 1984-08-16 | Hybrid ic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59170838A JPS6148928A (en) | 1984-08-16 | 1984-08-16 | Hybrid ic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6148928A true JPS6148928A (en) | 1986-03-10 |
| JPH0451064B2 JPH0451064B2 (en) | 1992-08-18 |
Family
ID=15912264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59170838A Granted JPS6148928A (en) | 1984-08-16 | 1984-08-16 | Hybrid ic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148928A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01156582U (en) * | 1988-04-20 | 1989-10-27 | ||
| US5552326A (en) * | 1995-03-01 | 1996-09-03 | Texas Instruments Incorporated | Method for forming electrical contact to the optical coating of an infrared detector using conductive epoxy |
| US5557149A (en) * | 1994-05-11 | 1996-09-17 | Chipscale, Inc. | Semiconductor fabrication with contact processing for wrap-around flange interface |
| JP2009197813A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197815A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197810A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197812A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197811A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
-
1984
- 1984-08-16 JP JP59170838A patent/JPS6148928A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01156582U (en) * | 1988-04-20 | 1989-10-27 | ||
| US5557149A (en) * | 1994-05-11 | 1996-09-17 | Chipscale, Inc. | Semiconductor fabrication with contact processing for wrap-around flange interface |
| US5656547A (en) * | 1994-05-11 | 1997-08-12 | Chipscale, Inc. | Method for making a leadless surface mounted device with wrap-around flange interface contacts |
| US5552326A (en) * | 1995-03-01 | 1996-09-03 | Texas Instruments Incorporated | Method for forming electrical contact to the optical coating of an infrared detector using conductive epoxy |
| JP2009197813A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197815A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197810A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197812A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
| JP2009197811A (en) * | 2009-06-11 | 2009-09-03 | Yamaha Motor Co Ltd | Engine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0451064B2 (en) | 1992-08-18 |
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| LAPS | Cancellation because of no payment of annual fees |