JPS60202984A - Hybrid integratd circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a hybrid integrated circuit using chip electronic components, and particularly to a hybrid integrated circuit that can be highly integrated.

Conventional configuration and its problems Figure 1 shows a flat package IC as a circuit component.
(hereinafter simply referred to as an IC) and a chip resistor, and shows an example of a hybrid integrated circuit. In the figure, R1-R3 are resistors, and IC1 is a semiconductor IC. FIG. 2 shows a chip resistor as an example of a chip electronic component. In the chip resistors R1 to R6, a resistor 2a3 and an electrode 2a1 are formed on an insulating substrate 2a2 by printing or vapor deposition.

3 and 4 are examples of hybrid integrated circuits constructed in a conventional manner. FIG. 3 is a top view of the wiring board S1, which is a base for configuring a hybrid integrated circuit on which chip electronic components are mounted, and FIG. 4 is a top view on which chip electronic components including a flat package IC are mounted. During actual assembly, chip electronic components are fixed to specified positions on the wiring board S using adhesive or adhesive material, and then the chip electronic components are fixed by a method such as dipping this board into a solder bath. Each electrode is electrically connected to a corresponding wiring conductor portion.

In such a conventional example, a circuit is configured through a wiring conductor placed on the insulating substrate S1, and a large electrode is required to reliably connect the chip electronic component to the electrode on the conductor. , and to prevent solder bridges during soldering, there was a limit to high-density mounting of chip components.

OBJECTS OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit including chip components, particularly flat package ICs, which can be mounted at high density.

Structure of the Invention This invention comprises a first chip electronic component layer on which a chip resistor and a chip capacitor are firmly mounted on an insulating substrate having no wiring conductor, and a mini-molded transistor and a flat package IC mounted on the first chip electronic component layer. 2nd model equipped with etc.
It consists of a chip electronic component layer, and the electrode portions of the chip electronic component constituting the first layer and the second layer are arranged so as to be in close contact with each other, and the respective electrodes are connected by a conductive material.

DESCRIPTION OF EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. 5 to 7. FIG. 6 shows an insulating substrate S1 serving as a base, and does not have a conductor layer for wiring. Figure 6 is a top view showing the arrangement of electronic components, including chip resistors R1, R2, R3 and jumper resistor 1.
Each of the chip components of the first chip electronic component layer, which also includes chips 1 to I8, is fixedly mounted on an insulating substrate S using an adhesive or the like.

A mini-mold transistor and a flat package IC are mounted on the first chip electronic component layer, and in the illustrated example, IC1 is mounted to form a second chip electronic component layer.

Jumper element 11 used in the first chip electronic component layer
~I8 has the same shape as the chip resistor shown in FIG. 2, and has a resistance value of approximately OΩ. The electrode parts of the electronic components constituting the first chip electronic layer are arranged so as to be in close contact with each other according to the circuit diagram shown in FIG. The electrode part of is also the first
The layer is arranged so as to be in close contact with the electrodes of the chip electronic component.

Thereafter, a conductive material 4 such as solder paste or conductive paste is applied to each electrode B portion, and heat treatment is performed to electrically connect the electrode portions that are in close contact with each other. FIG. 7 shows a perspective view of this embodiment in which the electrodes of a plurality of chip electronic components are arranged in close contact with each other and a second chip component layer is mounted on the first chip electronic component layer. . In the embodiment of the present invention, one end of the resistor R1, the resistor R
3, one end of jumper element 14. Although the connection of one end of T8 is not shown, these electrodes are all joints with external connection lead parts, and wire bonding and soldering of metal wires are possible, but the gist of the present invention is Therefore, I will not specifically discuss it here.

Effects of the Invention Because of this mounting structure, the present invention eliminates the need for electrical connections between chip electronic components using wiring conductors on the base insulating substrate, and allows the electrodes to be arranged so as to be in close contact with each other. , and because the chip electronic components are three-dimensionally arranged in the first layer and the second layer, it is essentially highly integrated. Further, there is no wiring pattern to the insulating substrate S1, and the design time is greatly shortened.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a hybrid integrated circuit, Figure 2 is a perspective view of a TEP resistor, Figure 3 is a top view of a wiring conductor on a conventional board, Figure 4 is a top view of its mounting state, and Figure 5 is a diagram of the main board. A top view of an insulating substrate used in one embodiment of the invention, FIG. 6 is a top view showing a state in which the invention is mounted, and FIG. 7 is a perspective view thereof. 2a1... Electrode, 2a2... Ceramic base, 2a3... Resistor, 4...
Conductive material, R1-R3...Resistance, ■1 to ■8
...Jumper element, IC1...Flat package IC, Sl...Insulating substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 4 Figure 5 Figure 6 Figure 7

Claims (2)

[Claims] (1) An insulating substrate having no conductor portion for wiring, a first chip electronic component layer firmly mounted on the insulating substrate, and a second chip electronic component layer mounted on the first step electronic component layer. A hybrid integrated circuit characterized by: (2) The electrode portions of the electronic components constituting the first layer and the second layer are arranged so as to be in close contact with each other, and each of the electrode portions is connected by a conductive material such as solder or conductive paste. A hybrid integrated circuit according to claim 1, characterized in that: