JPH0714938A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0714938A JPH0714938A JP5143731A JP14373193A JPH0714938A JP H0714938 A JPH0714938 A JP H0714938A JP 5143731 A JP5143731 A JP 5143731A JP 14373193 A JP14373193 A JP 14373193A JP H0714938 A JPH0714938 A JP H0714938A
- Authority
- JP
- Japan
- Prior art keywords
- power
- circuit
- board
- substrate
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に関
し、特にパワー回路部と小信号系回路部とが１チップ化
さたてパワーモノＩＣを実装した混成集積回路装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which a power circuit unit and a small signal system circuit unit are integrated into one chip and a power mono IC is mounted.
【０００２】[0002]
【従来の技術】従来、パワー系の半導体素子を搭載した
混成集積回路は図２に示す如く、表面を陽極酸化したア
ルミニウム等の絶縁基板（１１）と、前記基板（１１）
上にエポキシ樹脂等の絶縁層を介して任意の形状に設け
られた導電路（１２）と、前記導電路（１２）上に半田
付けされたＣｕ材等よりなるヒートシンク（１３）とそ
のヒートシンク（１３）上に固着されたパワートランジ
スタ等のパワー系の素子（１４）と、そのパワー素子
（１４）と周辺の導電路（１２）とを接続するボンディ
ングワイヤ線（１５）とで構成され、所望出力の混成集
積回路が実現されている。2. Description of the Related Art Conventionally, as shown in FIG. 2, a hybrid integrated circuit mounted with a power semiconductor element has an insulating substrate (11) such as aluminum whose surface is anodized, and the substrate (11).
A conductive path (12) provided on the conductive path (12) in an arbitrary shape via an insulating layer such as an epoxy resin, a heat sink (13) made of a Cu material or the like soldered on the conductive path (12), and its heat sink ( 13) a power system element (14) such as a power transistor fixed on the bonding element, and a bonding wire line (15) connecting the power element (14) and the peripheral conductive path (12). Output hybrid integrated circuits have been implemented.
【０００３】更に、従来の混成集積回路のヒートシンク
上に搭載されるパワー素子は、パワー段のみを構成する
回路が集積化されており、そのパワー素子を駆動させる
ドライバー用の小信号系の駆動用の回路素子は図２では
示されてないがパワー素子の近傍の導電路上に接続され
両者の接続が行われている。Further, in the power element mounted on the heat sink of the conventional hybrid integrated circuit, a circuit constituting only the power stage is integrated, and for driving a small signal system for a driver for driving the power element. Although not shown in FIG. 2, the circuit element is connected to a conductive path in the vicinity of the power element to connect them.
【０００４】[0004]
【発明が解決しようとする課題】従って、従来の混成集
積回路ではパワー素子とそのパワー素子を駆動させる小
信号素子とが夫々別に搭載されているため約１０Ａ以上
の大出力を有するパワー用の混成集積回路が実現でき
る。しかし、最近、パワー部とそのパワー部を駆動させ
る小信号部とが１チップ化された（例えば高耐圧用のＭ
ＯＳＦＥＴ等）ＬＳＩ素子が出現している。かかる素子
のパワー出力は前述した従来の混成集積回路の如き、大
出力ではなく約１〜１０Ａ位の大きさの出力である。Therefore, in the conventional hybrid integrated circuit, the power element and the small signal element for driving the power element are separately mounted, so that a hybrid for power having a large output of about 10 A or more is provided. An integrated circuit can be realized. However, recently, the power section and the small signal section for driving the power section have been integrated into one chip (for example, M for high breakdown voltage).
LSI elements such as OSFETs have appeared. The power output of such an element is not a large output as in the conventional hybrid integrated circuit described above, but an output of about 1 to 10 A.
【０００５】ところが、放熱性を考慮するとヒートシン
クの厚みは最低でも１ｍｍ以上の厚みが必要であり、ヒ
ートシンクと導電路間に界面差が生じ、パワー部の電極
と導電路とを接続する約２００μ径の太いＡｌワイヤ線
はボンディング接続できるものの、小信号部の電極と導
電路とを接続する約４０μ径の細いＡｌワイヤ線はボン
ディング接続が行えず、パワー部と小信号部とを備え
た、いわゆるパワーモノＩＣを従来の混成集積回路では
実装することができないという問題がある。However, in consideration of heat dissipation, the thickness of the heat sink needs to be at least 1 mm or more, and an interface difference occurs between the heat sink and the conductive path, and a diameter of about 200 μm connecting the electrode of the power section and the conductive path. Although the thick Al wire wire can be connected by bonding, the thin Al wire wire having a diameter of about 40 μm that connects the electrode of the small signal portion and the conductive path cannot be connected by bonding, and is provided with a power portion and a small signal portion. There is a problem that the power mono IC cannot be mounted by the conventional hybrid integrated circuit.
【０００６】この発明は、上述した課題に鑑みてなされ
たものであり、この発明の目的は、パワー回路部とその
パワー回路部を駆動させる小信号系回路とがモノＩＣ化
された、いわゆるパワーモノＩＣを搭載できる混成集積
回路装置を提供することにある。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is a so-called power in which a power circuit section and a small signal system circuit for driving the power circuit section are integrated into a mono IC. It is to provide a hybrid integrated circuit device capable of mounting a mono IC.
【０００７】[0007]
【課題を解決するための手段】上述した課題を解決し、
目的を達成するため、この発明に係わる混成集積回路装
置は、金属基板上に、回路パターンが形成され、且つ、
少なくとも１つの開口部を有した回路基板が貼着され、
開口部により露出された金属基板上にパワー半導体チッ
プを固着する。[Means for Solving the Problems]
To achieve the object, a hybrid integrated circuit device according to the present invention has a circuit pattern formed on a metal substrate, and
A circuit board having at least one opening is attached,
The power semiconductor chip is fixed on the metal substrate exposed by the opening.
【０００８】[0008]
【作用】以上のように構成される混成集積回路において
は、従来の構造では実装不可能であった。パワー回路部
とそのパワー回路部を駆動させる小信号系回路とが１チ
ップ化されたパワーモノ型のパワー半導体素子を固着実
装することができる。即ち、細線（約３０μ〜４０μ）
と太線（約２００μ〜３００μ）とのボンディングワイ
ヤ接続を必要とするパワーモノ型の半導体素子を固着実
装することができる。In the hybrid integrated circuit configured as described above, it is impossible to implement the conventional structure. It is possible to fix and mount a power mono type power semiconductor element in which the power circuit unit and the small signal system circuit for driving the power circuit unit are integrated into one chip. That is, fine wire (about 30μ-40μ)
It is possible to fix and mount a power mono type semiconductor element that requires bonding wire connection between a thick wire (about 200 μ to 300 μ) and a bonding wire.
【０００９】[0009]
【実施例】以下に、図１に示した実施例に基づいて本発
明を説明する。本発明の混成集積回路装置は、図１に示
す如く、金属基板（１）と、その基板（１）上に貼着さ
れる開口部（３）を有した回路基板（２）と、開口部
（３）により露出された基板（１）上に実装されたパワ
ー半導体素子（４）とから構成される。The present invention will be described below based on the embodiment shown in FIG. As shown in FIG. 1, the hybrid integrated circuit device of the present invention includes a metal substrate (1), a circuit board (2) having an opening (3) attached to the substrate (1), and an opening. It is composed of a power semiconductor element (4) mounted on the substrate (1) exposed by (3).
【００１０】金属基板（１）は、アルミニウムあるいは
銅をベースにしたものが用いられ、ここではアルミニウ
ム基板を用いて説明する。その基板（１）の表面には表
面コートとして酸化アルミニウム膜が設けられている。
基板（１）の一主面上には、基板（１）と略同一サイズ
の回路基板（２）が貼着される。回路基板（２）は、例
えば、厚膜３５μｍのエポキシ樹脂、あるいはポリイミ
ド樹脂と厚膜３５μｍの銅箔とのクラッド材が用いら
れ、そのクラッド材の所定位置には開口部（３）が設け
られている。この開口部（３）は、後述するパワー半導
体素子を実装するために設けられたものである。すなわ
ち、かかる回路基板（２）を基板（１）上に貼着する
と、上述した開口部（３）によって基板（１）の表面が
露出され、この露出された基板（１）上にパワー半導体
素子（４）が実装される。As the metal substrate (1), one based on aluminum or copper is used, and an aluminum substrate will be used for explanation here. An aluminum oxide film is provided as a surface coat on the surface of the substrate (1).
A circuit board (2) having substantially the same size as the board (1) is attached to one main surface of the board (1). For the circuit board (2), for example, a clad material of an epoxy resin or a polyimide resin having a thick film of 35 μm and a copper foil of a thick film of 35 μm is used, and an opening (3) is provided at a predetermined position of the clad material. ing. The opening (3) is provided for mounting a power semiconductor element described later. That is, when the circuit board (2) is attached onto the board (1), the surface of the board (1) is exposed by the above-mentioned opening (3), and the power semiconductor element is exposed on the exposed board (1). (4) is implemented.
【００１１】回路基板（２）の銅箔は基板（１）上に貼
着される前あるいはその後に所望形状にエッチングされ
所望形状の導電路（５）が形成される。ところで、開口
部（３）によって露出される基板（１）上には、あらか
じめニッケルメッキ処理が施されたニッケル層が形成さ
れ、さらにそのニッケル層上に半田クリームが印刷され
たパッド（７）が形成されている。このパッド（７）上
に実装される素子（４）の電位はフローディング状態に
あるために、パッド（７）は島状に独立して形成されて
いる。The copper foil of the circuit board (2) is etched into a desired shape before or after being attached to the board (1) to form a conductive path (5) having a desired shape. By the way, on the substrate (1) exposed by the opening (3), a nickel layer which has been subjected to nickel plating treatment in advance is formed, and a pad (7) having solder cream printed on the nickel layer is further formed. Has been formed. Since the electric potential of the element (4) mounted on the pad (7) is in a floating state, the pad (7) is independently formed in an island shape.
【００１２】基板（１）上に回路基板（２）を貼着した
後、両基板（１）および（２）上に回路素子が実装され
る。すなわち、基板（１）上にはパワー半導体素子
（４）のみが実装され、回路基板（２）上にはチップ抵
抗、チップコンデンサー等の複数の回路素子が半田リフ
リーおよびＡｇペースト工程により、実装される。本実
施例で使用されるパワー半導体素子（４）はパワートラ
ンジスタの如き、パワー回路のみが形成されるものでは
なく、パワー回路部とそのパワー回路部を駆動させる小
信号系回路とがモノＩＣ化（１チップ化）された、例え
ば高耐圧用ＭＯＳＦＥＴ等のパワーモノＩＣが使用され
る。かかる素子（４）を回路基板（２）上の導電路
（５）と接続する場合二種類のワイヤ線（６）（７）を
必要とする。即ち、パワー回路部領域に形成された電極
は約２００μ〜５００μ径の比較的太いＡｌワイヤ線
（６）が用いられて回路基板（２）上の導電路（５）と
接続され、小信号回路領域に形成された電極は約２０μ
〜５０μ径の比較的細いＡｌ等のワイヤ線（７）が用い
られて導電路（５）と接続される。After sticking the circuit board (2) on the board (1), circuit elements are mounted on both boards (1) and (2). That is, only the power semiconductor element (4) is mounted on the board (1), and a plurality of circuit elements such as chip resistors and chip capacitors are mounted on the circuit board (2) by solder refree and Ag paste processes. It The power semiconductor element (4) used in the present embodiment is not one in which only a power circuit such as a power transistor is formed, but a power IC and a small signal system circuit for driving the power IC are integrated into a mono IC. A power mono IC, such as a high breakdown voltage MOSFET, which is (made into one chip) is used. When connecting such an element (4) with the conductive path (5) on the circuit board (2), two types of wire wires (6) and (7) are required. That is, the electrodes formed in the power circuit area are connected to the conductive paths (5) on the circuit board (2) by using a relatively thick Al wire wire (6) having a diameter of about 200 μ to 500 μ, and the small signal circuit is connected. The electrode formed in the area is about 20μ
A relatively thin wire wire (7) of Al or the like having a diameter of ˜50 μm is used to connect with the conductive path (5).
【００１３】かかる、本発明に依れば、パワー素子
（４）のみを基板（１）上に直接実装し、周辺回路を基
板（１）上に貼着する回路基板（２）に実装する構造で
あるために、パワー素子（４）と回路基板（２）の段差
を抑制でき、従来実装できなかったパワーモノＩＣを実
装することが可能となる。According to the present invention, the structure in which only the power element (4) is directly mounted on the substrate (1) and the peripheral circuit is mounted on the circuit board (2) attached to the substrate (1). Therefore, the step difference between the power element (4) and the circuit board (2) can be suppressed, and it becomes possible to mount a power mono IC which could not be mounted conventionally.
【００１４】[0014]
【発明の効果】以上に詳述した如く、本発明に依れば、
従来構造では実装困難であったパワー回路部とそのパワ
ー回路部を駆動させる小信号回路とが１チップ化され
た、いわゆるパワーモノＩＣを放熱特性をあまり低下さ
せることなく実装することが可能とできる。As described in detail above, according to the present invention,
It is possible to mount a so-called power mono IC in which a power circuit section and a small signal circuit for driving the power circuit section, which are difficult to be mounted in the conventional structure, are integrated into one chip without significantly lowering heat dissipation characteristics. .
【図１】本発明の実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】従来例を示す断面図である。FIG. 2 is a sectional view showing a conventional example.
（１） 金属基板 （２） 回路基板 （３） 開口部 （４） パワー半導体素子 （５） 導電路 (1) Metal board (2) Circuit board (3) Opening (4) Power semiconductor element (5) Conductive path
Claims (2)
れ、且つ、少なくとも１つの開口部を有した回路基板が
貼着され、前記開口部により露出された前記金属基板上
にパワー半導体チップを固着したことを特徴とする混成
集積回路装置。1. A circuit pattern is formed on a metal substrate, and a circuit substrate having at least one opening is attached, and a power semiconductor chip is fixed on the metal substrate exposed by the opening. A hybrid integrated circuit device characterized by the above.
れ、且つ、少なくとも１つの開口部を有した回路基板が
貼着され、前記開口部より露出された前記金属基板上
に、パワー回路部とそのパワー回路部を駆動させる小信
号系回路部とが１チップ化されたパワー半導体素子を固
着したことを特徴とする混成集積回路装置。2. A circuit pattern is formed on a metal substrate, and a circuit substrate having at least one opening is adhered, and a power circuit unit and a power circuit unit are provided on the metal substrate exposed from the opening. A hybrid integrated circuit device characterized in that a power semiconductor element integrated into one chip is fixed to a small signal system circuit section for driving the power circuit section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14373193A JP3296626B2 (en) | 1993-06-15 | 1993-06-15 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14373193A JP3296626B2 (en) | 1993-06-15 | 1993-06-15 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0714938A true JPH0714938A (en) | 1995-01-17 |
| JP3296626B2 JP3296626B2 (en) | 2002-07-02 |
Family
ID=15345703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14373193A Expired - Fee Related JP3296626B2 (en) | 1993-06-15 | 1993-06-15 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3296626B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011078010A1 (en) | 2009-12-25 | 2011-06-30 | 富士フイルム株式会社 | Insulated substrate, process for production of insulated substrate, process for formation of wiring line, wiring substrate, and light-emitting element |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6903813B2 (en) | 2002-02-21 | 2005-06-07 | Jjl Technologies Llc | Miniaturized system and method for measuring optical characteristics |
| MXPA06014778A (en) | 2004-06-17 | 2007-03-23 | Bayer Healthcare Llc | Coaxial diffuse reflectance read head. |
-
1993
- 1993-06-15 JP JP14373193A patent/JP3296626B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011078010A1 (en) | 2009-12-25 | 2011-06-30 | 富士フイルム株式会社 | Insulated substrate, process for production of insulated substrate, process for formation of wiring line, wiring substrate, and light-emitting element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3296626B2 (en) | 2002-07-02 |
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