JP3172393B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JP3172393B2
JP3172393B2 JP10442195A JP10442195A JP3172393B2 JP 3172393 B2 JP3172393 B2 JP 3172393B2 JP 10442195 A JP10442195 A JP 10442195A JP 10442195 A JP10442195 A JP 10442195A JP 3172393 B2 JP3172393 B2 JP 3172393B2
Authority
JP
Japan
Prior art keywords
substrate
external lead
bonding
support member
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10442195A
Other languages
Japanese (ja)
Other versions
JPH08306858A (en
Inventor
伸一 豊岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10442195A priority Critical patent/JP3172393B2/en
Publication of JPH08306858A publication Critical patent/JPH08306858A/en
Application granted granted Critical
Publication of JP3172393B2 publication Critical patent/JP3172393B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE: To realize reduction in dead space and improvement in mounting efficiency of a substrate, by providing an outer lead support member which has a protrusion having a recess facing the periphery of the substrate. CONSTITUTION: An outer lead 21 is integrally molded by a support member 22, and a recess 26 is provided on the lower side of a right end surface 25 of a protrusion 24 of the exposed outer lead 21. Therefore, an element may be mounted in a space formed by the recess 26 and the surface of a substrate 10, so that improvement in element mounting efficiency of the substrate and reduction in the size of the substrate and the entire device can be realized. Also, by integrally supporting the outer lead 21, the strength of the outer lead can be improved. Even though a support pole is not provided on the support member, and even though the protruding portion is made longer, the support member is not inclined and perfect wire bonding can be performed. Thus, failure in adhesion and bonding between the support member and the substrate can be prevented, so as to improve yield.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、混成集積回路装置に関
し、特に多種多様のコネクタに対応するため、外部リー
ドと基板上の配線を金属ワイヤーで接続した混成集積回
路装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which external leads and wiring on a substrate are connected by metal wires in order to support various types of connectors.

【0002】[0002]

【従来の技術】従来の混成集積回路装置は、図5に示す
ように、セラミック、プリント基板および表面を絶縁処
理した金属基板等から成る基板1上に所望の配線パター
ン2が設けられ、この配線パターン2に複数の回路素子
3が設けられている。配線パターンは、配線、配線と一
体の電極またはランド、アイランド状のランドおよび外
部リードが固着されるパッド等で成る。更に、前記パッ
ドに外部リード4が半田で固着され、前記基板1表面、
回路素子2等が封止手段5により密封封止されている。
2. Description of the Related Art In a conventional hybrid integrated circuit device, as shown in FIG. 5, a desired wiring pattern 2 is provided on a substrate 1 composed of a ceramic, a printed substrate, a metal substrate whose surface is insulated, and the like. A plurality of circuit elements 3 are provided in the pattern 2. The wiring pattern includes wiring, electrodes or lands integrated with the wiring, island-like lands, and pads to which external leads are fixed. Further, external leads 4 are fixed to the pads by soldering,
The circuit element 2 and the like are hermetically sealed by the sealing means 5.

【0003】この構造において、外部リード4は、パッ
ドに半田付けされるために、特に外部リード4に加わる
外力により、外部リードがパッド部から剥離する問題が
あった。そのため、例えば、特開平2−165694号
公報、図6のように、外部リード4が樹脂でなる支持部
材6で一体成型されたものが用いられた。ここで図番8
で示す部分は、図5で示すパッドとの固着部9に該当す
る部分である。
In this structure, since the external lead 4 is soldered to the pad, there is a problem that the external lead is separated from the pad portion due to an external force applied to the external lead 4. For this reason, for example, as shown in FIG. 6 of JP-A-2-165694, an external lead 4 integrally molded with a support member 6 made of resin is used. Figure 8 here
The portion indicated by is the portion corresponding to the pad fixing portion 9 shown in FIG.

【0004】しかし、この外部リード4は、例えばソケ
ットに挿入されるため、サイズが規定される。特にカー
用の混成集積回路装置等では、外部リードのサイズか各
メーカーにより多種多様で、外部リードの幅、電流容量
によりこの外部リードの厚み等が異なる。そのためこの
多種多様の外部リードに合わせて間隔、サイズ等の異な
るパッドをその機種毎の基板に用意する必要があり、非
合理的であり、コスト高になる問題があった。しかも外
部リードは半田付けでされているために、半田付けの際
に、半田が飛び散りショートの原因となったり、フラッ
クスによる不良、またはフラックスの洗浄等が必要にな
る問題もあった。
However, since the external lead 4 is inserted into, for example, a socket, its size is defined. In particular, in the case of a hybrid integrated circuit device for a car or the like, the size of the external lead varies depending on the manufacturer, and the thickness of the external lead differs depending on the width and the current capacity of the external lead. Therefore, it is necessary to prepare pads having different intervals, sizes, and the like on the substrate for each model in accordance with the various external leads, which is irrational and increases the cost. In addition, since the external leads are soldered, the solder scatters during soldering, causing a short circuit, a defect due to a flux, or a need to clean the flux.

【0005】そのため、例えば図3で示すように、外部
リード4は、支持部材6で支持されており、外部リード
の固着部分9は、断面で見るとトの字の形状の支持部材
6の突出部分10の上面11に載置され、リードの電気
的接続領域が露出されているものが採用された。例えば
図3や図4のように、ボンディングパッド12が配列さ
れていれば、外部リード4のサイズがどのようなもので
あっても、金属細線13で接続されているので、外部リ
ードのサイズにより基板のパターンを変更することがな
く、ワイヤーボンデイングで接続するため半田やフラッ
クスによる不都合もなくなる特徴を有していた。
For this reason, as shown in FIG. 3, for example, the external lead 4 is supported by a support member 6, and the fixing portion 9 of the external lead is formed by projecting the support member 6 in a cross section when viewed in cross section. The one that was placed on the upper surface 11 of the part 10 and the electrical connection area of the lead was exposed was adopted. For example, as shown in FIGS. 3 and 4, if the bonding pads 12 are arranged, the external leads 4 are connected by the thin metal wires 13 regardless of the size of the external leads 4. Since the connection was made by wire bonding without changing the pattern of the substrate, there was a feature that the inconvenience due to solder and flux was eliminated.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、支持部
材6の突出部分10の下面14は、図3のように基板1
に接着材を介して固着されており、外部リード4のサイ
ズにも依るが、外部リード4固定部から上面11の固着
部分9までの距離(矢印Aで示す部分)は、約4ミリ以
上必要であり、またワイヤーボンディングの装置の都合
上、外部リードのボンデイングエリアからボンディング
パッド12のボンデイング部までの距離(矢印Bで示す
部分)も、最低4.5ミリ程度必要となり、E部がデッ
ドスペースとなり、同一回路基板を組むには、かえって
基板のサイズが大きくなる問題があった。
However, the lower surface 14 of the protruding portion 10 of the support member 6 is mounted on the substrate 1 as shown in FIG.
The distance from the fixing portion of the external lead 4 to the fixing portion 9 of the upper surface 11 (the portion indicated by the arrow A) is required to be about 4 mm or more, although it depends on the size of the external lead 4. Also, due to the wire bonding apparatus, the distance from the bonding area of the external lead to the bonding portion of the bonding pad 12 (portion indicated by arrow B) needs to be at least about 4.5 mm, and the E portion is a dead space. Therefore, there is a problem that the size of the substrate is rather large when assembling the same circuit substrate.

【0007】しかも図3の突出部分の右端部を図4では
一点鎖線で示しているが、この一点鎖線とボンディング
パッド12との間には、何も設けてないため、更に基板
サイズが大きくなり、トータル的に考えると実装効率が
悪化する問題があった。
Further, the right end of the protruding portion in FIG. 3 is indicated by a dashed line in FIG. 4, but nothing is provided between the dashed line and the bonding pad 12, so that the substrate size is further increased. However, there is a problem that mounting efficiency deteriorates when considered in total.

【0008】[0008]

【課題を解決するための手段】本発明は前述した課題に
鑑みて成され、第1に、外部リードのボンディング領域
が基板の内側に向かって延在され、この延在部分の下層
に対応する前記基板に素子が実装できるように、基板の
周辺に向かい凹みが設けられた外部リード支持部材を設
けることで解決するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem. First, a bonding region of an external lead extends toward the inside of a substrate and corresponds to a lower layer of the extended portion. This problem is solved by providing an external lead support member provided with a recess toward the periphery of the substrate so that the element can be mounted on the substrate.

【0009】第2に、外部リードを一体で支持し、ボン
ディング領域が基板の上方で内側に向かって延在され、
この延在部分の下層に対応する前記基板に素子が実装で
きるように、基板の周辺に向かい凹みが設けられたトの
字の形状の外部リード支持部材と、前記基板に設けら
れ、前記延在部分の下層に設けられた素子により、外部
リードのボンデイング領域か任意の距離に設けられた導
電パッドとを設けることで解決するものである。
Second, the external lead is integrally supported, and the bonding area extends inward above the substrate.
A C-shaped external lead support member provided with a recess toward the periphery of the substrate so that an element can be mounted on the substrate corresponding to the lower layer of the extension portion; This problem can be solved by providing a bonding area of an external lead or a conductive pad provided at an arbitrary distance by an element provided in a layer below the portion.

【0010】第3に、前記支持部材には支柱を設けるこ
とで解決するものである。第4に、外部リードのボンデ
ィング領域が基板の内側に向かって延在され、この延在
部分の下層に対応する前記基板に素子が実装できるよう
に、前記延在領域よりも前記基板との接着部分の長さが
短く設けられた外部リード支持部材を設けることで解決
するものである。
Third, the problem can be solved by providing a support on the support member. Fourth, the bonding area of the external lead extends toward the inside of the substrate, and the bonding area with the substrate is larger than that of the extending area so that the element can be mounted on the substrate corresponding to the lower layer of the extending part. The problem is solved by providing an external lead support member having a short portion.

【0011】[0011]

【作用】第1に、基板の周辺に向かい凹みが設けられた
外部リード支持部材を設けることで、この凸部の上面に
は、ボンデイングに十分な面積のボンディング領域が設
けられると共に、凸部の下面の下層には素子が実装でき
るため、デッドスペースの減少が実現できる。
First, by providing an external lead support member provided with a recess toward the periphery of the substrate, a bonding area having a sufficient area for bonding is provided on the upper surface of the convex portion, and the convex portion of the convex portion is provided. Since the element can be mounted on the lower layer of the lower surface, the dead space can be reduced.

【0012】第2に、第1の作用と共に、外部リードを
一体で支持しているために、外部リードの強度を向上せ
せることができる。第3に、前記支持部材には支柱を設
けることで、突出部が長くなっても支持部材が傾くこと
なく完全にワイヤーボンディングが可能となる。第4
に、延在領域よりも前記基板との接着部分の長さが短く
設けられた外部リード支持部材を設けることで、前記第
1の作用と同様に、凸部の上面には、ボンデイングに十
分な面積のボンディング領域が設けられると共に、凸部
の下面の下層には素子が実装できるため、デッドスペー
スの減少が実現できる。
Second, since the external leads are integrally supported together with the first operation, the strength of the external leads can be improved. Third, by providing the support member with a support, even if the protruding portion becomes long, the wire bonding can be completely performed without tilting the support member. 4th
In addition, by providing an external lead supporting member having a shorter length of the bonding portion with the substrate than the extending region, the upper surface of the convex portion has sufficient bonding for the bonding, similarly to the first operation. Since a bonding region having a large area is provided and an element can be mounted below the lower surface of the projection, a reduction in dead space can be realized.

【0013】また図7のように、突出部が傾斜している
場合、突出部が長くなると、付け根の部分が厚くなり、
図1と比べ強度が増す。
As shown in FIG. 7, when the protruding portion is inclined, as the protruding portion becomes longer, the base portion becomes thicker,
The strength is increased as compared with FIG.

【0014】[0014]

【実施例】以下に本発明の実施例を図1と図2を参照し
ながら説明する。まず、絶縁処理した第1の基板10
は、表面に配線パターン11が形成され、この配線パタ
ーンの一部には、図2のように、ランド12が設けられ
ている。このランドには、半導体チップ13が半田付け
され、配線となる導電路11には、抵抗等が印刷によ
り、また部品であっては半田で固着されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. First, the insulated first substrate 10
In FIG. 2, a wiring pattern 11 is formed on the surface, and a land 12 is provided on a part of the wiring pattern as shown in FIG. A semiconductor chip 13 is soldered to this land, and a resistance or the like is fixed to the conductive path 11 serving as a wiring by printing, and a component is fixed by soldering.

【0015】ここで第1の基板10は、セラミック基
板、絶縁樹脂基板例えばプリント基板または表面を絶縁
処理した金属基板でもよい。ここではAl基板の表面を
陽極酸化し酸化アルミニウムが生成された金属基板10
を採用し、配線パターン11は銅箔より成り、ポリイミ
ド等の樹脂層を介してホットプレスにより被着されてい
る。
Here, the first substrate 10 may be a ceramic substrate, an insulating resin substrate, for example, a printed substrate or a metal substrate whose surface is insulated. Here, a metal substrate 10 in which aluminum oxide is generated by anodizing the surface of an Al substrate
The wiring pattern 11 is made of copper foil and is attached by hot pressing via a resin layer such as polyimide.

【0016】当然半導体チップ13は、ダイオード,ト
ランジスタチップおよびLSIチップであり、その他に
抵抗14、トランスやコンデンサ等の部品も必要により
実装される。また配線パターン11は、配線15、配線
と一体の電極(例えばチップ抵抗が接続される部分16
やボンディングパッド17)、配線と一体のランド1
8、配線と一体ではあるが外部リードとの接続に使うパ
ッド19(図面では斜線でハッチングしてある)、およ
びランド13等より構成される。
The semiconductor chip 13 is, of course, a diode, a transistor chip, and an LSI chip. In addition, components such as a resistor 14, a transformer, and a capacitor are mounted as necessary. The wiring pattern 11 includes a wiring 15 and an electrode integrated with the wiring (for example, a portion 16 to which a chip resistor is connected).
And bonding pad 17), land 1 integrated with wiring
8. Pads 19 (indicated by hatching in the drawing) which are integrated with the wiring but used for connection to external leads, lands 13 and the like.

【0017】またチップと導電路11は、必要によって
は金属細線がワイヤーボンドされ所定の回路が達成され
ている。またこの第1の基板10の少なくとも一側辺近
傍には、前記回路から延在された外部リード21との接
続のためにパッド19(斜め線でハッチングした領域)
が複数個設けられている。この配列の仕方は本発明の特
徴ではあるが説明の都合上後述する。
Further, a thin metal wire is wire-bonded to the chip and the conductive path 11 as necessary to achieve a predetermined circuit. Pads 19 (areas hatched by oblique lines) are provided near at least one side of the first substrate 10 for connection with external leads 21 extending from the circuit.
Are provided. Although this arrangement is a feature of the present invention, it will be described later for convenience of explanation.

【0018】この外部リード21は、外部リード支持部
材22により、固着され、前記パッド19との接続のた
めに少なくとも接続領域が露出されている。ここでは図
1から明らかなように外部リードは、支持部材22で一
体成型されており、ボンディング領域のみが露出されて
いる。一体成型されているために、外部リード21に外
力が加わっても、外部リードは強固に固定されており、
ワイヤのボンディング部分が剥離することはない。また
一体成型でなくても良く、支持部材22の段部(面23
と凸部24の上面)に外部リードが接着固定されても良
い。
The external lead 21 is fixed by an external lead supporting member 22, and at least a connection region is exposed for connection with the pad 19. Here, as is clear from FIG. 1, the external leads are integrally molded with the support member 22, and only the bonding area is exposed. Since the external lead 21 is integrally molded, even if an external force is applied to the external lead 21, the external lead is firmly fixed.
The bonding portion of the wire does not peel. Further, the support member 22 may not be integrally formed, but may be formed by a step (the surface 23) of the support member 22.
The external leads may be bonded and fixed to the upper surface of the projection 24).

【0019】ここでのポイントは、図3でも説明したよ
うに、本ディング領域がたんに露出されていれば良い。
本発明の特徴は、凸部24の右端面25の下方で凹み2
6が設けられていることにある。外部リード21と基板
10との接続のためのボンディング領域は、発明が解決
しようとする課題の欄にも説明したように、少なくとも
4ミリ程度の長さは必要で、これに伴い支持部材22の
突出長さも長くなる。しかし凹み26を設けているの
で、この凹み26と基板10表面で構成する空間には、
素子(配線、印刷抵抗等も可能)が実装できるので、基
板の素子実装効率を向上でき、図3の構造と比べ基板サ
イズ、装置全体のサイズを小さくすることができる。
The point here is, as described with reference to FIG. 3, as long as the booked area is simply exposed.
The feature of the present invention is that the recess 2 is formed below the right end face 25 of the projection 24.
6 is provided. As described in the section of the problem to be solved by the invention, the bonding area for connecting the external lead 21 and the substrate 10 needs to be at least about 4 mm long, and accordingly, the supporting member 22 The protruding length also increases. However, since the recess 26 is provided, the space formed by the recess 26 and the surface of the substrate 10 includes:
Since elements (wiring, printed resistance, etc. are also possible) can be mounted, the efficiency of mounting elements on the substrate can be improved, and the size of the substrate and the entire device can be reduced as compared with the structure of FIG.

【0020】図2において、矢印Dが指した所より下方
に向かう領域は、従来型、つまり図4で示した一点鎖線
の部分である。また矢印Eで示した一点鎖線は、支持部
材22と基板10との接合部右側を示すものである。つ
まり矢印DとEの間には、前述した色々な種類の配線パ
ターンが設けられており、凹みの高さにも依るが、チッ
プ抵抗、半導体チップ等の高さのある素子も実装でき
る。
In FIG. 2, the region directed downward from the position indicated by the arrow D is the conventional type, that is, the portion indicated by the chain line shown in FIG. The dashed line indicated by the arrow E indicates the right side of the joint between the support member 22 and the substrate 10. That is, between the arrows D and E, the various types of wiring patterns described above are provided, and depending on the height of the recess, a tall element such as a chip resistor or a semiconductor chip can be mounted.

【0021】また第2の特徴として、斜線で示したパッ
ド19の配置を以下に説明する。図4で説明したパッド
12の位置は、ボンディングを行うために、外部リード
4のボンディング部から一定距離離れたところに配置さ
れる。従って一直線上に配置されることになる。この構
造を図1または図2に適用すると、矢印DとEとの間に
は、この一直線上に配置したパッドが邪魔になり、色々
なタイプの配線パターンの配置がしにくくなり、かえっ
て実行効率を悪化させる問題がある。
As a second feature, the arrangement of the pad 19 indicated by oblique lines will be described below. The position of the pad 12 described with reference to FIG. 4 is arranged at a predetermined distance from the bonding portion of the external lead 4 for performing bonding. Therefore, they are arranged on a straight line. When this structure is applied to FIG. 1 or FIG. 2, the pad arranged on the straight line between the arrows D and E becomes an obstacle, and it becomes difficult to arrange various types of wiring patterns. There is a problem that worsens.

【0022】従って本願は、矢印DとEとの間に設けら
れた配線パターンにより、又は矢印Dより右側の配線パ
ターンの都合により、パッドの位置を一定距離にしない
ことにある。つまりDの領域を境にして、左右に設けら
れる配線パターンの都合で、空きスペースを探し、その
領域にパッド19を設けることで、図4のような場合の
実装効率の悪化を防止できる。またボンデイング機械
は、最近は、コンピューター制御であるので、外部リー
ドのボンデイングエリアとパッドとの距離は任意に選択
できるので何の問題もない。また直接、トランジスタ等
の半導体素子へ直接ボンディングすることも可能であ
る。
Accordingly, the present application is to prevent the position of the pad from being a fixed distance due to the wiring pattern provided between the arrows D and E or due to the wiring pattern on the right side of the arrow D. That is, by searching for an empty space and providing the pad 19 in the area of the wiring pattern provided on the left and right sides of the area D, deterioration of the mounting efficiency in the case shown in FIG. 4 can be prevented. Also, since the bonding machine is computer-controlled recently, there is no problem since the distance between the bonding area of the external lead and the pad can be arbitrarily selected. It is also possible to directly bond to a semiconductor element such as a transistor.

【0023】ここで外部リードの仕様により、凸部の上
面を長くする必要がある場合、ボンデイングの加圧力に
より支持部材と基板との接着面が剥がれたり、ボンディ
ング時に超音波出力がうまく接合面に伝わらない恐れが
ある。この場合、支持部材の凸部24の下面と基板との
間に支柱を設けることで、この問題は解決できる。この
支柱は、支持部材と一体で成型されていても良いし、基
板と一体でも良い。また別体で形成されていても良い。
各外部リードの幅にも依るが、少なくとも一本有れば良
い。
If it is necessary to lengthen the upper surface of the projection due to the specifications of the external lead, the bonding surface between the support member and the substrate may be peeled off by the pressing force of the bonding, or the ultrasonic output may be properly applied to the bonding surface during bonding. It may not be transmitted. In this case, this problem can be solved by providing a support between the lower surface of the protrusion 24 of the support member and the substrate. This support may be formed integrally with the support member, or may be integrated with the substrate. Further, they may be formed separately.
Although it depends on the width of each external lead, at least one lead is sufficient.

【0024】一方、図7に第2の実施例を説明する。こ
の実施例は、前実施例の凸部24の上のコーナーから基
板との接着面の右の側辺までを結び、左斜め下に傾斜し
た面を有することにある。形状は異なるが凹みを有する
ため、やはりここに形成される空間に配線パターンが設
けられるため、実装効率を向上させることができる。両
実施例は、最後に支持部材22と基板周辺を囲む枠材ま
たはケース材(ここでは図示せず)で基板表面を樹脂で
封止する封止空間を形成する。図7は、斜め左下に傾斜
しているため、左端は、高さのある素子を実装すること
は難しいが、樹脂を注入したときに樹脂に取り込まれる
気泡を表面に取り出すことが可能である。
FIG. 7 shows a second embodiment. This embodiment has a surface that connects the upper corner of the convex portion 24 of the previous embodiment to the right side of the bonding surface with the substrate and that is inclined diagonally downward and to the left. Since the wiring pattern is provided in the space formed here since the shape is different but has a recess, the mounting efficiency can be improved. In both embodiments, finally, a sealing space for sealing the substrate surface with resin is formed by the support member 22 and a frame material or a case material (not shown here) surrounding the periphery of the substrate. In FIG. 7, it is difficult to mount an element having a height at the left end because it is inclined obliquely to the lower left, but it is possible to take out bubbles taken into the resin when the resin is injected.

【0025】例えば上方からシリコンゲルが注入され、
続いてエポキシ等の樹脂が注入され完成されている。シ
リコーンゲルは、半導体チップ等に接続されている金属
細線等への歪みを防止したり、耐湿性を向上するもので
あり、必ず注入しなければならないものではない。
For example, silicon gel is injected from above,
Subsequently, a resin such as epoxy is injected and completed. Silicone gel prevents distortion of fine metal wires and the like connected to a semiconductor chip and the like and improves moisture resistance, and is not necessarily required to be injected.

【0026】[0026]

【発明の効果】以上の説明からも明らかなように、第1
に、基板の周辺に向かい凹みが設けられた凸部を持つ外
部リード支持部材を設けることで、この凸部の上面に
は、ボンデイングに十分な面積のボンディング領域が設
けられると共に、凸部の下面の下層には素子が実装でき
るため、デッドスペースの減少が実現できる。従って外
部リードのサイズにより、基板上に設けられるパターン
設計の変更もなく多機種に同一基板が展開できると共
に、基板の実装効率を悪化させることもなく、装置全体
のサイズの大型化を抑止できる。
As is clear from the above description, the first
In addition, by providing an external lead supporting member having a convex portion provided with a recess toward the periphery of the substrate, a bonding area having a sufficient area for bonding is provided on the upper surface of the convex portion, and the lower surface of the convex portion is provided. Since the element can be mounted in the lower layer, the dead space can be reduced. Therefore, depending on the size of the external leads, the same substrate can be developed in many types without changing the design of the pattern provided on the substrate, and the overall size of the device can be suppressed from being increased without deteriorating the mounting efficiency of the substrate.

【0027】第2に、第1の効果と共に、外部リードを
一体で支持しているために、外部リードの強度を向上せ
せることができる。更には、外部リードに接続されたワ
イヤーの他端が接続される部分、つまりパッドの位置
は、このワイヤーの長さ、つまり外部リードのボンデイ
ング領域とパッドとの距離を任意に設定している。つま
り凹み部の配線パターンの都合、またはこれより右側に
設けられる配線パターンの都合により、パットは適当な
位置(空いているスペース)に設けられるので、パッド
の位置に制約をうけて実装効率を悪化させることがな
い。
Second, since the external leads are integrally supported together with the first effect, the strength of the external leads can be improved. Further, the portion to which the other end of the wire connected to the external lead is connected, that is, the position of the pad, arbitrarily sets the length of the wire, that is, the distance between the bonding region of the external lead and the pad. That is, the pad is provided at an appropriate position (vacant space) due to the wiring pattern of the recessed portion or the wiring pattern provided on the right side thereof, so that the mounting position is restricted due to the restriction of the pad position. I will not let you.

【0028】第3に、前記支持部材には支柱を設けるこ
とで、突出部が長くなっても支持部材が傾くことなく完
全にワイヤーボンディングが可能となる。従って、支持
部材と基板との接着不良やボンディング不良が防止で
き、歩留まりの向上にもつながる。第4に、延在領域よ
りも前記基板との接着部分の長さが短く設けられた外部
リード支持部材を設けることで、前記第1の作用と同様
に、凸部の上面には、ボンデイングに十分な面積のボン
ディング領域が設けられると共に、凸部の下面の下層に
は素子が実装できるため、デッドスペースの減少が実現
できる。
Third, by providing the support member with a support, the wire bonding can be completely performed without the support member being inclined even when the protruding portion becomes long. Therefore, poor adhesion and poor bonding between the support member and the substrate can be prevented, which leads to an improvement in yield. Fourth, by providing an external lead supporting member provided with a shorter bonding portion with the substrate than the extension region, the upper surface of the projection is bonded to the upper surface of the projection in the same manner as in the first operation. Since a bonding region having a sufficient area is provided and an element can be mounted below the lower surface of the projection, a reduction in dead space can be realized.

【0029】また図7のように、突出部が傾斜している
場合、突出部が長くなると、付け根の部分が厚くなり、
図1と比べ強度が増す。また樹脂を封止した際、中に取
り込まれる気泡が除去でき、特に大電流が流れ発熱する
ような装置の場合、気泡の破裂等を防止できる。
As shown in FIG. 7, when the protruding portion is inclined, as the protruding portion becomes longer, the base portion becomes thicker,
The strength is increased as compared with FIG. In addition, when the resin is sealed, air bubbles taken in can be removed, and particularly in the case of a device in which a large current flows and generates heat, bursting of the air bubbles and the like can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第一の実施例を説明する図である。FIG. 1 is a diagram illustrating a first embodiment of the present invention.

【図2】図1に対応する平面図である。FIG. 2 is a plan view corresponding to FIG.

【図3】従来の混成集積回路装置の断面図である。FIG. 3 is a cross-sectional view of a conventional hybrid integrated circuit device.

【図4】図3に対応する平面図である。FIG. 4 is a plan view corresponding to FIG.

【図5】従来の混成集積回路装置の組立図である。FIG. 5 is an assembly diagram of a conventional hybrid integrated circuit device.

【図6】外部リードを一体成型した従来の支持部材の図
である。
FIG. 6 is a view of a conventional support member in which external leads are integrally formed.

【図7】本発明の第二の実施例を説明する図である。FIG. 7 is a diagram illustrating a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 第1の基板 11 配線パターン 12 ランド 13 半導体チップ 14 抵抗 15 配線 17 ボンディングパッド 18 ランド 19 パッド 21 外部リード 22 外部リード支持部材 26 凹み Reference Signs List 10 first substrate 11 wiring pattern 12 land 13 semiconductor chip 14 resistor 15 wiring 17 bonding pad 18 land 19 pad 21 external lead 22 external lead support member 26 recess

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 少なくとも表面が絶縁性を有する基板
と、 この基板に設けられた配線パターンと、 この配線パターンと一体でまたは別体で成るランドと電
気的に接続された半導体素子と、 前記配線パターンや前記半導体素子で構成される回路の
入出力信号が印加される外部リードと、 この外部リードのボンディング領域が前記基板の内側に
向かって延在され、この延在部分の下層に対応する前記
基板に素子が実装できるように、基板の周辺に向かい凹
みが設けられた外部リード支持部材と、 前記基板に設けられた導電パッドと前記外部リードのボ
ンディング領域を接続する接続手段と、 少なくとも前記基板表面およびボンディング部を保護す
る封止手段とを有することを特徴とした混成集積回路装
置。
1. A substrate having at least a surface having an insulating property; a wiring pattern provided on the substrate; a semiconductor element electrically connected to a land formed integrally with or separate from the wiring pattern; An external lead to which an input / output signal of a circuit constituted by a pattern or the semiconductor element is applied, and a bonding region of the external lead extends toward the inside of the substrate, and corresponds to a lower layer corresponding to the extended portion. An external lead support member provided with a recess toward the periphery of the substrate so that an element can be mounted on the substrate; connecting means for connecting a conductive pad provided on the substrate to a bonding area of the external lead; and at least the substrate A hybrid integrated circuit device having sealing means for protecting a surface and a bonding portion.
【請求項2】 少なくとも表面が絶縁性を有する基板
と、 この基板に設けられた配線パターンと、 この配線パターンと一体でまたは別体で成るランドと電
気的に接続された半導体素子と、 前記配線パターンや前記半導体素子で構成される回路の
入出力信号が印加される外部リードと、 この外部リードを一体で支持し、ボンディング領域が前
記基板の上方で内側に向かって延在され、この延在部分
の下層に対応する前記基板に素子が実装できるように、
基板の周辺に向かい凹みが設けられたトの字の形状の外
部リード支持部材と、 前記基板に設けられ、前記延在部分の下層に設けられた
素子により、外部リードのボンデイング領域か任意の距
離に設けられた導電パッドと、 前記導電パッドと前記外部リードのボンディング領域を
接続する接続手段と、 少なくとも前記基板表面およびボンディング部を保護す
る封止手段とを有することを特徴とした混成集積回路装
置。
2. A substrate having at least a surface having an insulating property; a wiring pattern provided on the substrate; a semiconductor element electrically connected to a land integrated with or separate from the wiring pattern; An external lead to which an input / output signal of a circuit constituted by the pattern or the semiconductor element is applied; and an external lead which is integrally supported, and a bonding region extends inward above the substrate, and As the element can be mounted on the substrate corresponding to the lower layer of the part,
An external lead support member having a U-shape provided with a recess toward the periphery of the substrate; and an element provided on the substrate and provided below the extending portion, the bonding area of the external lead or an arbitrary distance. A hybrid integrated circuit device, comprising: a conductive pad provided on a substrate; connecting means for connecting the bonding area between the conductive pad and the external lead; and sealing means for protecting at least the substrate surface and the bonding portion. .
【請求項3】 前記基板支持部材の凹みには、支柱が設
けられる請求項1または2記載の混成集積回路装置。
3. The hybrid integrated circuit device according to claim 1, wherein a pillar is provided in the recess of said substrate support member.
【請求項4】 少なくとも表面が絶縁性を有する基板
と、 この基板に設けられた配線パターンと、 この配線パターンと一体でまたは別体で成るランドと電
気的に接続された半導体素子と、 前記配線パターンや前記半導体素子で構成される回路の
入出力信号が印加される外部リードと、 この外部リードのボンディング領域が前記基板の内側に
向かって延在され、この延在部分の下層に対応する前記
基板に素子が実装できるように、前記延在領域よりも前
記基板との接着部分の長さが短く設けられた外部リード
支持部材と、 前記基板に設けられた導電パッドと前記外部リードのボ
ンディング領域を接続する接続手段と、 少なくとも前記基板表面およびボンディング部を保護す
る封止手段とを有することを特徴とした混成集積回路装
置。
4. A substrate having at least a surface having an insulating property; a wiring pattern provided on the substrate; a semiconductor element electrically connected to a land formed integrally with or separate from the wiring pattern; An external lead to which an input / output signal of a circuit constituted by a pattern or the semiconductor element is applied, and a bonding region of the external lead extends toward the inside of the substrate, and corresponds to a lower layer corresponding to the extended portion. An external lead supporting member provided with a shorter bonding portion with the substrate than the extending region so that an element can be mounted on the substrate; and a bonding region between the conductive pad provided on the substrate and the external lead. And a sealing means for protecting at least the substrate surface and the bonding portion.
JP10442195A 1995-04-27 1995-04-27 Hybrid integrated circuit device Expired - Fee Related JP3172393B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10442195A JP3172393B2 (en) 1995-04-27 1995-04-27 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10442195A JP3172393B2 (en) 1995-04-27 1995-04-27 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH08306858A JPH08306858A (en) 1996-11-22
JP3172393B2 true JP3172393B2 (en) 2001-06-04

Family

ID=14380236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10442195A Expired - Fee Related JP3172393B2 (en) 1995-04-27 1995-04-27 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP3172393B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100454537C (en) * 2005-04-13 2009-01-21 株式会社电装 Electronic apparatus and method for manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885097B2 (en) 2000-04-25 2005-04-26 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100454537C (en) * 2005-04-13 2009-01-21 株式会社电装 Electronic apparatus and method for manufacturing the same

Also Published As

Publication number Publication date
JPH08306858A (en) 1996-11-22

Similar Documents

Publication Publication Date Title
US6482674B1 (en) Semiconductor package having metal foil die mounting plate
US6313520B1 (en) Resin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereon
JPH09260538A (en) Resin sealed semiconductor device manufacturing method and its mounting structure
JPWO2020208741A1 (en) Semiconductor devices and lead frame materials
JP2002134674A (en) Semiconductor device and its manufacturing method
KR101644913B1 (en) Semiconductor package by using ultrasonic welding and methods of fabricating the same
JP3172393B2 (en) Hybrid integrated circuit device
JP3183064B2 (en) Semiconductor device
JPH11307721A (en) Power module device and manufacture therefor
JP2524482B2 (en) QFP structure semiconductor device
JP4543542B2 (en) Semiconductor device
KR101008534B1 (en) Power semiconductor mudule package and method for fabricating the same
JP3048707B2 (en) Hybrid integrated circuit
JP3454192B2 (en) Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same
JPH06163746A (en) Hybrid integrated circuit device
JP2975783B2 (en) Lead frame and semiconductor device
JPH07226454A (en) Semiconductor device
JPH0741167Y2 (en) Insulator-sealed circuit device
JPH0442942Y2 (en)
JPH0334561A (en) Semiconductor device
JPH08181168A (en) Semiconductor device
JP3248117B2 (en) Semiconductor device
JPH11219969A (en) Semiconductor device
JPH05144985A (en) Hybrid integrated circuit device
JP2692904B2 (en) Semiconductor device with built-in diode chip and manufacturing method thereof

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090323

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 8

Free format text: PAYMENT UNTIL: 20090323

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20100323

LAPS Cancellation because of no payment of annual fees