JP2692904B2 - Semiconductor device with built-in diode chip and manufacturing method thereof - Google Patents
Semiconductor device with built-in diode chip and manufacturing method thereofInfo
- Publication number
- JP2692904B2 JP2692904B2 JP63286932A JP28693288A JP2692904B2 JP 2692904 B2 JP2692904 B2 JP 2692904B2 JP 63286932 A JP63286932 A JP 63286932A JP 28693288 A JP28693288 A JP 28693288A JP 2692904 B2 JP2692904 B2 JP 2692904B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- diode
- semiconductor device
- transistor
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明はSIP型半導体装置にトランジスタチップとダ
ンパダイオード用チップとを内蔵した半導体装置の構造
と製造方法に関する。The present invention relates to a structure and a manufacturing method of a semiconductor device in which a SIP type semiconductor device has a transistor chip and a damper diode chip built therein.
（ロ）従来の技術 CRT等の励振回路は第４図に示す如くL,Cを含んでお
り、のこぎり波で励振した場合、励振用トランジスタ
（１）がoffしてもLC中の電流振動は直ちには停止しな
いので、トランジスタ（１）のエミッタ・コレクタ間に
並列にダンパダイオード（２）を接続し、トランジスタ
（１）がoffする場合には、このダイパダイオード
（２）に順方向電流を流して振動を抑える手法が処され
ている。(B) Conventional technology An excitation circuit such as a CRT contains L and C as shown in Fig. 4. When excited by a sawtooth wave, the current oscillation in LC does not occur even if the excitation transistor (1) is turned off. Since it does not stop immediately, a damper diode (2) is connected in parallel between the emitter and collector of the transistor (1), and when the transistor (1) turns off, a forward current is applied to this diper diode (2). The method of suppressing the vibration is taken.
従来、この種の回路に用いられる半導体装置は、ダン
パダイオード（２）が励振用トランジスタ（１）と同等
の高耐圧が要求されることから、パワートランジスタチ
ップを内蔵した半導体装置とダイオードチップを内蔵し
た半導体装置とを回路基板上で組み立てるか、又は特開
昭62−25447号公報に記載されているようなパワーモジ
ュールと称される半導体装置に収納していた。Conventionally, a semiconductor device used in this type of circuit requires a high withstand voltage equivalent to that of the excitation transistor (1) for the damper diode (2). Therefore, a semiconductor device including a power transistor chip and a diode chip are incorporated. The above semiconductor device is assembled on a circuit board, or is housed in a semiconductor device called a power module as described in JP-A-62-25447.
（ハ）発明が解決しようとする課題 しかしながら、電子機器の小型化及びローコスト化の
要求から、前記パワートランジスタチップとダイオード
チップとを１つのパッケージ、しかもSIP型半導体装置
に搭載したい要求が強まってきた。その為本願は、SIP
型パッケージに両者を搭載するに際し、量産化に優れ安
価に且つ信頼性の高い装置を製造し得る構造と製造方法
を提供するものである。(C) Problems to be Solved by the Invention However, due to demands for miniaturization and cost reduction of electronic devices, there is an increasing demand for mounting the power transistor chip and the diode chip in one package, and further in a SIP type semiconductor device. . Therefore, this application is SIP
It is intended to provide a structure and a manufacturing method capable of manufacturing a device which is excellent in mass production, inexpensive, and highly reliable when mounting both in a die package.
（ニ）課題が解決するための手段 本発明は上記従来の課題に鑑み成されたもので、 まず第１に、複数個のダイオードチップ（11）を並列
接続して搭載することにより、限られたスペース内に効
率的に配置でき且つ既製のダイオードチップを利用し得
る構造を得るものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems. First, it is limited by mounting a plurality of diode chips (11) in parallel. (EN) A structure that can be efficiently arranged in a space and can utilize a ready-made diode chip.
第２に、エミッタパッド（18）を接続するボンディン
グワイヤ（16）の軌跡とダイオードを接続するボンディ
ングワイヤ（16）の軌跡を夫々リード（15）の延在方向
に対して平行となるように各チップ（11）（12）を配置
することにより、量産性に優れ且つトランジスタ（11）
及びダイオードチップ（12）共に既製のチップを利用で
きる構造と製造方法を提供するものである。Secondly, the locus of the bonding wire (16) connecting the emitter pad (18) and the locus of the bonding wire (16) connecting the diode are made parallel to the extending direction of the leads (15), respectively. By arranging the chips (11) (12), the mass productivity is excellent and the transistor (11)
The present invention provides a structure and a manufacturing method that can use ready-made chips for both the diode chip (12).
第３に、SIP型の短尺状リードフレームに両チップを
搭載するに際し、先ず全てのダイ部分（14）にトランジ
スタチップ（11）を固着し、続いてダイオードチップ
（12）を固着することにより、信頼性の高いダイボンド
が可能な製造方法を提供するものである。Thirdly, when mounting both chips on the SIP type short lead frame, first, the transistor chips (11) are fixed to all the die parts (14), and then the diode chips (12) are fixed. It is intended to provide a manufacturing method capable of highly reliable die bonding.
（ホ）作用 本発明によれば、第１に小さいサイズのダイオードチ
ップ（12）を複数個並列接続するので、チップ配置の設
計自由度が増し、ダイ部分（14）の余白に任意に配置で
きる。しかも、略正方形形状を成す既成のダイオードチ
ップ（12）を使用できるので、余白形状に合致したパタ
ーンのダイオードチップ（12）を新規製造せずに済む。(E) Operation According to the present invention, first, a plurality of small-sized diode chips (12) are connected in parallel, so that the degree of freedom in designing the chip arrangement is increased and the chip portions can be arbitrarily arranged in the margin of the die portion (14). . Moreover, since the existing diode chip (12) having a substantially square shape can be used, it is not necessary to newly manufacture the diode chip (12) having a pattern matching the blank shape.
第２に、ボンディングワイヤ（16）の軌跡がリード
（15）に対して平行となるようにトランジスタチップ
（11）とダイオードチップ（12）を配置したので、夫々
のパッドとエミッタリード（15b）とを夫々ステッチボ
ンドするワイヤ（16）を極端に屈折させずに済む。Secondly, since the transistor chip (11) and the diode chip (12) are arranged so that the locus of the bonding wire (16) is parallel to the lead (15), each pad and emitter lead (15b) It is not necessary to bend the wire (16) that stitch-bonds each other extremely.
第３に、先にトランジスタチップ（11）のダイボンド
を行うので、１回目ダイボンドの熱処理によってダイ部
（14）表面が酸化する以前に厳しい信頼性を要するトラ
ンジスタチップ（11）の固着を終えることができる。Thirdly, since the transistor chip (11) is die-bonded first, it is possible to finish the fixing of the transistor chip (11) that requires severe reliability before the surface of the die part (14) is oxidized by the first heat treatment of the die bond. it can.
（へ）実施例 以下、本発明の最も好ましい一実施例を図面を参照し
ながら詳細に説明する。(H) Embodiment Hereinafter, a most preferred embodiment of the present invention will be described in detail with reference to the drawings.
第１図はパワー系のトランジスタチップ（11）と、２
個のダイオードチップ（12）とを固着した状態のリード
フレームの要部を示し、（13）は放熱用ヒートシンク、
（14）はヒートシンク（13）の主要面でチップ搭載部と
なるダイ部分、（15）は外部接続端子としてのリードで
ある。Fig. 1 shows a power system transistor chip (11) and 2
The main part of the lead frame with the diode chips (12) fixed is shown, (13) is a heat sink for heat dissipation,
(14) is a die portion which is a chip mounting portion on the main surface of the heat sink (13), and (15) is a lead as an external connection terminal.
リードフレームは、あらかじめ異る大きさのダイ部分
（14）を有する複数種類の規格化されたリードフレーム
のなかから、搭載するチップの大きさに鑑みて適当なダ
イ部分（14）の大きさと放熱特性を有するタイプのリー
ドフレームが選択される。前記規格化されたリードフレ
ームのダイ部分（14）は、更に規格化された外形寸法と
チップサイズの異る複数種類のチップを搭載できるよ
う、また限られた寸法の中で最大寸法のエリアを確保す
る為、リード（15）の延在方向に対して横方向に長い長
方形形状を有する。The lead frame is made up of multiple types of standardized lead frames that have die parts (14) of different sizes in advance, and the size and heat dissipation of the die part (14) appropriate for the size of the chip to be mounted are considered. A type of lead frame with characteristics is selected. The standardized lead frame die part (14) has a maximum dimension area within a limited dimension so that multiple types of chips having different standardized external dimensions and chip sizes can be mounted. In order to secure it, it has a rectangular shape that is long in the lateral direction with respect to the extending direction of the leads (15).
而して、パワートランジスタを構成するトランジスタ
チップ（11）は、高耐圧大電流容量を実現する為例えば
9.0×7.0mmの如き大きなチップサイズとなり、これをダ
イ部分（14）に配置すると残る余白部分はごく限られた
細長い領域となる。Thus, the transistor chip (11) forming the power transistor has a high withstand voltage and a large current capacity, for example,
A large chip size, such as 9.0 x 7.0 mm, is placed on the die part (14), and the remaining blank area is a very narrow and narrow area.
本発明は上記限られた領域に対し、小サイズのダイオ
ードチップ（12）を並設し、ワイヤ（16）で並列接続す
ることによりダンパダイオードとして要求される電流容
量を達成する。ダイオードチップ（12）は一般に小型化
指向の為正方形に近い外観を有し、上記実施例において
も既製のチップサイズが4.0×4.0mmの如きダイオードチ
ップ（12）を使用する。この様な構成によれば、小サイ
ズのダイオードチップ（12）を利用するので、前記限ら
れた領域を有効利用でき、装置の大型化を防止できる。
また、既製のダイオードチップ（12）を利用できるの
で、チップの新規設計が不要である。The present invention achieves the current capacity required as a damper diode by arranging small-sized diode chips (12) in parallel in the limited area and connecting them in parallel with a wire (16). The diode chip (12) generally has an appearance close to a square because it is aimed at downsizing, and the diode chip (12) having an off-the-shelf chip size of 4.0 × 4.0 mm is also used in the above embodiment. With such a configuration, since the small-sized diode chip (12) is used, the limited area can be effectively used, and the device can be prevented from becoming large.
Moreover, since a ready-made diode chip (12) can be used, a new chip design is unnecessary.
ここで既製のトランジスタチップ（11）と装置を第２
図を用いて説明する。同図に示す如く、規格化されたリ
ードフレームのダイ部分（14）にトランジスタチップ
（11）が固着されワイヤ（16）でワイヤボンディングが
成された後主要部を樹脂モールドして製造される。トラ
ンジスタチップ（11）は、規格化されたダイ部分（14）
の形状に対応して、及び寸法が近接して異る大きさの大
小複数種類の規格化リードフレームに搭載できるよう、
横長の長方形形状を有し且つ図示の如く横長に固着され
る。トランジスタチップ（11）の表面には周知のプロセ
ス技術によりトランジスタを構成する拡散領域が形成さ
れ、更にはアルミ層等のホトエッチングによって各電極
及びワイヤボンディング用のベースパッド（17）とエミ
ッタパッド（18）が設けられる。エミッタパッド（18）
は、トランジスタの動作状態を平均化する為パターンが
対称形状となるように複数箇所に設けられる。複数のパ
ッド（18）を同時ボンドする為にはアルミワイヤ（16）
と超音波ボンディングによるステッチボンドが有効であ
り、エミッタパッド（18）はステッチボンド対応の為に
リード（15）の延在方向に対して平行に並べられ、且つ
パッド形状は前記延在方向に縦長の形状を有する。この
様に配置することでトランジスタ特性及びステッチボン
ドによるワイヤボンダビリティを改善する。Here, the off-the-shelf transistor chip (11) and the second device
This will be described with reference to the drawings. As shown in the figure, the transistor chip (11) is fixed to the die portion (14) of the standardized lead frame, wire bonding is performed with the wire (16), and then the main part is molded with resin. Transistor chip (11) has standardized die parts (14)
Corresponding to the shape of, and the size can be mounted on multiple types of standardized lead frames of different sizes close to each other,
It has a horizontally long rectangular shape and is fixed horizontally as shown. Diffusion regions forming transistors are formed on the surface of the transistor chip (11) by a well-known process technique, and further, a base pad (17) and an emitter pad (18) for wire bonding and electrodes are formed by photoetching an aluminum layer or the like. ) Is provided. Emitter pad (18)
Are provided at a plurality of positions so that the patterns have a symmetrical shape in order to average the operating states of the transistors. Aluminum wire (16) to bond multiple pads (18) simultaneously
Stitch bond by ultrasonic bonding is effective, and the emitter pad (18) is arranged parallel to the extending direction of the lead (15) to correspond to the stitch bond, and the pad shape is vertically elongated in the extending direction. Has the shape of. By arranging in this way, transistor characteristics and wire bondability due to stitch bonding are improved.
斯様な既製のトランジスタチップ（11）を本発明装置
に搭載する場合も、第１図に示すようにチップ（11）の
向きは第２図と同様の向きで固着する。更に、トランジ
スタチップ（11）はベース端子用リード（15a）に近い
側へシフトして配置し、ダイオードチップ（12）はエミ
ッタ端子用リード（15b）に近い側へ縦に並べて配置す
る。この様にすれば、リード（15）の延在方向に対し
て、エミッタパッド（18）を結ぶラインとダイオードチ
ップ（12）の夫々のボンディングエリア（パッド）を結
ぶラインを平行に配置でき、その為ワイヤ（16）を極端
に屈折せずに済むのでボンダビリティを損わずにワイヤ
ボンドできる。トランジスタチップ（11）を90度傾けれ
ば、ダイ部分（14）に対してスペースの有効利用ができ
るが、これではアルミワイヤ（16）を90度以上屈折させ
てワイヤボンドすることになるので、ボンダビリティが
極めて劣化する。また、上記配置とすることにより、ベ
ース用のワイヤ（16）とエミッタ用のワイヤ（16）を交
差させずに済む。Even when such an off-the-shelf transistor chip (11) is mounted on the device of the present invention, the chip (11) is fixed in the same orientation as in FIG. 2 as shown in FIG. Further, the transistor chip (11) is shifted and arranged closer to the base terminal lead (15a), and the diode chip (12) is vertically arranged closer to the emitter terminal lead (15b). In this way, the line connecting the emitter pad (18) and the line connecting each bonding area (pad) of the diode chip (12) can be arranged in parallel to the extending direction of the lead (15). Therefore, the wire (16) does not have to be bent extremely, so that wire bonding can be performed without impairing bondability. If the transistor chip (11) is tilted 90 degrees, the space can be effectively used for the die part (14), but this will bend the aluminum wire (16) by 90 degrees or more and wire bond it. Bondability is extremely deteriorated. Further, with the above arrangement, it is not necessary to intersect the base wire (16) and the emitter wire (16).
以下本発明の製造方法について説明する。本願構成の
装置を製造する場合、トランジスタ用SIP型リードフレ
ームを利用するので、トランジスタチップ（11）が単体
で搭載される他機種と同じボンディング装置を利用する
のが簡便である。この様なボンディング装置は１回のフ
ローで１サイズのチップを搭載する能力しか持たないの
が一般的であり、多チップ同時搭載能力を有する装置を
利用するには新たな設備投資を要する。The manufacturing method of the present invention will be described below. When manufacturing the device having the configuration of the present application, since the SIP type lead frame for the transistor is used, it is easy to use the same bonding device as the other model in which the transistor chip (11) is mounted alone. Such a bonding apparatus generally has only the ability to mount one size chip in one flow, and new equipment investment is required to use the apparatus having the simultaneous mounting capacity for multiple chips.
一方、リードフレームの素材は放熱性、価格等の点
で、銅系又は鉄系の如きリードフレームが用いられ、濡
れ性改善の為にその表面にNi等の金属メッキを処したも
のが多い。この様なリードフレームに対し、半田等の材
料でダイボンディングを行うべく数百℃の加熱処理を処
すと、露出した表面が酸化しこれが次のチップの接着性
信頼性を損う要因となる。On the other hand, as the material of the lead frame, a copper-based or iron-based lead frame is used in terms of heat dissipation, price, etc., and in many cases, the surface thereof is plated with a metal such as Ni to improve wettability. When such a lead frame is subjected to a heat treatment at several hundreds of degrees Celsius for die bonding with a material such as solder, the exposed surface is oxidized, which becomes a factor of impairing the adhesive reliability of the next chip.
従って本発明の製造方法は先ず第３図Ａに示す如く、
同じパターンが多数繰り返された短尺状のリードフレー
ム（20）をダイボンド装置のステージ上に載置し、ヒー
タブロックで加熱しながらトランジスタチップ（11）を
半田付けし、これを反復して全てのダイ部分（14）にト
ランジスタチップ（11）を固着し、装置のステージ上か
らリードフレーム（20）を取り出す。次に第３図Ｂに示
す様に、チップ吸着コレット等の設定が異るダイボンデ
ィング装置のステージ上にリードフレーム（20）を移
し、ダイオードチップ（12）を余白ダイ部分（14）に半
田付けし、同様種・同サイズのチップであればもう一度
吸着コレットを動作させて２つのダイオードチップ（1
2）を固着する。続いて第３図Ｃに示すように、ワイヤ
ボンディングを行った後図示せぬ樹脂で主要部を封止し
て製造される。Therefore, as shown in FIG. 3A, the manufacturing method of the present invention is as follows.
A short lead frame (20) in which the same pattern is repeated many times is placed on the stage of the die bonder, and the transistor chip (11) is soldered while being heated by the heater block. The transistor chip (11) is fixed to the portion (14), and the lead frame (20) is taken out from the stage of the device. Next, as shown in FIG. 3B, the lead frame (20) is transferred onto the stage of the die bonding apparatus with different settings such as the chip suction collet, and the diode chip (12) is soldered to the blank die part (14). If the chips of the same type and the same size are used, operate the suction collet once again to operate the two diode chips (1
2) Fix. Subsequently, as shown in FIG. 3C, after wire bonding is performed, the main part is sealed with a resin (not shown) to manufacture.
この構成による方法によれば、ダイ部分（14）表面が
まだ酸化されないうちにトランジスタチップ（11）をダ
イボンドするので、放熱性を重視するトランジスタチッ
プ（11）を高信頼性で接着することができる。一方、ダ
イオードチップ（12）はトランジスタチップ（11）より
は放熱性を重視せずに済むので、前記酸化膜形成が容認
できる。従って、全体として高い信頼性を持つ装置を組
み立てることができる。According to the method with this configuration, the transistor chip (11) is die-bonded before the surface of the die part (14) is yet to be oxidized, so that the transistor chip (11) that attaches importance to heat dissipation can be bonded with high reliability. . On the other hand, since the diode chip (12) does not need to give more importance to heat dissipation than the transistor chip (11), the formation of the oxide film is acceptable. Therefore, it is possible to assemble a device having high reliability as a whole.
（ト）発明の効果 以上説明した如く本発明によれば、まず第１に小さい
サイズのダイオードチップ（12）を並列接続するので、
設計自由度を大きくでき、トランジスタチップ（11）に
より制限されたダイ部分（14）の余白にダイオードチッ
プ（12）を効率的に無駄なく配置できる利点を有する。
従って、所望の耐圧と電流容量を達成したダンパダイオ
ードを効率的に１パッケージ化できる。(G) Effect of the Invention As described above, according to the present invention, first, the diode chips (12) having a small size are connected in parallel.
This has the advantage that the degree of freedom in design can be increased and the diode chip (12) can be efficiently and efficiently arranged in the margin of the die portion (14) limited by the transistor chip (11).
Therefore, the damper diode that achieves the desired breakdown voltage and current capacity can be efficiently packaged in one package.
第２に、エミッタパッド（18）を結ぶラインとダイオ
ードチップ（12）を結ぶラインとをリード（15）の延在
方向に対して夫々平行となるように各チップを配置した
ので、ボンダビリティを損うこと無くワイヤボンドがで
きる利点を有する。Secondly, since the chips are arranged such that the line connecting the emitter pads (18) and the line connecting the diode chips (12) are parallel to the extending direction of the leads (15), bondability is improved. It has an advantage that wire bonding can be performed without damage.
第３に、トランジスタチップ（11）を先にダイボンド
することにより、全体として接着信頼性の高い装置を製
造できる利点をも有する。Thirdly, by die-bonding the transistor chip (11) first, there is an advantage that a device with high adhesion reliability can be manufactured as a whole.
さらに本発明によれば、トランジスタチップ（11）、
ダイオードチップ（12）、リードフレーム（20）、更に
はボンディング装置までをも既製の製品を利用できるの
で、新規設備投資が全く必要無く、即生産態勢に移行で
きる利点をも有する。Further according to the invention, the transistor chip (11),
Since the ready-made products can be used for the diode chip (12), the lead frame (20), and even the bonding device, there is an advantage that no new capital investment is required and the production system can be immediately started.
第１図は本発明を説明する為の平面図、第２図は既製品
を説明する為の平面図、第３図Ａ乃至第３図Ｃは本発明
を説明する為の平面図、第４図は従来例を説明する為の
回路図である。1 is a plan view for explaining the present invention, FIG. 2 is a plan view for explaining an off-the-shelf product, and FIGS. 3A to 3C are plan views for explaining the present invention. The figure is a circuit diagram for explaining a conventional example.
Claims (2)
ジスタチップと複数個のダイオードチップとを載置した
半導体装置であって、 前記トランジスタチップの表面に同一電位に接続すべき
複数個のボンディングパッドが設けられ、且つ前記複数
個のボンディングパッドがリードの延在方向と平行に並
ぶような向きに前記トランジスタチップを固着し、 前記ダイオードチップの夫々の表面に前記同一電位に接
続すべきボンディングパッドが設けられ、且つ前記ダイ
部分の前記同一電位に対応するリードに近接した位置に
前記リードの延在方向と平行に並ぶようにして前記複数
個のダイオードチップを固着し、 前記トランジスタチップの複数個のボンディングパッド
と前記同一電位に対応するリードとを１本のワイヤで接
続し、 前記ダイオードチップの夫々のボンディングパッドと前
記同一電位に対応するリードとを前記トランジスタチッ
プのワイヤとは独立した１本のワイヤで接続し、 主要部を樹脂モールドしたことを特徴とするダイオード
チップ内蔵型半導体装置。1. A semiconductor device in which a transistor chip and a plurality of diode chips are mounted on a common die part of a SIP type semiconductor device, and a plurality of bonding pads to be connected to the same potential on the surface of the transistor chip. And the plurality of bonding pads are fixed to the transistor chip in a direction such that the plurality of bonding pads are arranged in parallel to the extending direction of the leads, and bonding pads to be connected to the same potential are provided on the respective surfaces of the diode chip. The plurality of diode chips are fixed to the die portion at a position close to the leads corresponding to the same potential so as to be arranged parallel to the extending direction of the leads, The bonding pad and the lead corresponding to the same potential are connected by one wire, and the diode A semiconductor device with a built-in diode chip, characterized in that each bonding pad of the chip and the lead corresponding to the same potential are connected by one wire independent of the wire of the transistor chip, and the main part is resin-molded. .
ップは単体封止される他機種のものと同一パターンを有
するチップであり且つ前記トランジスタチップはリード
の延在方向に対して他機種のものと同じ向きで固着する
ことを特徴とする請求項第１項に記載のダイオードチッ
プ内蔵型半導体装置の製造方法。2. The transistor chip and the diode chip are chips that have the same pattern as those of other models that are individually sealed, and the transistor chip is in the same direction as that of other models with respect to the extending direction of the leads. The method for manufacturing a semiconductor device with a built-in diode chip according to claim 1, wherein the semiconductor device is fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63286932A JP2692904B2 (en) | 1988-11-14 | 1988-11-14 | Semiconductor device with built-in diode chip and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63286932A JP2692904B2 (en) | 1988-11-14 | 1988-11-14 | Semiconductor device with built-in diode chip and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02132849A JPH02132849A (en) | 1990-05-22 |
| JP2692904B2 true JP2692904B2 (en) | 1997-12-17 |
Family
ID=17710826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63286932A Expired - Fee Related JP2692904B2 (en) | 1988-11-14 | 1988-11-14 | Semiconductor device with built-in diode chip and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2692904B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61288454A (en) * | 1985-06-17 | 1986-12-18 | Sharp Corp | Lead frame of semiconductor device provided with multiple chip |
| JPS63142844A (en) * | 1986-12-06 | 1988-06-15 | Toshiba Corp | Semiconductor device |
-
1988
- 1988-11-14 JP JP63286932A patent/JP2692904B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02132849A (en) | 1990-05-22 |
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