JP2000156464A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000156464A
JP2000156464A JP10330452A JP33045298A JP2000156464A JP 2000156464 A JP2000156464 A JP 2000156464A JP 10330452 A JP10330452 A JP 10330452A JP 33045298 A JP33045298 A JP 33045298A JP 2000156464 A JP2000156464 A JP 2000156464A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead
semiconductor
main surface
sealing body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10330452A
Other languages
Japanese (ja)
Inventor
Tamaki Wada
環 和田
Masachika Masuda
正親 増田
Takuji Ide
琢二 井手
Shunichiro Fujioka
俊一郎 藤岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP10330452A priority Critical patent/JP2000156464A/en
Publication of JP2000156464A publication Critical patent/JP2000156464A/en
Withdrawn legal-status Critical Current

Links

Classifications

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01—ELECTRIC ELEMENTS
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To laminate a plurality of semiconductor chips, sealing them with a resin-sealing body, and make thin a semiconductor device by adhering and fixing first and second semiconductor chips while the surface and backside face each other and the positions are shifted in the direction that orthogonally crosses the arrangement direction of an electrode. SOLUTION: Semiconductor chips 4 and 5 are adhered and fixed via an adhesive layer 7 while the backsides face each other so that the other long side 4A2 of the semiconductor chips and one long side 5A1 face the side of a lead 10B. Then, the laminates of the semiconductor chips 4 and 5 are supported by a support lead 8, and the support lead 8 is adhered and fixed to a main surface 4A of the semiconductor chip 4 via the adhesive layer 8. As a result, no tabs exist between the semiconductor chips 4 and 5 and at the same time only one adhesive layer exists, thus reducing distance from the main surface 4A of the semiconductor chip to a main surface 5A.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、二つの半導体チップを積層
し、この二つの半導体チップを一つの樹脂封止体で封止
する半導体装置の製造方法に適用して有効な技術に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a semiconductor device in which two semiconductor chips are stacked and the two semiconductor chips are sealed with one resin sealing body. It is related to technology that is effective when applied to

【０００２】[0002]

【従来の技術】記憶回路システムの大容量化を図る目的
として、記憶回路システムが構成された二つの半導体チ
ップを積層し、この二つの半導体チップを一つの樹脂封
止体で封止する積層型半導体装置が提案されている。例
えば、特開平７−５８２８１号公報にはＬＯＣ（Ｌead
Ｏn Ｃhip)構造の積層型半導体装置が開示されている。
また、特開平４−３０２１６５号公報にはタブ構造の積
層型半導体装置が開示されている。2. Description of the Related Art Purpose of increasing the capacity of a storage circuit system
As two semiconductor chips with a memory circuit system
The two semiconductor chips are sealed with one resin.
A stacked semiconductor device sealed with a stopper has been proposed. An example
For example, Japanese Unexamined Patent Publication No. 7-58281 discloses LOC (Lead
OnCA stacked semiconductor device having a hip) structure is disclosed.
Japanese Patent Application Laid-Open No. 4-302165 discloses a product having a tab structure.
A layer type semiconductor device is disclosed.

【０００３】ＬＯＣ構造の積層型半導体装置は、表裏面
のうちの表面である回路形成面に複数の外部電極（パッ
ド）が形成された第１半導体チップ及び第２半導体チッ
プと、第１半導体チップの回路形成面に絶縁性フィルム
を介在して接着固定されると共に、その回路形成面の外
部電極（以下、単に電極と称す）に導電性のワイヤを介
して電気的に接続される複数の第１リードと、第２半導
体チップの回路形成面（以下、単に主面と称する）に絶
縁性フィルムを介在して接着固定されると共に、その主
面の電極に導電性のワイヤを介して電気的に接続される
複数の第２リードと、第１半導体チップ、第２半導体チ
ップ、第１リードのインナー部、第２リードのインナー
部及びワイヤ等を封止する樹脂封止体とを有する構成に
なっている。第１半導体チップ、第２半導体チップの夫
々は、夫々の主面を互いに対向させた状態で積層されて
いる。第１リード、第２リードの夫々は、夫々の接続部
を互いに重ね合わせた状態で接合されている。A stacked semiconductor device having a LOC structure includes a first semiconductor chip and a second semiconductor chip having a plurality of external electrodes (pads) formed on a circuit forming surface which is a front surface and a back surface, and a first semiconductor chip. And a plurality of first electrodes electrically connected to external electrodes (hereinafter simply referred to as electrodes) on the circuit forming surface via conductive wires, while being insulated and fixed to the circuit forming surface via an insulating film. The first lead and the circuit forming surface of the second semiconductor chip (hereinafter simply referred to as the main surface) are bonded and fixed with an insulating film interposed therebetween, and electrically connected to the electrodes on the main surface via conductive wires. Having a plurality of second leads connected to the semiconductor chip, a first semiconductor chip, a second semiconductor chip, an inner portion of the first lead, an inner portion of the second lead, a resin sealing body for sealing the wires and the like. Has become. The first semiconductor chip and the second semiconductor chip are stacked with their main surfaces facing each other. Each of the first lead and the second lead is joined in a state where respective connecting portions are overlapped with each other.

【０００４】タブ構造の積層型半導体装置は、タブ（ダ
イパッドとも言う）の表裏面のうちの表面に接着層を介
して固定される第１半導体チップと、タブの裏面に接着
層を介して固定される第２半導体チップと、第１半導体
チップ、第２半導体チップのうち何れか一方の半導体チ
ップの電極に導電性のワイヤを介して電気的に接続され
る複数の専用リードと、第１半導体チップ、第２半導体
チップの夫々の電極に導電性のワイヤを介して電気的に
接続される複数の共通リードと、第１半導体チップ、第
２半導体チップ、専用リードのインナー部、共通リード
のインナー部及びワイヤ等を封止する樹脂封止体とを有
する構成になっている。第１半導体チップ、第２半導体
チップの夫々の電極は、主面において互いに対向する二
つの長辺側に夫々の長辺に沿って形成されている。専用
リード、共用リードの夫々は、半導体チップの二つの長
辺の夫々の外側に配置されている。A stacked semiconductor device having a tab structure includes a first semiconductor chip fixed to the front surface and back surface of a tab (also referred to as a die pad) via an adhesive layer, and fixed to the back surface of the tab via an adhesive layer. A second semiconductor chip, a plurality of dedicated leads electrically connected to electrodes of one of the first semiconductor chip and the second semiconductor chip via a conductive wire, and a first semiconductor chip. A plurality of common leads electrically connected to respective electrodes of the chip and the second semiconductor chip via conductive wires, an inner portion of the first semiconductor chip, the second semiconductor chip, the dedicated lead, and an inner portion of the common lead; And a resin sealing body for sealing the parts and wires. The respective electrodes of the first semiconductor chip and the second semiconductor chip are formed along the long sides on two long sides facing each other on the main surface. Each of the dedicated lead and the shared lead is disposed outside each of the two long sides of the semiconductor chip.

【０００５】[0005]

【発明が解決しようとする課題】本発明者等は、積層型
半導体装置の開発に先立ち、以下の問題点に直面した。
ＬＯＣ構造では二枚のリードフレームを用いて製造する
ため、製造コストが高くなる。一方、タブ構造では一枚
のリードフレームで製造することができるが、ミラー反
転回路パターンの半導体チップを用いる必要があるた
め、タブ構造においても製造コストが高くなる。タブ構
造では、タブの表裏面に夫々の裏面が向い合うようにし
て二つの半導体チップを塔載するため、主面の互いに対
向する二つの長辺の夫々の辺側に電極を形成する場合、
上側の半導体チップの電極に対して下側の半導体チップ
の電極が左右逆になる。Prior to the development of the stacked semiconductor device, the present inventors faced the following problems.
Since the LOC structure is manufactured using two lead frames, the manufacturing cost increases. On the other hand, although the tab structure can be manufactured with one lead frame, the manufacturing cost is increased also in the tab structure because a semiconductor chip having a mirror inversion circuit pattern needs to be used. In the tab structure, in order to mount two semiconductor chips so that the respective back surfaces face the front and back surfaces of the tab, when forming an electrode on each of the two long sides of the main surface opposed to each other,
The electrodes of the lower semiconductor chip are reversed left and right with respect to the electrodes of the upper semiconductor chip.

【０００６】そこで、一辺側に電極が形成された二つの
半導体チップを使用し、一方の半導体チップの一辺側が
他方の半導体チップの一辺側に対して反対側に位置する
ように二つの半導体チップをタブの表裏面に塔載するこ
とにより、ミラー反転回路パターンの半導体チップが不
要になるので、タブ構造における製造コストの低減化を
図ることができる。Accordingly, two semiconductor chips having electrodes formed on one side are used, and the two semiconductor chips are arranged such that one side of one semiconductor chip is located on the opposite side to one side of the other semiconductor chip. By mounting on the front and back surfaces of the tab, a semiconductor chip having a mirror inversion circuit pattern is not required, so that the manufacturing cost of the tab structure can be reduced.

【０００７】しかしながら、タブ構造では樹脂封止体の
厚さが厚くなり、樹脂封止体の厚さが１．０〜１．１ｍ
ｍ厚のＴＳＯＰ（Ｔhin Ｓmall Ｏutline Ｐackage）型
で積層型半導体装置を構成することが困難である。即
ち、タブ構造では、タブの表面及び裏面に半導体チップ
を塔載する構成になっていることから、上側の半導体チ
ップと下側の半導体チップとの間にタブが存在し、上側
の半導体チップの主面から下側の半導体チップの主面ま
での距離が増加するので、樹脂封止体の厚さが厚くな
る。更に、タブの表面及び裏面に半導体チップを塔載す
る構成になっていることから、上側の半導体チップと下
側の半導体チップとの間に二つの接着層が存在し、上側
の半導体チップの主面から下側の半導体チップの主面ま
での距離が増加するので、樹脂封止体の厚さが厚くな
る。本発明者等の検討によれば、半導体チップの厚さを
０．１７２５〜０．２ｍｍに薄くすることにより、樹脂
封止体の厚さを１．０〜１．１ｍｍ以下にすることがで
きるが、このような場合、半導体チップの機械的強度が
低下するので、半導体チップに亀裂、破損等の不具合が
発生し易くなる。特に、半導体ウエーハを複数のチップ
に分割するダイシング工程時や、タブに半導体チップを
塔載するダイボンディング工程時に多発する。However, in the tab structure, the thickness of the resin sealing body is large, and the thickness of the resin sealing body is 1.0 to 1.1 m.
it is difficult to constitute a stacked semiconductor device in m thick TSOP (T hin S mall O utline P ackage) type. That is, since the tab structure has a configuration in which the semiconductor chips are mounted on the front surface and the back surface of the tab, a tab exists between the upper semiconductor chip and the lower semiconductor chip, and the upper semiconductor chip has Since the distance from the main surface to the main surface of the lower semiconductor chip increases, the thickness of the resin sealing body increases. Further, since the semiconductor chip is mounted on the front and back surfaces of the tab, two adhesive layers exist between the upper semiconductor chip and the lower semiconductor chip, and the main chip of the upper semiconductor chip is provided. Since the distance from the surface to the main surface of the lower semiconductor chip increases, the thickness of the resin sealing body increases. According to the study by the present inventors, by reducing the thickness of the semiconductor chip to 0.1725 to 0.2 mm, the thickness of the resin sealing body can be reduced to 1.0 to 1.1 mm or less. However, in such a case, the mechanical strength of the semiconductor chip is reduced, so that the semiconductor chip is liable to be broken or broken. In particular, it frequently occurs in a dicing process of dividing a semiconductor wafer into a plurality of chips or in a die bonding process of mounting a semiconductor chip on a tab.

【０００８】また、タブ構造では、半導体チップの電極
とワイヤとの接続不良が発生し易い。即ち、タブの表面
及び裏面に半導体チップを塔載した後ではタブをヒート
ステージに接触させることが困難であるため、ヒートス
テージの熱が有効に伝達されず、半導体チップの電極と
ワイヤとの接続不良が発生し易い。In the tab structure, a connection failure between the electrode of the semiconductor chip and the wire is likely to occur. That is, after the semiconductor chip is mounted on the front and back surfaces of the tab, it is difficult to bring the tab into contact with the heat stage, so that the heat of the heat stage is not effectively transmitted, and the connection between the electrode of the semiconductor chip and the wire is made. Failure is likely to occur.

【０００９】本発明の目的は、二つの半導体チップを積
層し、この二つの半導体チップを一つの樹脂封止体で封
止する半導体装置の薄型化を図ることが可能な技術を提
供することにある。本発明の他の目的は、二つの半導体
チップを積層し、この二つの半導体チップを一つの樹脂
封止体で封止する半導体装置において、リードフレーム
一個で二つの半導体チップに設けられた電極に対応する
ことが可能な技術を提供することにある。An object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device in which two semiconductor chips are stacked and the two semiconductor chips are sealed with one resin sealing body. is there. Another object of the present invention is to provide a semiconductor device in which two semiconductor chips are stacked and the two semiconductor chips are sealed with one resin sealing body, and one lead frame is used for electrodes provided on the two semiconductor chips. It is to provide a technology that can respond.

【００１０】本発明の他の目的は、半導体装置の組立工
程における作業性を向上することが可能な技術を提供す
ることにある。本発明の前記ならびにその他の目的と新
規な特徴は、本明細書の記述及び添付図面によって明ら
かになるであろう。Another object of the present invention is to provide a technique capable of improving workability in a process of assembling a semiconductor device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１１】[0011]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。 （１）方形状の半導体基板の主面の第一辺に沿って複数
の電極（パッド）が配列された第１及び第２の２つの半
導体チップを準備する工程と、前記第１及び第２の半導
体チップの夫々を、前記第１半導体チップの第１辺と前
記第２半導体チップの第１辺とが反対側になるように、
前記主面と反対側の面（裏面）同志を向い合せ、かつ前
記電極の配列方向と直交する方向に位置をずらした積層
状態で接着固定する工程と、該接着固定された第１及び
第２の半導体チップの積層体の前記第１半導体チップの
主面に支持リードを接着固定する工程と、前記第１半導
体チップの各電極と表面識別記号のリードフレームのリ
ードのインナー部とを導電性のワイヤを介して電気的に
接続する工程と、前記第２半導体チップの各電極と裏面
識別記号のリードフレームのリードのインナー部とを導
電性のワイヤを介して電気的に接続する工程と、前記第
１及び第２の半導体チップ、ワイヤならびにリードのイ
ンナー部を樹脂により封止する工程とを備えた半導体装
置の製造方法である。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) a step of preparing first and second two semiconductor chips on each of which a plurality of electrodes (pads) are arranged along a first side of a main surface of a rectangular semiconductor substrate; Each of the semiconductor chips described above such that the first side of the first semiconductor chip is opposite to the first side of the second semiconductor chip.
Adhering and fixing in a laminated state in which the surfaces opposite to the main surface (back surface) face each other and are displaced in a direction orthogonal to the arrangement direction of the electrodes; and the first and second adhering and fixing. Bonding a support lead to the main surface of the first semiconductor chip of the semiconductor chip laminate, and connecting each electrode of the first semiconductor chip and the inner part of the lead of the lead frame of the surface identification symbol to each other. Electrically connecting via a wire, electrically connecting each electrode of the second semiconductor chip and the inner part of the lead of the lead frame of the back surface identification symbol via a conductive wire, Sealing the inner portions of the first and second semiconductor chips, wires, and leads with a resin.

【００１２】（２）前記支持リードは、電源リード又は
ＧＮＤリードと兼用する構造である。 （３）前記支持リードの接着固定位置がリードの高さと
同一平面にある。 （４）前記リードのアウタリードは、前記樹脂封止体の
厚さ方向において、樹脂封止体の中心線を含む水平平面
よりも上方向の位置に設けられている。(2) The support lead has a structure that also serves as a power supply lead or a GND lead. (3) The fixing position of the support lead is on the same plane as the height of the lead. (4) The outer lead of the lead is provided at a position above a horizontal plane including a center line of the resin sealing body in a thickness direction of the resin sealing body.

【００１３】[0013]

【発明の実施の形態】以下、図面を参照して本発明の実
施の形態（実施例）を詳細に説明する。なお、発明の実
施の形態を説明するための全図において、同一機能を有
するものは同一符号を付け、その繰り返しの説明は省略
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments (examples) of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

【００１４】（実施形態１）本実施形態では、二方向リ
ード配列構造であるＴＳＯＰ型の半導体装置に本発明を
適用した例について説明する。図１は本発明の実施形態
（実施例）１である半導体装置の樹脂封止体の上部を除
去した状態の平面図、図２は前記半導体装置の樹脂封止
体の下部を除去した状態の底面図、図３は図１のＡ−Ａ
線に沿う模式的断面図、図４は図１のＢ−Ｂ線に沿う模
式的断面図である。なお、図１及び図２において、図１
に示す左側のリード群は図２に示す右側のリード群と対
応し、図１に示す右側のリード群は図２に示す左側のリ
ード群と対応する。(Embodiment 1) In this embodiment, an example in which the present invention is applied to a TSOP type semiconductor device having a two-way lead array structure will be described. FIG. 1 is a plan view showing a state in which an upper part of a resin sealing body of a semiconductor device according to an embodiment (example) 1 of the present invention is removed, and FIG. 2 is a state in which a lower part of the resin sealing body of the semiconductor device is removed. FIG. 3 is a bottom view, and FIG.
FIG. 4 is a schematic sectional view taken along line BB of FIG. 1. 1 and FIG.
2 corresponds to the right-side lead group shown in FIG. 2, and the right-side lead group shown in FIG. 1 corresponds to the left-side lead group shown in FIG.

【００１５】図１、図２及び図３に示すように、本実施
形態の半導体装置１は、半導体基板の主面（表面）を有
する第１半導体チップ４を第２半導体チップ５の上に積
層し、この第１半導体チップ４及び第２半導体チップ５
を一つの樹脂封止体１２で封止した構成になっている。As shown in FIGS. 1, 2 and 3, a semiconductor device 1 of the present embodiment has a first semiconductor chip 4 having a main surface (front surface) of a semiconductor substrate laminated on a second semiconductor chip 5. The first semiconductor chip 4 and the second semiconductor chip 5
Is sealed with one resin sealing body 12.

【００１６】前記第１半導体チップ４及び５は、前記第
１半導体チップ４の第１辺と前記第２半導体チップ５の
第１辺とが反対側になるように主面（表面）と反対側の
面（裏面）同志を向い合せ、かつ前記電極の配列方向と
直交する方向に位置をずらした積層状態で接着固定され
ている。前記第１半導体チップ４及び５の夫々は、同一
の外形寸法で形成されている。また、半導体チップ４、
５の夫々の平面形状は方形状で形成され、本実施形態に
おいては、例えば長方形で形成されている。The first semiconductor chips 4 and 5 are opposite to the main surface (front surface) such that the first side of the first semiconductor chip 4 is opposite to the first side of the second semiconductor chip 5. Are fixed in a laminated state with their surfaces (back surfaces) facing each other and shifted in the direction perpendicular to the direction in which the electrodes are arranged. Each of the first semiconductor chips 4 and 5 has the same outer dimensions. Also, the semiconductor chip 4,
5 is formed in a square shape, and in the present embodiment, is formed in, for example, a rectangular shape.

【００１７】半導体チップ４、５の夫々は、例えば、単
結晶珪素からなる半導体基板及びこの半導体基板上に形
成された多層配線層を主体とする構成になっている。こ
の半導体チップ４、５の夫々には、記憶回路システムと
して、例えばフラッシュメモリと呼称される６４メガビ
ットのＥＥＰＲＯＭ（Ｅlectrically Ｅrasable Ｐrogr
ammable Ｒead Ｏnly Ｍemory)が構成されている。Each of the semiconductor chips 4 and 5 has, for example, a configuration in which a semiconductor substrate made of, for example, single crystal silicon and a multilayer wiring layer formed on the semiconductor substrate are mainly used. The respective semiconductor chips 4 and 5, as the storage circuit system, for example of 64 Mbit called a flash memory EEPROM (E lectrically E rasable P rogr
ammable R ead O nly M emory) it is formed.

【００１８】半導体チップ４の表裏面のうちの表面であ
る主面４Ａにおいて、その互いに対向する二つの長辺の
うちの一方の長辺４Ａ１側にこの一方の長辺４Ａ１に沿
って複数の電極（ボンディングパッド）６が形成されて
いる（図１及び図３参照）。この複数の電極６の夫々
は、半導体チップ４の多層配線層のうちの最上層の配線
層に形成されている。最上層の配線層はその上層に形成
された表面保護膜（最終保護膜）で被覆され、この表面
保護膜には電極６の表面を露出するボンディング開口が
形成されている。On the main surface 4A, which is the front surface of the front and back surfaces of the semiconductor chip 4, a plurality of electrodes are formed along one long side 4A1 of one of the two long sides facing each other. A (bonding pad) 6 is formed (see FIGS. 1 and 3). Each of the plurality of electrodes 6 is formed on the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 4. The uppermost wiring layer is covered with a surface protective film (final protective film) formed thereon, and a bonding opening for exposing the surface of the electrode 6 is formed in the surface protective film.

【００１９】半導体チップ５の表裏面のうちの表面であ
る主面５Ａにおいて、その互いに対向する二つの長辺の
うちの一方の長辺５Ａ１側にこの一方の長辺５Ａ１に沿
って複数の電極６が形成されている（図２及び図３参
照）。この複数の電極６の夫々は、半導体チップ４の多
層配線層のうちの最上層の配線層に形成されている。最
上層の配線層はその上層に形成された表面保護膜（最終
保護膜）で被覆され、この表面保護膜には電極６の表面
を露出するボンディング開口が形成されている。On the main surface 5A, which is the front surface of the front and back surfaces of the semiconductor chip 5, a plurality of electrodes are formed along one long side 5A1 on one of the two long sides facing each other. 6 are formed (see FIGS. 2 and 3). Each of the plurality of electrodes 6 is formed on the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 4. The uppermost wiring layer is covered with a surface protective film (final protective film) formed thereon, and a bonding opening for exposing the surface of the electrode 6 is formed in the surface protective film.

【００２０】半導体チップ４に構成されたフラッシュメ
モリの回路パターンは、半導体チップ５に構成されたフ
ラッシュメモリの回路パターンと同一になっている。ま
た、半導体チップ４の主面４Ａ１に形成された電極６の
配置パターンは、半導体チップ５の主面５Ａ１に形成さ
れた電極６の配置パターンと同一になっている。即ち、
半導体チップ４、半導体チップ５の夫々は、同一構造で
構成されている。The circuit pattern of the flash memory configured on the semiconductor chip 4 is the same as the circuit pattern of the flash memory configured on the semiconductor chip 5. The arrangement pattern of the electrodes 6 formed on the main surface 4A1 of the semiconductor chip 4 is the same as the arrangement pattern of the electrodes 6 formed on the main surface 5A1 of the semiconductor chip 5. That is,
Each of the semiconductor chip 4 and the semiconductor chip 5 has the same structure.

【００２１】樹脂封止体１２の平面形状は方形状で形成
され、本実施形態１においては例えば長方形で形成され
ている（図１、図２参照）。この樹脂封止体１２の互い
に対向する二つの長辺のうちの一方の長辺側にはこの一
方の長辺に沿って複数のリード１０Ａが配列され、他方
の長辺側にはこの他方の長辺に沿って複数のリード１０
Ｂが配列されている。複数のリード１０Ａの夫々は、樹
脂封止体１２の内外に亘って延在し、半導体チップ４の
長辺４Ａ１の外側に配置され、かつ半導体チップ４の各
電極６に導電性のワイヤ１１を介して電気的に接続され
ている（図１及び図３参照）。複数のリード１０Ｂの夫
々は、樹脂封止体１２の内外に亘って延在し、半導体チ
ップ４の長辺４Ａ１と対向する他の長辺４Ａ２の外側に
配置され、かつ半導体チップ５の各電極６に導電性のワ
イヤ１１を介して電気的に接続されている。The planar shape of the resin sealing body 12 is formed in a square shape, and in the first embodiment is formed in, for example, a rectangular shape (see FIGS. 1 and 2). A plurality of leads 10A are arranged along one long side of one of the two long sides of the resin sealing body 12 facing each other. Multiple leads 10 along the long side
B are arranged. Each of the plurality of leads 10 </ b> A extends inside and outside the resin sealing body 12, is disposed outside the long side 4 </ b> A <b> 1 of the semiconductor chip 4, and has a conductive wire 11 attached to each electrode 6 of the semiconductor chip 4. (See FIGS. 1 and 3). Each of the plurality of leads 10 </ b> B extends inside and outside the resin sealing body 12, is arranged outside the other long side 4 </ b> A <b> 2 facing the long side 4 </ b> A <b> 1 of the semiconductor chip 4, and is connected to each electrode of the semiconductor chip 5. 6 is electrically connected through a conductive wire 11.

【００２２】複数のリード１０Ａ、１０Ｂの夫々には端
子名が付されている。ＶＣＣ端子は電源電位（例えば５
ボルト）に電位固定される電源電位端子である。ＶＳＳ
端子は基準電位（例えば０ボルト）に電位固定される基
準電位端子である。Ｉ／Ｏの０端子〜７端子はデータ入
出力端子である。ＲＥＳ端子はリセット端子である。Ｒ
／Ｂ端子はリーディ／ビズィ端子である。ＣＤＥ端子は
コマンド・データ・イネーブル端子である。ＯＥ端子は
出力イネーブル端子である。ＳＣ端子はシリアル・クロ
ック端子である。ＷＥはライト・イネーブル端子であ
る。ＣＥはチップ・イネーブル端子である。ＮＣ端子は
空き端子である。Each of the leads 10A and 10B is assigned a terminal name. The VCC terminal is connected to the power supply potential (for example, 5
(Volts). VSS
The terminal is a reference potential terminal fixed at a reference potential (for example, 0 volt). Terminals 0 to 7 of the I / O are data input / output terminals. The RES terminal is a reset terminal. R
The / B terminal is a ready / busy terminal. The CDE terminal is a command data enable terminal. The OE terminal is an output enable terminal. The SC terminal is a serial clock terminal. WE is a write enable terminal. CE is a chip enable terminal. The NC terminal is an empty terminal.

【００２３】半導体チップ４、５の夫々は、半導体チッ
プ４の他方の長辺４Ａ２及び半導体チップ５の一方の長
辺５Ａ１がリード１０Ｂ側に向く（位置する）ように夫
々の裏面同志を向い合わせた状態で接着層７を介在して
互いに接着固定されている。即ち、半導体チップ４、５
の夫々は、電極６が配列された夫々の辺が反対側に位置
するように、夫々の裏面同志を向い合わせた状態で互い
に接着固定され、積層構造になっている。また、半導体
チップ４、５の積層体は支持リード８に支持されてい
る。支持リード８は、半導体チップ４の主面（表面）４
Ａに接着層８を介在して接着固定されている。The semiconductor chips 4 and 5 face each other so that the other long side 4A2 of the semiconductor chip 4 and the one long side 5A1 of the semiconductor chip 5 face (position) the lead 10B side. In this state, they are bonded and fixed to each other with the adhesive layer 7 interposed therebetween. That is, the semiconductor chips 4 and 5
Are bonded and fixed to each other with their back surfaces facing each other such that the respective sides on which the electrodes 6 are arranged are located on opposite sides, and have a laminated structure. The stacked body of the semiconductor chips 4 and 5 is supported by the support leads 8. The support lead 8 is provided on the main surface (front surface) 4 of the semiconductor chip 4.
A is fixedly bonded to A with an adhesive layer 8 interposed therebetween.

【００２４】このことから、半導体チップ４と半導体チ
ップ５との間にはタブが存在しないので、半導体チップ
４の主面４Ａから半導体チップ５の主面５Ａ（表面）ま
での距離を縮小することができる。また、半導体チップ
４と半導体チップ５との間には一つの接着層しか存在し
ないので、半導体チップ４の主面４Ａから半導体チップ
５の主面５Ａまでの距離を縮小することができる。ま
た、支持リード８は半導体チップ４の主面４Ａに接着固
定されているので、支持リード８の厚さは半導体チップ
４の電極６とリード１０Ａとを電気的に接続するワイヤ
１１のループ高さで相殺され、支持リード８による樹脂
封止体１２の厚さへの影響はない。From this, since there is no tab between the semiconductor chip 4 and the semiconductor chip 5, the distance from the main surface 4A of the semiconductor chip 4 to the main surface 5A (front surface) of the semiconductor chip 5 can be reduced. Can be. Further, since only one adhesive layer exists between the semiconductor chip 4 and the semiconductor chip 5, the distance from the main surface 4A of the semiconductor chip 4 to the main surface 5A of the semiconductor chip 5 can be reduced. Since the support lead 8 is bonded and fixed to the main surface 4A of the semiconductor chip 4, the thickness of the support lead 8 is equal to the loop height of the wire 11 for electrically connecting the electrode 6 of the semiconductor chip 4 and the lead 10A. And there is no effect of the support leads 8 on the thickness of the resin sealing body 12.

【００２５】半導体チップ４、５の夫々は、半導体チッ
プ４の電極６が半導体チップ５の一方の長辺５Ａ１と対
向する他方の長辺５Ａ２よりもその外側に位置し、半導
体チップ５の電極６が半導体チップ４の他方の長辺４Ａ
２よりもその外側に位置するように夫々の位置をずらし
た状態で接着固定されている。即ち、半導体チップ４、
半導体チップ５の夫々は、電極６の配列方向に対して直
行する方向に夫々の位置をずらした状態で接着固定され
ている。In each of the semiconductor chips 4 and 5, the electrode 6 of the semiconductor chip 4 is located outside the other long side 5A2 facing one long side 5A1 of the semiconductor chip 5, and the electrode 6 of the semiconductor chip 5 Is the other long side 4A of the semiconductor chip 4
They are bonded and fixed with their respective positions shifted so as to be located outside of the position 2. That is, the semiconductor chip 4,
Each of the semiconductor chips 5 is bonded and fixed in such a manner that their positions are shifted in a direction perpendicular to the arrangement direction of the electrodes 6.

【００２６】リード１０Ａ及びリード１０Ｂは、樹脂封
止体１２で封止されるインナー部（内部リード部）と樹
脂封止体１２の外部に導出されるアウター部（外部リー
ド部）とで構成され、アウター部は面実装型形状として
例えばガルウィング形状に成形されている。The leads 10A and 10B are composed of an inner portion (internal lead portion) sealed by the resin sealing body 12 and an outer portion (external lead portion) led out of the resin sealing body 12. The outer portion is formed into a gull wing shape as a surface mount type shape.

【００２７】導電性のワイヤ１１としては例えば金（Ａ
ｕ）ワイヤが用いられている。ワイヤ１１の接続方法と
しては、例えば熱圧着に超音波振動を併用したボンディ
ング法を用いている。As the conductive wire 11, for example, gold (A
u) Wire is used. As a connection method of the wire 11, for example, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

【００２８】樹脂封止体１２は、低応力化を図る目的と
して、例えば、フェノール系硬化剤、シリコーンゴム及
びフィラー等が添加されたビフェニール系の樹脂で形成
されている。この樹脂封止体１２は、大量生産に好適な
トランスファモールディング法で形成されている。トラ
ンスファモールディング法は、ポット、ランナー、流入
ゲート及びキャビティ等を備えたモールド金型を使用
し、ポットからランナー及び流入ゲートを通してキャビ
ティ内に樹脂を加圧注入して樹脂封止体を形成する方法
である。The resin sealing body 12 is made of, for example, a biphenyl-based resin to which a phenol-based curing agent, silicone rubber, a filler and the like are added for the purpose of reducing stress. This resin sealing body 12 is formed by a transfer molding method suitable for mass production. The transfer molding method is a method of using a mold having a pot, a runner, an inflow gate, a cavity, and the like, and injecting a resin from the pot into the cavity through the runner and the inflow gate to form a resin sealing body. is there.

【００２９】図３において、半導体チップ４、５の夫々
厚さは０．２４ｍｍであり、接着層７の厚さは０．０１
ｍｍであり、リード１０Ａ及び１０Ｂの厚さは０．１２
５ｍｍであり、半導体チップ４の主面４Ａからこの半導
体チップ４の電極６とリード１０Ａとを電気的に接続す
るワイヤ１１の頂部までの高さ（ループ高さ）は０．１
９ｍｍであり、このワイヤ１１の頂部から樹脂封止体１
１の上面までの間隔は０．０６５ｍｍであり、樹脂封止
体１２の厚さは１．０ｍｍであり、樹脂封止体１２上面
からリード（１０Ａ，１０Ｂ）の実装面までの高さは
１．２０ｍｍである。なお、図示していないが、半導体
チップ５の主面５Ａからこの半導体チップ５の電極６と
リード１０Ｂとを電気的に接続するワイヤ１１の頂部ま
での高さは０．１９ｍｍであり、このワイヤ１１の頂部
から樹脂封止体１１の下面までの間隔は０．０６５ｍｍ
である。In FIG. 3, the thickness of each of the semiconductor chips 4 and 5 is 0.24 mm, and the thickness of the adhesive layer 7 is 0.01
mm, and the thickness of the leads 10A and 10B is 0.12.
The height (loop height) from the main surface 4A of the semiconductor chip 4 to the top of the wire 11 for electrically connecting the electrode 6 of the semiconductor chip 4 and the lead 10A is 0.1 mm.
9 mm from the top of the wire 11
1 is 0.065 mm, the thickness of the resin sealing body 12 is 1.0 mm, and the height from the upper surface of the resin sealing body 12 to the mounting surface of the leads (10A, 10B) is 1 mm. .20 mm. Although not shown, the height from the main surface 5A of the semiconductor chip 5 to the top of the wire 11 for electrically connecting the electrode 6 of the semiconductor chip 5 and the lead 10B is 0.19 mm. The distance from the top of 11 to the lower surface of the resin sealing body 11 is 0.065 mm
It is.

【００３０】図３に示すように、前記支持リード８の接
着固定位置は、リード１０Ａ，１０Ｂのインナー部の高
さと同一平面にある。また、支持リード８の上面はワイ
ヤ１１の頂部よりも低くなっている。支持リード８は、
図４に示すように、半導体チップ４の互いに対向する二
つの短辺４Ａ３及び４Ａ４を横切るように延在してい
る。なお、図４において、符号５Ａ３は半導体チップ５
の互いに対向する二つの短辺のうちの一方の短辺であ
り、符号５Ａ４は他方の短辺である。As shown in FIG. 3, the fixing position of the support lead 8 is on the same plane as the height of the inner portions of the leads 10A and 10B. The upper surface of the support lead 8 is lower than the top of the wire 11. The support lead 8 is
As shown in FIG. 4, the semiconductor chip 4 extends so as to cross the two short sides 4A3 and 4A4 of the semiconductor chip 4 facing each other. In FIG. 4, reference numeral 5A3 denotes the semiconductor chip 5.
Is one of two short sides facing each other, and reference numeral 5A4 is the other short side.

【００３１】また、前記リード１０Ａ，１０Ｂのアウタ
ー部は、図３に示すように、前記樹脂封止体１１の厚さ
方向において、樹脂封止体１１の中心線を含む水平平面
よりも上側の位置に設けられている。このように構成す
ることにより、樹脂封止体１１にかかる応力を緩和する
ことができる。As shown in FIG. 3, the outer portions of the leads 10A and 10B are located above the horizontal plane including the center line of the resin sealing body 11 in the thickness direction of the resin sealing body 11. Position. With this configuration, the stress applied to the resin sealing body 11 can be reduced.

【００３２】次に、半導体装置１の製造プロセスで用い
られるリードフレームについて説明する。図５に示すよ
うに、リードフレームＬＦ１は、枠体１４で規定された
領域内に、複数のリード１０Ａ、複数のリード１０Ｂ、
支持リード８等を配置した構成になっている。複数のリ
ード１０Ａは、枠体１４の互いに対向する二つの長辺部
分のうちの一方の長辺部分に沿って配列され、この一方
の長辺部分と一体化されている。複数のリード１０Ｂ
は、枠体１４の互いに対向する二つの長辺部分のうちの
他方の長辺部分に沿って配列され、この他方の長辺部分
と一体化されている。支持リード８は、複数のリード１
０Ａからなるリード群と、複数のリード１０Ｂからなる
リード群との間に配置され、枠体１４と一体化されてい
る。即ち、リードフレームＬＦ１は、二方向リード配列
構造になっている。Next, a lead frame used in the manufacturing process of the semiconductor device 1 will be described. As shown in FIG. 5, the lead frame LF1 includes a plurality of leads 10A, a plurality of leads 10B,
The configuration is such that support leads 8 and the like are arranged. The plurality of leads 10A are arranged along one long side portion of the two long side portions of the frame body 14 facing each other, and are integrated with this one long side portion. Multiple leads 10B
Are arranged along the other long side of the two opposing long sides of the frame 14 and are integrated with the other long side. The support lead 8 includes a plurality of leads 1.
It is arranged between a lead group consisting of OA and a lead group consisting of a plurality of leads 10B, and is integrated with the frame body. That is, the lead frame LF1 has a two-way lead arrangement structure.

【００３３】複数のリード１０Ａの夫々は、樹脂封止体
に封止されるインナー部と樹脂封止体の外部に導出され
るアウター部とで構成され、タイバー１３を介して互い
に連結されている。複数のリード１０Ｂの夫々は、樹脂
封止体に封止されるインナー部と樹脂封止体の外部に導
出されるアウター部とで構成され、タイバー１３を介し
て互いに連結されている。Each of the plurality of leads 10A is composed of an inner portion sealed with a resin sealing body and an outer portion led out of the resin sealing body, and is connected to each other via a tie bar 13. . Each of the plurality of leads 10B includes an inner part sealed by the resin sealing body and an outer part led out of the resin sealing body, and is connected to each other via a tie bar 13.

【００３４】リードフレームＬＦ１は、例えば鉄（Ｆ
ｅ）−ニッケル（Ｎｉ）系の合金又は銅（Ｃｕ）若しく
は銅系の合金からなる平板材にエッチング加工又はプレ
ス加工を施して所定のリードパターンを形成することに
よって形成される。The lead frame LF1 is made of, for example, iron (F
e)-formed by subjecting a flat plate made of a nickel (Ni) -based alloy or copper (Cu) or a copper-based alloy to etching or pressing to form a predetermined lead pattern.

【００３５】前記リードフレームＬＦ１は、その両面に
半導体チップ４、５を搭載するため、現在使用している
面がその表面かあるいは裏面かを明確に認識する必要が
ある。そこで、その使用されているリードフレームＬＦ
１の面が表面かあるいは裏面かを識別する表裏面識別記
号１４Ａ、１４ＢがリードレームＬＦ１の枠体１４に設
けられている。例えば、図６に示すように、表面側の枠
体１４には表面識別記号「ＡＢＣ」１４Ａが、裏面側の
枠体１４には裏面識別記号「ＤＥＦ」１４Ｂが設けられ
ている。前記表裏面識別記号１４Ａ、１４Ｂは、例え
ば、図７及び図８に示すように、表裏面識別用貫通刻印
１４Ｃであってもよい。要するに、使用されているリー
ドフレームＬＦ１の面が表面かあるいは裏面かが識別で
きる記号であればどのようなものであってもよい。Since the semiconductor chips 4 and 5 are mounted on both surfaces of the lead frame LF1, it is necessary to clearly recognize whether the currently used surface is the front surface or the rear surface. Therefore, the lead frame LF used is
Front and back surface identification symbols 14A and 14B for identifying whether the first surface is the front surface or the back surface are provided on the frame body 14 of the lead frame LF1. For example, as shown in FIG. 6, the front side frame 14 is provided with a front side identification symbol "ABC" 14A, and the back side frame 14 is provided with a rear side identification symbol "DEF" 14B. The front and back surface identification symbols 14A and 14B may be, for example, front and back surface identification stamps 14C as shown in FIGS. 7 and 8. In short, any symbol can be used as long as it can identify whether the surface of the lead frame LF1 used is the front surface or the back surface.

【００３６】このように構成することにより、フレーム
の枠体１４の部分でも表裏両面から認識できるので、リ
ードフレームＬＦ１の両面に半導体チップ４、５を搭載
する際の不具合を低減することができる。これにより、
半導体チップ４、５の固定、リード１０Ａ、１０Ｂの固
定、ワイヤ１１のボンディング等の組立工程における作
業性を向上することができる。With such a configuration, the portion of the frame 14 of the frame can be recognized from both the front and back sides, so that problems when the semiconductor chips 4 and 5 are mounted on both sides of the lead frame LF1 can be reduced. This allows
Workability in an assembly process such as fixing the semiconductor chips 4 and 5, fixing the leads 10 </ b> A and 10 </ b> B, and bonding the wires 11 can be improved.

【００３７】次に、半導体装置１の製造方法について、
図９乃至図１２（要部断面図）を用いて説明する。ま
ず、リードフレームＬＦ１に一方の半導体チップ４を接
着固定する。リードフレームＬＦ１と半導体チップ４と
の固定は、図９に示すように、ヒートステージ２０に半
導体チップ４を装着し、その後、半導体チップ４の主面
４Ａに例えば熱硬化性樹脂からなる接着剤を塗布して接
着層９を形成し、その後、半導体チップ４の主面４Ａに
支持リード８をボンディングツール２１で圧着すること
によって行われる。Next, a method of manufacturing the semiconductor device 1 will be described.
This will be described with reference to FIGS. 9 to 12 (cross-sectional views of main parts). First, one semiconductor chip 4 is bonded and fixed to the lead frame LF1. To fix the lead frame LF1 and the semiconductor chip 4, as shown in FIG. 9, the semiconductor chip 4 is mounted on the heat stage 20, and then an adhesive made of, for example, a thermosetting resin is applied to the main surface 4A of the semiconductor chip 4. The application is performed by forming an adhesive layer 9 and then pressing the support lead 8 to the main surface 4A of the semiconductor chip 4 with a bonding tool 21.

【００３８】次に、半導体チップ４の電極６とリード１
０Ａとを導電性のワイヤ１１で電気的に接続する。半導
体チップ４の電極６とリード１０Ａとの接続は、図１０
に示すように、ヒートステージ２２に半導体チップ４を
装着し、その後、ヒートステージ２２にリード１０Ａ及
びリード１０Ｂをフレーム押さえ部材２３で押さえ付け
た状態で行なわれる。ワイヤ１１としては例えばＡｕワ
イヤを用いる。また、ワイヤ１１の接続方法としては例
えば熱圧着に超音波振動を併用したボンディング法を用
いる。Next, the electrodes 6 of the semiconductor chip 4 and the leads 1
0A is electrically connected with a conductive wire 11. The connection between the electrode 6 of the semiconductor chip 4 and the lead 10A is shown in FIG.
As shown in (2), the semiconductor chip 4 is mounted on the heat stage 22, and thereafter, the lead 10 A and the lead 10 B are held on the heat stage 22 by the frame holding member 23. For example, an Au wire is used as the wire 11. As a method for connecting the wires 11, for example, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

【００３９】次に、半導体チップ４に半導体チップ５を
接着固定する。半導体チップ４と半導体チップ５との固
定は、図１１に示すように、ヒートステージ２３に半導
体チップ４をその主面４Ａを下にして装着し、その後、
半導体チップ４の裏面に例えばＡｇペースト材からなる
接着剤を塗布して接着層７を形成し、その後、半導体チ
ップ４の裏面上に半導体チップ５をその裏面を下にして
装着することによって行なわれる。この時、半導体チッ
プ４の一方の長辺４Ａ１に対して半導体チップ５の一方
の長辺５Ａ１が反対側に位置するように向きを揃えた状
態で半導体チップ４、半導体チップ５の夫々の裏面同志
を向い合わせて接着固定する。Next, the semiconductor chip 5 is bonded and fixed to the semiconductor chip 4. To fix the semiconductor chip 4 and the semiconductor chip 5, as shown in FIG. 11, the semiconductor chip 4 is mounted on the heat stage 23 with its main surface 4A facing down.
An adhesive made of, for example, an Ag paste material is applied to the back surface of the semiconductor chip 4 to form an adhesive layer 7, and then the semiconductor chip 5 is mounted on the back surface of the semiconductor chip 4 with the back surface down. . At this time, the back surfaces of the semiconductor chip 4 and the semiconductor chip 5 are aligned with each other in such a state that the one long side 5A1 of the semiconductor chip 5 is located on the opposite side to the one long side 4A1 of the semiconductor chip 4. Face to face and fix.

【００４０】また、半導体チップ４の電極６が半導体チ
ップ５の他方の長辺５Ａ２よりもその外側に位置し、半
導体チップ５の電極６が半導体チップ４の他方の長辺４
Ａ２よりもその外側に位置するように位置をずらした状
態で半導体チップ４、半導体チップ５の夫々の裏面同志
を向い合わせて接着固定する。The electrode 6 of the semiconductor chip 4 is located outside the other long side 5A2 of the semiconductor chip 5, and the electrode 6 of the semiconductor chip 5 is
The semiconductor chips 4 and 5 are adhesively fixed with their back surfaces facing each other in a state where the positions are shifted so as to be located outside of A2.

【００４１】なお、この工程において、半導体チップ４
はその主面４Ａを下にした状態でヒートステージ２３に
装着されるので、ヒートステージ２３とワイヤ１１との
接触を防止するため、ヒートステージ２３には窪み２３
Ａが設けられている。In this step, the semiconductor chip 4
Is mounted on the heat stage 23 with its main surface 4A down, so that the contact between the heat stage 23 and the wire 11 is prevented.
A is provided.

【００４２】次に、半導体チップ５の電極６とリード１
０Ｂとを導電性のワイヤ１１で電気的に接続する。半導
体チップ５の電極６とリード１０Ｂとの接続は、図１２
に示すように、半導体チップ５の主面５Ａを上向きにし
てヒートステージ２４に半導体チップ４及び半導体チッ
プ５を装着し、その後、ヒートステージ２４にリード１
０Ａ及びリード１０Ｂをフレーム押さえ部材２５で押え
つけた状態で行なわれる。ワイヤ１１としては例えばＡ
ｕワイヤを用いる。Next, the electrodes 6 of the semiconductor chip 5 and the leads 1
0B is electrically connected with a conductive wire 11. The connection between the electrode 6 of the semiconductor chip 5 and the lead 10B is shown in FIG.
As shown in FIG. 5, the semiconductor chip 4 and the semiconductor chip 5 are mounted on the heat stage 24 with the main surface 5A of the semiconductor chip 5 facing upward, and then the leads 1 are mounted on the heat stage 24.
0A and the lead 10B are held by the frame holding member 25. As the wire 11, for example, A
Use a u-wire.

【００４３】また、ワイヤ１１の接続方法としては例え
ば熱圧着に超音波振動を併用したボンディング法を用い
る。この工程において、半導体チップ５の電極６と対向
する裏面の領域が露出しているので、この裏面の領域に
接触するように突出部２５Ｂをヒートステージ２４に設
けておくことにより、半導体チップ５の電極と対向する
裏面の領域をヒートステージ２４に直に接触させること
ができる。As a method for connecting the wires 11, for example, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used. In this step, since the region of the back surface facing the electrode 6 of the semiconductor chip 5 is exposed, the protrusion 25B is provided on the heat stage 24 so as to contact the region of the back surface. The area of the back surface facing the electrode can be brought into direct contact with the heat stage 24.

【００４４】即ち、半導体チップ４の電極６が半導体チ
ップ５の他方の長辺５Ａ２よりもその外側に位置し、半
導体チップ５の電極６が半導体チップ４の他方の長辺４
Ａ２よりもその外側に位置するように位置をずらした状
態で半導体チップ４、半導体チップ５の夫々の裏面同志
を接着固定することにより、半導体チップ５の電極６と
対向する裏面の領域をヒートステージ２４に直に接触さ
せることができ、ヒートステージ２４の熱が半導体チッ
プ５の電極６に有効に伝達されるので、半導体チップ５
の電極６とワイヤ１１との接続不良を低減することがで
きる。That is, the electrode 6 of the semiconductor chip 4 is located outside the other long side 5A2 of the semiconductor chip 5, and the electrode 6 of the semiconductor chip 5 is
The semiconductor chip 4 and the semiconductor chip 5 are adhesively fixed to each other with their positions shifted to be outside of the area A2, so that the area of the back surface facing the electrode 6 of the semiconductor chip 5 is heat-staged. 24, and the heat of the heat stage 24 is effectively transmitted to the electrodes 6 of the semiconductor chip 5.
Defective connection between the electrode 6 and the wire 11 can be reduced.

【００４５】なお、この工程において、半導体チップ４
はその主面４Ａを下にした状態でヒートステージ２４に
装着されるので、ヒートステージ２４とワイヤ１１との
接触を防止するため、ヒートステージ２４には窪み２４
Ａが設けられている。In this step, the semiconductor chip 4
Is mounted on the heat stage 24 with its main surface 4A facing down, so that the heat stage 24 is indented to prevent contact between the wire 11 and the heat stage 24.
A is provided.

【００４６】次に、半導体チップ４、半導体チップ５、
支持リード８、リード１０Ａのインナー部、リード１０
Ｂのインナー部及びワイヤ１１等を樹脂で封止して樹脂
封止体１２を形成する。樹脂封止体１２の形成はトラン
スファモールディング法で行う。Next, the semiconductor chip 4, the semiconductor chip 5,
Support lead 8, inner part of lead 10A, lead 10
A resin sealing body 12 is formed by sealing the inner portion of B, the wire 11 and the like with a resin. The formation of the resin sealing body 12 is performed by a transfer molding method.

【００４７】次に、リード１０Ａに連結されたタイバー
１３及びリード１０Ｂに連結されたタイバー１３を切断
し、その後、リード１０Ａ、リード１０Ｂの夫々のアウ
ター部にメッキ処理を施し、その後、リードフレームＬ
Ｆ１の枠体１４からリード１０Ａ及び１０Ｂを切断し、
その後、リード１０Ａ、１０Ｂの夫々のアウター部を面
実装型形状として例えばガルウィング形状に成形し、そ
の後、リードフレームＬＦ１の枠体１４から支持リード
８を切断することにより、図１、図２及び図３に示す半
導体装置１がほぼ完成する。Next, the tie bar 13 connected to the lead 10A and the tie bar 13 connected to the lead 10B are cut, and then the outer portions of the leads 10A and 10B are plated.
Cut the leads 10A and 10B from the frame 14 of F1,
After that, the outer portions of the leads 10A and 10B are formed into a gull wing shape, for example, as a surface-mounting shape, and then the support leads 8 are cut from the frame 14 of the lead frame LF1, thereby obtaining FIGS. The semiconductor device 1 shown in FIG. 3 is almost completed.

【００４８】このようにして構成された半導体装置１
は、図１３（要部断面図）に示すように、１つの回路シ
ステムを構成する電子装置の構成部品として実装基板３
０に複数個実装される。半導体装置１は、同一機能のリ
ードが対向して配置されているので、リード１０Ａとリ
ード１０Ｂとを電気的に接続するための配線３１を直線
的に引き回すことができる。また、半導体装置１のリー
ド１０Ｂと他の半導体装置１のリード１０Ａとを電気的
に接続するための配線３１を直線的に引き回すことがで
きる。従って、実装基板３０の配線層数を低減すること
ができるので、電子装置、例えばメモリーモジュール等
の薄型化を図ることができる。The semiconductor device 1 thus configured
As shown in FIG. 13 (a cross-sectional view of a main part), the mounting board 3 is used as a component of an electronic device constituting one circuit system.
0 is implemented in multiple numbers. In the semiconductor device 1, since the leads having the same function are arranged to face each other, the wiring 31 for electrically connecting the leads 10A and 10B can be linearly routed. Further, the wiring 31 for electrically connecting the lead 10B of the semiconductor device 1 and the lead 10A of another semiconductor device 1 can be routed linearly. Therefore, the number of wiring layers of the mounting substrate 30 can be reduced, and thus the thickness of the electronic device, for example, the memory module can be reduced.

【００４９】以上説明したように、本実施形態１によれ
ば以下の効果が得られる。 （１）半導体チップ４、半導体チップ５の夫々は、半導
体チップ４の一方の長辺４Ａ２及び半導体チップ５の一
方の長辺５Ａ１がリード１０Ｂ側に向くように夫々の裏
面同志を向い合わせた状態で互いに接着固定され、支持
リード８は半導体チップ４の主面４Ａ１に接着固定され
ている。このことから、半導体チップ４と半導体チップ
５との間にはタブが存在しないので、半導体チップ４の
主面４Ａから半導体チップ５の主面５Ａまでの距離を縮
小することができる。また、半導体チップ４と半導体チ
ップ５との間には一つの接着層しか存在しないので、半
導体チップ４の主面４Ａから半導体チップ５の主面５Ａ
までの距離を縮小することができる。また、支持リード
８は半導体チップ４の主面４Ａに接着固定されているの
で、支持リード８の厚さはワイヤ１１のループ高さで相
殺され、支持リード８による樹脂封止体１２の厚さへの
影響はない。この結果、樹脂封止体１２の厚さを薄くす
ることができるので、半導体装置１の薄型化を図ること
ができる。As described above, according to the first embodiment, the following effects can be obtained. (1) The semiconductor chip 4 and the semiconductor chip 5 face each other such that the one long side 4A2 of the semiconductor chip 4 and the one long side 5A1 of the semiconductor chip 5 face the lead 10B side. The support leads 8 are bonded and fixed to the main surface 4A1 of the semiconductor chip 4. Accordingly, since no tab exists between the semiconductor chip 4 and the semiconductor chip 5, the distance from the main surface 4A of the semiconductor chip 4 to the main surface 5A of the semiconductor chip 5 can be reduced. Also, since only one adhesive layer exists between the semiconductor chip 4 and the semiconductor chip 5, the main surface 4A of the semiconductor chip 4 is shifted from the main surface 5A of the semiconductor chip 5 to the main surface 5A.
Distance can be reduced. Further, since the support lead 8 is bonded and fixed to the main surface 4A of the semiconductor chip 4, the thickness of the support lead 8 is offset by the loop height of the wire 11, and the thickness of the resin sealing body 12 by the support lead 8 is reduced. There is no effect on As a result, the thickness of the resin sealing body 12 can be reduced, so that the thickness of the semiconductor device 1 can be reduced.

【００５０】また、半導体チップ（４，５）の厚さを薄
くすることなく、樹脂封止体１２の厚さを薄くすること
ができるので、歩留まりの高い薄型の半導体装置１を提
供することができる。Further, since the thickness of the resin sealing body 12 can be reduced without reducing the thickness of the semiconductor chips (4, 5), a thin semiconductor device 1 having a high yield can be provided. it can.

【００５１】また、樹脂封止体１２の厚さを薄くするこ
とができるので、二つの半導体チップ（４，５）を積層
し、この二つの半導体チップを一つの樹脂封止体１２で
封止した半導体装置１をＴＳＯＰ型で構成することがで
きる。Further, since the thickness of the resin sealing body 12 can be reduced, two semiconductor chips (4, 5) are stacked, and the two semiconductor chips are sealed with one resin sealing body 12. Semiconductor device 1 can be configured in a TSOP type.

【００５２】また、二枚のリードフレームを使用する必
要がなく、更にミラー反転回路パターンの半導体チップ
を使用する必要がないので、半導体装置１の低コスト化
及び薄型化を図ることができる。Further, since it is not necessary to use two lead frames and further, it is not necessary to use a semiconductor chip having a mirror inversion circuit pattern, the cost and thickness of the semiconductor device 1 can be reduced.

【００５３】（２）半導体チップ４、半導体チップ５の
夫々は、半導体チップ４の電極６が半導体チップ５の他
方の長辺５Ａ２よりもその外側に位置し、半導体チップ
５の電極６が半導体チップ４の他方の長辺４Ａ２よりも
その外側に位置するように夫々の位置をずらした状態で
接着固定されている。このことから、ワイヤボンディン
グ工程において、半導体チップ５の電極６と対向する裏
面の領域をヒートステージ２４に直に接触させることが
でき、ヒートステージ２４の熱が半導体チップ５の電極
６に有効に伝達されるので、半導体チップ５の電極６と
ワイヤ１１との接続不良を低減することができる。この
結果、半導体装置１の製造プロセス（組立プロセス）に
おける歩留まりを高めることができる。(2) In each of the semiconductor chip 4 and the semiconductor chip 5, the electrode 6 of the semiconductor chip 4 is located outside the other long side 5A2 of the semiconductor chip 5, and the electrode 6 of the semiconductor chip 5 is 4 are bonded and fixed in a state where their respective positions are shifted so as to be located outside the other long side 4A2 of the other. Thus, in the wire bonding step, the area of the back surface facing the electrode 6 of the semiconductor chip 5 can be brought into direct contact with the heat stage 24, and the heat of the heat stage 24 is effectively transmitted to the electrode 6 of the semiconductor chip 5. Therefore, poor connection between the electrode 6 of the semiconductor chip 5 and the wire 11 can be reduced. As a result, the yield in the manufacturing process (assembly process) of the semiconductor device 1 can be increased.

【００５４】（３）リードフレームＬＦ１は、その両面
に半導体チップ４、５を搭載するために、その使用され
ているリードフレームＬＦ１の面が表面かあるいは裏面
かを識別する表裏面識別記号１４Ａ、１４Ｂ、１４Ｃを
リードフレームＬＦ１の枠体１４に設けることにより、
リードフレームＬＦ１の枠体１４の部分であってもその
表裏両面を認識できるので、リードフレームＬＦ１の両
面に半導体チップ４、５を搭載する際の不具合を低減す
ることができる。これにより、半導体チップ４、５の固
定、リード１０Ａ、１０Ｂの固定やワイヤ１１のボンデ
ィング等の組立工程における作業性を向上することがで
きる。(3) Since the semiconductor chips 4 and 5 are mounted on both surfaces of the lead frame LF1, the front and back surface identification symbol 14A for identifying whether the surface of the lead frame LF1 used is the front surface or the back surface. By providing 14B and 14C on the frame 14 of the lead frame LF1,
Since both the front and back surfaces of the frame body 14 of the lead frame LF1 can be recognized, problems when mounting the semiconductor chips 4 and 5 on both surfaces of the lead frame LF1 can be reduced. Thereby, workability in an assembly process such as fixing the semiconductor chips 4 and 5, fixing the leads 10 </ b> A and 10 </ b> B, and bonding the wires 11 can be improved.

【００５５】なお、本実施形態１では、半導体チップ４
の主面４Ａに支持リード８を接着固定した例について説
明したが、支持リード８は、半導体チップ５の主面５Ａ
に接着固定してもよい。この場合、支持リード８には、
そのチップ固定部を半導体チップ５の主面５Ａ側に位置
させるための折り曲げ加工が施される。また、このよう
な場合においても、支持リード８の厚さは、半導体チッ
プ５の電極６とリード１０Ｂとを電気的に接続するワイ
ヤ１１のループ高さで相殺されるので、支持リード８に
よる樹脂封止体１２の厚さへの影響はない。In the first embodiment, the semiconductor chip 4
The example in which the support lead 8 is bonded and fixed to the main surface 4A of the semiconductor chip 5 has been described.
May be adhered and fixed. In this case, the support lead 8
Bending processing is performed to position the chip fixing portion on the main surface 5A side of the semiconductor chip 5. Also in such a case, the thickness of the support lead 8 is offset by the loop height of the wire 11 that electrically connects the electrode 6 of the semiconductor chip 5 and the lead 10B. There is no effect on the thickness of the sealing body 12.

【００５６】（実施形態２）図１４は本発明の実施形態
２である半導体装置の樹脂封止体の上部を除去した状態
の平面図であり、図１５は図１４のＣ−Ｃ線に沿う模式
的断面図であり、図１６は図１４のＤ−Ｄ線に沿う模式
的断面図である。図１４、図１５及び図１６に示すよう
に、本実施形態２の半導体装置２は、前述の実施形態１
と基本的に同様の構成になっており、以下の構成が異な
っている。(Embodiment 2) FIG. 14 is a plan view of a semiconductor device according to Embodiment 2 of the present invention in a state where an upper portion of a resin sealing body is removed, and FIG. 15 is taken along line CC of FIG. FIG. 16 is a schematic cross-sectional view, and FIG. 16 is a schematic cross-sectional view along the line DD in FIG. As shown in FIG. 14, FIG. 15 and FIG. 16, the semiconductor device 2 of the second embodiment
The configuration is basically the same as that described above, and the following configuration is different.

【００５７】即ち、半導体チップ４、半導体チップ５の
夫々は、半導体チップ４の一方の長辺４Ａ１と交わる一
方の短辺４Ａ３がこの一方の短辺４Ａ３と同一側であっ
て半導体チップ５の一方の長辺５Ａ１と交わる一方の短
辺５Ａ３よりもその外側に位置し、半導体チップ５の一
方の短辺５Ａ３と対向する他方の短辺５Ａ４がこの他方
の短辺５Ａ４と同一側であって半導体チップ４の一方の
短辺４Ａ３と対向する他方の短辺４Ａ４よりも外側に位
置するように夫々の位置をずらした状態で接着固定され
ている。即ち、半導体チップ４、半導体チップ５の夫々
は、電極６の配列方向に夫々の位置をずらした状態で接
着固定されている。That is, in each of the semiconductor chip 4 and the semiconductor chip 5, one short side 4A3 intersecting with one long side 4A1 of the semiconductor chip 4 is on the same side as the one short side 4A3, and one side of the semiconductor chip 5 The other short side 5A4 of the semiconductor chip 5 which is located outside the short side 5A3 intersecting with the long side 5A1 and faces the one short side 5A3 of the semiconductor chip 5 is on the same side as the other short side 5A4. The chips 4 are bonded and fixed in such a manner that their positions are shifted so as to be located outside the other short side 4A4 facing the one short side 4A3. That is, the semiconductor chip 4 and the semiconductor chip 5 are bonded and fixed in such a manner that their positions are shifted in the arrangement direction of the electrodes 6.

【００５８】また、半導体チップ４の一方の短辺４Ａ３
及び半導体チップ５の一方の短辺５Ａ３の外側に配置さ
れた支持リード８Ａと、半導体チップ４の他方の短辺４
Ａ４及び半導体チップ５の他方の短辺５Ａ４の外側に配
置された支持リード８Ｂとを有し、支持リード８Ａは、
半導体チップ５の他方の短辺５Ａ４の外側において半導
体チップ４の裏面に接着層７を介在して接着固定され、
支持リード８Ｂは、半導体チップ４の他方の短辺４Ａ４
の外側において半導体チップ５の裏面に接着層７を介在
して接着固定されている。Also, one short side 4A3 of the semiconductor chip 4
A supporting lead 8A disposed outside one short side 5A3 of the semiconductor chip 5;
A4 and a support lead 8B disposed outside the other short side 5A4 of the semiconductor chip 5;
Outside the other short side 5A4 of the semiconductor chip 5, it is bonded and fixed to the back surface of the semiconductor chip 4 with an adhesive layer 7 interposed therebetween,
The support lead 8B is connected to the other short side 4A4 of the semiconductor chip 4.
Is bonded and fixed to the back surface of the semiconductor chip 5 with an adhesive layer 7 interposed therebetween.

【００５９】支持リード８Ａには、半導体チップ４の裏
面側にそのチップ固定部を位置させるための折り曲げ加
工が施され、支持リード８Ｂには、半導体チップ５の裏
面側にそのチップ固定部を位置させるための折り曲げ加
工が施されている。The support lead 8A is bent to position the chip fixing portion on the back surface side of the semiconductor chip 4, and the support lead 8B is positioned on the back surface side of the semiconductor chip 5 with the chip fixing portion. It is bent to make it bend.

【００６０】このように構成された半導体装置２は、図
１７（平面図）に示すリードフレームＬＦ２を用いた製
造プロセスで製造される。本実施形態の半導体装置２の
製造は、前述の実施形態１で説明した製造方法と若干異
なり、半導体チップ４、半導体チップ５の夫々を夫々の
裏面同志を向い合わせた状態で接着固定し、支持リード
８Ａ、支持リード８Ｂの夫々に半導体チップ４、半導体
チップ５の夫々を接着固定した後、ワイヤボンディング
を行う。支持リードと半導体チップとの固定は、支持リ
ード８Ａと支持リード８Ｂとの間に、接着固定された半
導体チップ４及び半導体チップ５を傾斜させて挿入する
ことにより行うことができる。The semiconductor device 2 thus configured is manufactured by a manufacturing process using the lead frame LF2 shown in FIG. 17 (plan view). The manufacturing of the semiconductor device 2 of this embodiment is slightly different from the manufacturing method described in the first embodiment, and the semiconductor chip 4 and the semiconductor chip 5 are bonded and fixed with their back surfaces facing each other. After the semiconductor chip 4 and the semiconductor chip 5 are respectively bonded and fixed to the lead 8A and the support lead 8B, wire bonding is performed. The fixing between the support lead and the semiconductor chip can be performed by inserting the semiconductor chip 4 and the semiconductor chip 5 bonded and fixed at an angle between the support lead 8A and the support lead 8B.

【００６１】ワイヤボンディング工程は、半導体チップ
４の電極６とリード１０Ａとをワイヤ１１で電気的に接
続し、その後、半導体チップ５の電極６とリード１０Ｂ
とワイヤ１１で電気的に接続することによって行うが、
半導体チップ４、半導体チップ５の夫々は、電極６の配
列方向に夫々の位置をずらした状態で接着固定されてい
るので、半導体チップ４の電極６とリード１０Ａとをワ
イヤ１１で接続する時、直ではないが、半導体チップ４
の他方の短辺４Ａ３側の領域と対向する裏面の領域に支
持リード８Ａを介在してヒートステージを接触させるこ
とができる。また、半導体チップ５の電極６とリード１
０Ｂとをワイヤ１１で接続する時、直ではないが、半導
体チップ５の他方の短辺５Ａ３側の領域と対向する裏面
の領域に支持リード８Ｂを介在してヒートステージを接
触させることができる。In the wire bonding step, the electrodes 6 of the semiconductor chip 4 are electrically connected to the leads 10A by wires 11, and then the electrodes 6 of the semiconductor chip 5 are connected to the leads 10B.
Is electrically connected with the wire 11,
Since each of the semiconductor chip 4 and the semiconductor chip 5 is bonded and fixed with their respective positions shifted in the arrangement direction of the electrodes 6, when the electrodes 6 of the semiconductor chip 4 and the leads 10A are connected by the wires 11, Not directly, but semiconductor chip 4
The heat stage can be brought into contact with the region on the back surface opposite to the region on the other short side 4A3 side via the support lead 8A. Further, the electrode 6 of the semiconductor chip 5 and the lead 1
When the wire 11 is connected to the heat stage 0B, the heat stage can be brought into contact with a region on the back surface of the semiconductor chip 5 which is not directly opposed to the region on the other short side 5A3 side via the support lead 8B.

【００６２】このように、半導体チップ４、半導体チッ
プ５の夫々は、半導体チップ４の一方の短辺４Ａ３が半
導体チップ５の一方の短辺５Ａ３よりもその外側に位置
し、半導体チップ５の他方の短辺５Ａ４が半導体チップ
４の他方の短辺４Ａ４よりもその外側に位置するように
夫々の位置をずらした状態で互いに接着固定され、支持
リード８Ａは、半導体チップ５の一方の短辺５Ａ３外側
において半導体チップ４の裏面に接着固定され、支持リ
ード８Ｂは、半導体チップ４の他方の短辺４Ａ４の外側
において半導体チップ５の裏面に接着固定されているこ
とから、半導体チップ４と半導体チップ５との間にはタ
ブが存在しないので、半導体チップ４の主面４Ａから半
導体チップ５の主面５Ａまでの距離を縮小することがで
きる。また、半導体チップ４と半導体チップ５との間に
は一つの接着層しか存在しないので、半導体チップ４の
主面４Ａから半導体チップ５の主面５Ａまでの距離を縮
小することができる。また、支持リード８Ａは半導体チ
ップ５の一方の短辺５Ａ３よりもその外側に引き出され
た半導体チップ４の裏面に接着固定され、支持リード８
Ｂは半導体チップ４の他方の短辺４Ａ４よりもその外側
に引き出された半導体チップ５の裏面に接着固定されて
いるので、支持リード８Ａ、８Ｂの夫々の厚さは半導体
チップ４の主面４Ａから半導体チップ５の主面５Ａまで
の厚さで相殺され、支持リード８Ａ、８Ｂによる樹脂封
止体１２の厚さへの影響はない。この結果、前述の実施
形態１と同様の効果が得られる。As described above, in each of the semiconductor chip 4 and the semiconductor chip 5, one short side 4A3 of the semiconductor chip 4 is located outside the one short side 5A3 of the semiconductor chip 5, and the other side of the semiconductor chip 5 Are adhered and fixed to each other in such a manner that their short sides 5A4 are located outside of the other short side 4A4 of the semiconductor chip 4 while being shifted from each other, and the support leads 8A are connected to one short side 5A3 of the semiconductor chip 5. Since the support leads 8B are bonded and fixed to the back surface of the semiconductor chip 4 outside the other short side 4A4 of the semiconductor chip 4, the semiconductor chip 4 and the semiconductor chip 5 are bonded together. Since there is no tab between them, the distance from the main surface 4A of the semiconductor chip 4 to the main surface 5A of the semiconductor chip 5 can be reduced. Further, since only one adhesive layer exists between the semiconductor chip 4 and the semiconductor chip 5, the distance from the main surface 4A of the semiconductor chip 4 to the main surface 5A of the semiconductor chip 5 can be reduced. Further, the support lead 8A is bonded and fixed to the back surface of the semiconductor chip 4 which is drawn out of the short side 5A3 of the semiconductor chip 5 beyond the one short side 5A3.
B is bonded and fixed to the back surface of the semiconductor chip 5 drawn out of the other short side 4A4 of the semiconductor chip 4, so that the thickness of each of the support leads 8A and 8B is equal to the main surface 4A of the semiconductor chip 4. Of the semiconductor chip 5 to the main surface 5A of the semiconductor chip 5, and there is no influence on the thickness of the resin sealing body 12 by the support leads 8A and 8B. As a result, the same effects as in the first embodiment can be obtained.

【００６３】また、半導体チップ４、半導体チップ５の
夫々は、半導体チップ４の一方の長辺４Ａ１と交わる一
方の短辺４Ａ３がこの一方の短辺４Ａ３と同一側であっ
て半導体チップ５の一方の長辺５Ａ１と交わる一方の短
辺５Ａ３よりもその外側に位置し、半導体チップ５の一
方の短辺５Ａ３と対向する他方の短辺５Ａ４がこの他方
の短辺５Ａ４と同一側であって半導体チップ４の一方の
短辺４Ａ３と対向する他方の短辺４Ａ４よりも外側に位
置するように夫々の位置をずらした状態で接着固定され
ていることから、ワイヤボンディング工程において、半
導体チップ４の裏面とヒートステージ２４との接触面積
が増加するので、ワイヤボンディング工程における半導
体チップ４の加熱時間を短縮することができる。また、
半導体チップ５の裏面とヒートステージ２４との接触面
積が増加するので、ワイヤボンディング工程における半
導体チップ５の加熱時間を短縮することができる。この
結果、半導体装置２の生産効率を高めることができる。Each of the semiconductor chip 4 and the semiconductor chip 5 has one short side 4A3 intersecting with one long side 4A1 of the semiconductor chip 4 on the same side as the one short side 4A3. The other short side 5A4 of the semiconductor chip 5 which is located outside the short side 5A3 intersecting with the long side 5A1 and faces the one short side 5A3 of the semiconductor chip 5 is on the same side as the other short side 5A4. The chip 4 is bonded and fixed so that it is located outside the other short side 4A4 opposite to the one short side 4A3, and the back side of the semiconductor chip 4 in the wire bonding step. Since the contact area between the semiconductor chip 4 and the heat stage 24 increases, the heating time of the semiconductor chip 4 in the wire bonding step can be reduced. Also,
Since the contact area between the back surface of the semiconductor chip 5 and the heat stage 24 increases, the heating time of the semiconductor chip 5 in the wire bonding step can be reduced. As a result, the production efficiency of the semiconductor device 2 can be improved.

【００６４】（実施形態３）図１８は本発明の実施形態
３である半導体装置の樹脂封止体の上部を除去した状態
の平面図であり、図１９は図１８のＥ−Ｅ線に沿う模式
的断面図である。図１８、図１９に示すように、本実施
形態３の半導体装置３は、前述の実施形態２と基本的に
同様の構成になっており、以下の構成が異なっている。(Embodiment 3) FIG. 18 is a plan view of a semiconductor device according to Embodiment 3 of the present invention in a state where an upper portion of a resin sealing body is removed, and FIG. 19 is taken along line EE of FIG. It is a typical sectional view. As shown in FIGS. 18 and 19, the semiconductor device 3 of the third embodiment has basically the same configuration as that of the above-described second embodiment, but differs in the following configuration.

【００６５】即ち、支持リード８Ａは、半導体チップ４
の主面４Ａにおいてその一方の短辺４Ａ３側に接着固定
され、支持リード８Ｂは、半導体チップ５の主面５Ａに
おいてその他方の短辺５Ａ４側に接着固定されている。That is, the support lead 8A is connected to the semiconductor chip 4
The support lead 8B is bonded and fixed to the other short side 5A4 side of the main surface 5A of the semiconductor chip 5 on the main surface 4A of the semiconductor chip 5.

【００６６】支持リード８Ａには折り曲げ加工が施され
ていないが、支持リード８Ｂには、半導体チップ５の主
面５Ａ側にそのチップ固定部を位置させるための折り曲
げ加工が施されている。The support lead 8A is not bent, but the support lead 8B is bent on the main surface 5A side of the semiconductor chip 5 to position the chip fixing portion.

【００６７】このように構成された半導体装置３は、図
２０（平面図）に示すリードフレームＬＦ３を用いた製
造プロセスで製造される。本実施形態３の半導体装置３
の製造は、前述の実施形態２で説明した製造方法と同様
に、半導体チップ４、半導体チップ５の夫々を夫々の裏
面同志を向い合わせた状態で接着固定し、支持リード８
Ａ、支持リード８Ｂの夫々に半導体チップ４、半導体チ
ップ５の夫々を接着固定した後、ワイヤボンディングを
行う。支持リードと半導体チップとの固定は、支持リー
ド８Ａと支持リード８Ｂとの間に、接着固定された半導
体チップ４及び半導体チップ５を傾斜させて挿入するこ
とにより行うことができる。The semiconductor device 3 thus configured is manufactured by a manufacturing process using a lead frame LF3 shown in FIG. 20 (plan view). Semiconductor device 3 of Embodiment 3
In the same manner as in the manufacturing method described in the second embodiment, the semiconductor chip 4 and the semiconductor chip 5 are bonded and fixed with the back surfaces thereof facing each other.
A, after bonding the semiconductor chip 4 and the semiconductor chip 5 to each of the support leads 8B, wire bonding is performed. The fixing between the support lead and the semiconductor chip can be performed by inserting the semiconductor chip 4 and the semiconductor chip 5 bonded and fixed at an angle between the support lead 8A and the support lead 8B.

【００６８】ワイヤボンディング工程は、半導体チップ
４の電極６とリード１０Ａとをワイヤ１１で電気的に接
続し、その後、半導体チップ５の電極６とリード１０Ｂ
とをワイヤ１１で電気的に接続することによって行う
が、半導体チップ４、半導体チップ５の夫々は、電極６
の配列方向に夫々の位置をずらした状態で接着固定され
ており、支持リード８Ａは半導体チップ４の主面４Ａに
おいて一方の短辺４Ａ３側に接着固定され、支持リード
８Ｂは半導体チップ５の主面５Ａにおいて他方の短辺５
Ａ４側に接着固定されているので、半導体チップ４の電
極６とリード１０Ａとをワイヤ１１で接続する時、半導
体チップ４の一方の短辺４Ａ３側の領域と対向する裏面
の領域にヒートステージを直に接触させることができ
る。また、半導体チップ５の電極６とリード１０Ｂとを
ワイヤ１１で接続する時、半導体チップ５の他方の短辺
５Ａ３側の領域と対向する裏面の領域にヒートステージ
を直に接触させることができる。In the wire bonding step, the electrodes 6 of the semiconductor chip 4 are electrically connected to the leads 10A by wires 11, and then the electrodes 6 of the semiconductor chip 5 are connected to the leads 10B.
And the semiconductor chip 4 and the semiconductor chip 5 are electrically connected to each other by wires 11.
The supporting leads 8A are bonded and fixed to one short side 4A3 of the main surface 4A of the semiconductor chip 4 while the supporting leads 8B are fixed to the main chip 4A. The other short side 5 on the surface 5A
When the electrode 6 of the semiconductor chip 4 and the lead 10A are connected by the wire 11, the heat stage is mounted on the back surface of the semiconductor chip 4 opposite to the short side 4A3. It can be brought into direct contact. Further, when the electrode 6 of the semiconductor chip 5 and the lead 10B are connected by the wire 11, the heat stage can be brought into direct contact with the region on the back surface opposite to the region on the other short side 5A3 side of the semiconductor chip 5.

【００６９】このように、支持リード８Ａは、半導体チ
ップ４の主面４Ａにおいてその一方の短辺４Ａ３側に接
着固定され、支持リード８Ｂは、半導体チップ５の主面
５Ａにおいてその他方の短辺５Ａ４側に接着固定されて
いることから、半導体チップ４と半導体チップ５との間
にはタブが存在しないので、半導体チップ４の主面４Ａ
から半導体チップ５の主面５Ａまでの距離を縮小するこ
とができる。また、半導体チップ４と半導体チップ５と
の間には一つの接着層しか存在しないので、半導体チッ
プ４の主面４Ａから半導体チップ５の主面５Ａまでの距
離を縮小することができる。また、支持リード８Ａは、
半導体チップ４の主面４Ａにおいてその一方の短辺４Ａ
３側に接着固定され、支持リード８Ｂは、半導体チップ
５の主面５Ａにおいてその他方の短辺５Ａ４側に接着固
定されているので、支持リード８Ａの厚さは半導体チッ
プ４の電極６とリード１０Ａとを電気的に接続するワイ
ヤ１１のループ高さで相殺され、支持リード８Ｂの厚さ
は半導体チップ５の電極６とリード１０Ｂとを電気的に
接続するワイヤ１１のループ高さで相殺される。従っ
て、支持リード８Ａ、８Ｂによる樹脂封止体１２の厚さ
への影響はない。この結果、前述の実施形態２と同様の
効果が得られる。As described above, the support lead 8A is bonded and fixed to one short side 4A3 of the main surface 4A of the semiconductor chip 4, and the support lead 8B is fixed to the other short side of the main surface 5A of the semiconductor chip 5. Since there is no tab between the semiconductor chip 4 and the semiconductor chip 5 because it is bonded and fixed to the 5A4 side, the main surface 4A of the semiconductor chip 4
Of the semiconductor chip 5 to the main surface 5A of the semiconductor chip 5 can be reduced. Further, since only one adhesive layer exists between the semiconductor chip 4 and the semiconductor chip 5, the distance from the main surface 4A of the semiconductor chip 4 to the main surface 5A of the semiconductor chip 5 can be reduced. The support lead 8A is
One short side 4A of the main surface 4A of the semiconductor chip 4
3 and the supporting lead 8B is bonded and fixed to the other short side 5A4 of the main surface 5A of the semiconductor chip 5, so that the thickness of the supporting lead 8A is equal to that of the electrode 6 of the semiconductor chip 4 and the lead. The thickness of the support lead 8B is offset by the loop height of the wire 11 that electrically connects the electrode 6 of the semiconductor chip 5 and the lead 10B. You. Therefore, the thickness of the resin sealing body 12 is not affected by the support leads 8A and 8B. As a result, the same effect as in the second embodiment can be obtained.

【００７０】なお、前述の実施形態１においても、本実
施形態３と同様に、電極６の配列方向に位置をずらした
状態で半導体チップ４、半導体チップ５の夫々の裏面同
志を接着固定してもよい。この場合においても、本実施
形態３と同様に、半導体チップ４の裏面とヒートステー
ジとの接触面積が増加するので、ワイヤボンディング工
程における半導体チップ４の加熱時間を短縮することが
できる。また、半導体チップ５の裏面とヒートステージ
との接触面積が増加するので、ワイヤボンディング工程
における半導体チップ５の加熱時間を短縮することがで
きる。In the first embodiment, similarly to the third embodiment, the back surfaces of the semiconductor chips 4 and 5 are bonded and fixed with their positions shifted in the arrangement direction of the electrodes 6. Is also good. Also in this case, as in the third embodiment, the contact area between the back surface of the semiconductor chip 4 and the heat stage increases, so that the heating time of the semiconductor chip 4 in the wire bonding step can be reduced. In addition, since the contact area between the back surface of the semiconductor chip 5 and the heat stage increases, the heating time of the semiconductor chip 5 in the wire bonding step can be reduced.

【００７１】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

【００７２】例えば、本発明は、二方向リード配列構造
であるＳＯＪ（Ｓmall Ｏutline Ｊ-leaded Ｐackage）
型、ＳＯＰ（Ｓmall Ｏutline Ｐackage）型等の半導体
装置に適用できる。また、本発明は、四方向リード配列
構造であるＱＦＰ（Ｑuad Ｆlatpack Ｐackage）型、Ｑ
ＦＪ（Ｑuad Ｆlatpack Ｊ-leaded Ｐackage）型等の半
導体装置に適用できる。[0072] For example, the present invention is, SOJ is a two-way lead array structure (S mall O utline J -leaded Package )
Type, it can be applied to a semiconductor device of SOP (S mall O utline P ackage ) type. Further, the present invention is a four-way lead array structure QFP (Q uad F latpack P ackage ) type, Q
Can be applied to FJ (Q uad F latpack J -leaded Package) type and the like semiconductor device.

【００７３】[0073]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。 （１）二つの半導体チップを積層し、この二つの半導体
チップを一つの樹脂封止体で封止する半導体装置の薄型
化を図ることができる。 （２）二つの半導体チップを積層し、この二つの半導体
チップを一つの樹脂封止体で封止する半導体装置におい
て、リードフレーム一個で二つの半導体チップに設けら
れた電極に対応することができる。 （３）半導体装置の組立工程における作業性を向上する
ことができる。 （４）半導体装置の歩留まりを高めることができる。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) It is possible to reduce the thickness of a semiconductor device in which two semiconductor chips are stacked and the two semiconductor chips are sealed with one resin sealing body. (2) In a semiconductor device in which two semiconductor chips are stacked and the two semiconductor chips are sealed with one resin sealing body, one lead frame can correspond to the electrodes provided on the two semiconductor chips. . (3) Workability in the assembly process of the semiconductor device can be improved. (4) The yield of semiconductor devices can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態１である半導体装置の樹脂封
止体の上部を除去した状態の平面図である。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention in a state where an upper portion of a resin sealing body is removed.

【図２】前記半導体装置の樹脂封止体の下部を除去した
状態の底面図である。FIG. 2 is a bottom view of the semiconductor device in a state where a lower portion of a resin sealing body is removed.

【図３】図１に示すＡ−Ａ線に沿う模式的断面図であ
る。FIG. 3 is a schematic cross-sectional view taken along line AA shown in FIG.

【図４】図１に示すＢ−Ｂ線に沿う模式的断面図であ
る。FIG. 4 is a schematic sectional view taken along line BB shown in FIG.

【図５】前記半導体装置の製造プロセスで用いられるリ
ードフレームの平面図である。FIG. 5 is a plan view of a lead frame used in a manufacturing process of the semiconductor device.

【図６】前記リードフレームの表裏面識別記号の実施例
を説明するための平面図である。FIG. 6 is a plan view for explaining an embodiment of front and back surface identification symbols of the lead frame.

【図７】前記リードフレームの表裏面識別記号の別の実
施例を説明するための平面図である。FIG. 7 is a plan view for explaining another embodiment of the front and back surface identification symbols of the lead frame.

【図８】前記リードフレームの表裏面識別記号の別の実
施例を説明するための平面図である。FIG. 8 is a plan view for explaining another embodiment of the front and back surface identification symbols of the lead frame.

【図９】前記半導体装置の製造方法を説明するための模
式的断面図である。FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device.

【図１０】前記半導体装置の製造方法を説明するための
模式的断面図である。FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device.

【図１１】前記半導体装置の製造方法を説明するための
模式的断面図である。FIG. 11 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device.

【図１２】前記半導体装置の製造方法を説明するための
模式的断面図である。FIG. 12 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device.

【図１３】前記半導体装置を実装基板に実装した状態の
要部断面図である。FIG. 13 is a sectional view of a principal part in a state where the semiconductor device is mounted on a mounting board.

【図１４】本発明の実施形態２である半導体装置の樹脂
封止体の上部を除去した状態の平面図である。FIG. 14 is a plan view of the semiconductor device according to the second embodiment of the present invention in a state where an upper portion of a resin sealing body is removed.

【図１５】図１１に示すＣ−Ｃ線に沿う模式的断面図で
ある。FIG. 15 is a schematic sectional view taken along the line CC shown in FIG. 11;

【図１６】図１１に示すＤ−Ｄ線に沿う模式的断面図で
ある。FIG. 16 is a schematic cross-sectional view taken along the line DD shown in FIG.

【図１７】前記半導体装置の製造プロセスで用いられる
リードフレームの平面図である。FIG. 17 is a plan view of a lead frame used in a manufacturing process of the semiconductor device.

【図１８】本発明の実施形態３である半導体装置の樹脂
封止体の上部を除去した状態の平面図である。FIG. 18 is a plan view of the semiconductor device according to the third embodiment of the present invention in a state where an upper portion of a resin sealing body is removed.

【図１９】図１５に示すＥ−Ｅ線に沿う模式的断面図で
ある。FIG. 19 is a schematic cross-sectional view taken along the line EE shown in FIG.

【図２０】前記半導体装置の製造プロセスで用いられる
リードフレームの平面図である。FIG. 20 is a plan view of a lead frame used in the manufacturing process of the semiconductor device.

【符号の説明】[Explanation of symbols]

１，２，３…半導体装置、４，５…半導体チップ、６…
電極、７…接着層、８，８Ａ，８Ｂ…支持リード、９…
接着層、１０Ａ，１０Ｂ…リード、１１…ワイヤ、１２
…樹脂封止体、ＬＦ１，ＬＦ２，ＬＦ３…リードフレー
ム、１４…リードフレーム枠体、１４Ａ，１４Ｂ，１４
Ｃ…リードフレームの表裏面識別記号。1,2,3 ... semiconductor device, 4,5 ... semiconductor chip, 6 ...
Electrode, 7 ... adhesive layer, 8, 8A, 8B ... supporting lead, 9 ...
Adhesive layer, 10A, 10B ... lead, 11 ... wire, 12
... Resin sealing body, LF1, LF2, LF3 ... Lead frame, 14 ... Lead frame frame, 14A, 14B, 14
C: Lead frame front / back identification code.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/50 (72)発明者 増田 正親 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業本部内 (72)発明者 井手 琢二 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業本部内 (72)発明者 藤岡 俊一郎 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業本部内 Ｆターム(参考） 5F044 AA20 EE02 GG07 5F067 AA01 AA02 AB02 BA06 BE02 CB00 DE01 DF16 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/50 (72) Inventor Masachika Masuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. Hitachi, Ltd. Semiconductor Business Headquarters (72) Inventor Takuji Ide 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd.Semiconductor Business Headquarters Co., Ltd. No. 20-1 F-term in the Semiconductor Division, Hitachi, Ltd. F-term (reference) 5F044 AA20 EE02 GG07 5F067 AA01 AA02 AB02 BA06 BE02 CB00 DE01 DF16

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 方形状の半導体基板の回路形成面の第一
辺に沿って複数の外部電極（パッド）が配列された第１
及び第２の２つの半導体チップを準備する工程と、 前記第１及び第２の半導体チップの夫々を、前記第１半
導体チップの第１辺と前記第２半導体チップの第１辺と
が反対側になるように、前記回路形成面（表面）と反対
側の面（裏面）同志を向い合せ、かつ前記外部電極の配
列方向と直交する方向に位置をずらした積層状態で接着
固定する工程と、 該接着固定された第１及び第２の半導体チップの積層体
の前記第１半導体チップの回路形成面に支持リードを接
着固定する工程と、 前記第１半導体チップの各外部電極と表面識別記号のリ
ードフレームのリードのインナー部とを導電性のワイヤ
を介して電気的に接続する工程と、 前記第２半導体チップの各外部電極と裏面識別記号のリ
ードフレームのリードのインナー部とを導電性のワイヤ
を介して電気的に接続する工程と、 前記第１及び第２の半導体チップ、ワイヤならびにリー
ドのインナー部を樹脂により封止する工程とを備えたこ
とを特徴とする半導体装置の製造方法。A first semiconductor substrate having a plurality of external electrodes (pads) arranged along a first side of a circuit forming surface of a rectangular semiconductor substrate;
And a step of preparing two second semiconductor chips; and setting each of the first and second semiconductor chips such that a first side of the first semiconductor chip is opposite to a first side of the second semiconductor chip. Bonding and fixing in a laminated state in which the surfaces (rear surface) opposite to the circuit forming surface (front surface) face each other and are displaced in a direction perpendicular to the arrangement direction of the external electrodes, A step of bonding and fixing a support lead to a circuit forming surface of the first semiconductor chip of the stacked body of the first and second semiconductor chips bonded and fixed; Electrically connecting the inner part of the lead of the lead frame to the inner part of the lead of the second semiconductor chip via a conductive wire; Wire And a step of sealing the first and second semiconductor chips, wires, and inner portions of the leads with a resin. 【請求項２】 前記支持リードは、電源リード又はＧＮ
Ｄリードと兼用する構造であることを特徴とする請求項
１に記載の半導体装置の製造方法。2. The power supply lead or GN.
2. The method according to claim 1, wherein the semiconductor device has a structure also used as a D lead. 【請求項３】 前記支持リードの接着固定位置がリード
の高さと同一平面にあることを特徴とする請求項１又は
２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the bonding position of the support lead is on the same plane as the height of the lead. 【請求項４】 前記リードのアウター部は、前記樹脂封
止体の厚さ方向において、樹脂封止体の中心線を含む水
平平面よりも上方向の位置に設けられていることを特徴
とする請求項１乃至３のうちいずれか１項に記載の半導
体装置の製造方法。4. An outer portion of the lead is provided at a position above a horizontal plane including a center line of the resin sealing body in a thickness direction of the resin sealing body. A method for manufacturing a semiconductor device according to claim 1.
JP10330452A 1998-11-20 1998-11-20 Manufacture of semiconductor device Withdrawn JP2000156464A (en)

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JP10330452A JP2000156464A (en) 1998-11-20 1998-11-20 Manufacture of semiconductor device

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JP2007137316A Division JP4750076B2 (en) 2007-05-24 2007-05-24 Manufacturing method of semiconductor device

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Publication Number Publication Date
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Family

ID=18232787

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Application Number Title Priority Date Filing Date
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Cited By (9)

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US6353265B1 (en) 2001-02-06 2002-03-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6724074B2 (en) 2001-12-27 2004-04-20 Samsung Electronics Co., Ltd. Stack semiconductor chip package and lead frame
US6737736B2 (en) 2001-02-08 2004-05-18 Renesas Technology Corp. Semiconductor device
JP2007251202A (en) * 2007-05-24 2007-09-27 Renesas Technology Corp Manufacturing method of semiconductor device
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US6353265B1 (en) 2001-02-06 2002-03-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6737736B2 (en) 2001-02-08 2004-05-18 Renesas Technology Corp. Semiconductor device
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US6965154B2 (en) 2001-02-08 2005-11-15 Renesas Technology Corp. Semiconductor device
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US6724074B2 (en) 2001-12-27 2004-04-20 Samsung Electronics Co., Ltd. Stack semiconductor chip package and lead frame
KR100447869B1 (en) * 2001-12-27 2004-09-08 삼성전자주식회사 Stack Semiconductor Chip Package Having Multiple I/O Pins and Lead Frame Suitable For Use in Such a Stack Semiconductor Chip Package
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