JP2954108B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP2954108B2
JP2954108B2 JP9256988A JP25698897A JP2954108B2 JP 2954108 B2 JP2954108 B2 JP 2954108B2 JP 9256988 A JP9256988 A JP 9256988A JP 25698897 A JP25698897 A JP 25698897A JP 2954108 B2 JP2954108 B2 JP 2954108B2
Authority
JP
Japan
Prior art keywords
conductive
semiconductor device
semiconductor chip
insulating tape
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9256988A
Other languages
Japanese (ja)
Other versions
JPH1197472A (en
Inventor
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP9256988A priority Critical patent/JP2954108B2/en
Priority to US09/157,474 priority patent/US6011306A/en
Priority to CN98120024A priority patent/CN1213176A/en
Publication of JPH1197472A publication Critical patent/JPH1197472A/en
Application granted granted Critical
Publication of JP2954108B2 publication Critical patent/JP2954108B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に関し、特にリードオンチィップ（ＬＯＣ）
型のモールド・ボールグリッドアレイ（ＢＧＡ）半導体
装置およびその製造方法に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a lead-on-chip (LOC).
The present invention relates to a mold ball grid array (BGA) semiconductor device and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】一般的な従来のＬＯＣ構造のＢＧＡ半導
体装置は、図７の斜視図に示すように、半導体チップ１
上に絶縁接着テープ２２によりリード１９を接合し、半
導体チップ１上のパッド２からポンディングワイヤ３を
リード１９の端部にポンディングしている。このポンデ
ィングワイヤ３を含む半導体チップ１は、モールド樹脂
４により樹脂封入された後、リード１９上に半田ボール
１０を搭載して半導体装置を完成している。この場合、
ポンディングはパッド１０からリード１９の隙間の外側
斜め上方から行われることになる。2. Description of the Related Art A general BGA semiconductor device having a conventional LOC structure has a semiconductor chip 1 as shown in a perspective view of FIG.
Leads 19 are joined to each other by an insulating adhesive tape 22, and the bonding wires 3 are bonded to the ends of the leads 19 from the pads 2 on the semiconductor chip 1. The semiconductor chip 1 including the bonding wires 3 is sealed with a molding resin 4 and then mounted with solder balls 10 on leads 19 to complete a semiconductor device. in this case,
Bonding is performed from obliquely above the outside of the gap between the pad 10 and the lead 19.

【０００３】[0003]

【発明が解決しようとする課題】上述した従来例の半導
体装置では、半導体チップ１が小さくなった時、または
多ピンとなった時に、リード１９は支持のためのリード
フレーム２０と接続する必要があり、リード１９どうし
の間隔が極めて狭くなり、ポンディングワイヤ３をポン
ディングする際に用いられるワイヤボンディング装置の
キャピラリの挿入が困難になり、ワイヤボンディングが
不可能となるという問題がある。In the above-described conventional semiconductor device, when the semiconductor chip 1 becomes smaller or has more pins, the leads 19 need to be connected to a lead frame 20 for support. In addition, the distance between the leads 19 becomes extremely small, so that it becomes difficult to insert a capillary of a wire bonding apparatus used for bonding the bonding wire 3 and wire bonding becomes impossible.

【０００４】本発明の目的は、このような問題を解決
し、半導体チップの小型化、多ピン化に対応してリード
を不要とした接続構造をもった半導体装置およびその製
造方法を提供することにある。An object of the present invention is to solve the above problems and to provide a semiconductor device having a connection structure which eliminates the need for leads in response to the miniaturization of semiconductor chips and the increase in the number of pins, and a method of manufacturing the same. It is in.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体装置の構
成は、半導体チップ上に部分的に導電部を形成した絶縁
性樹脂シャフトが接合され、前記半導体チップのパッド
から前記樹脂シャフトの導電部にボンディングワイヤが
接続され、この導電部に外部接続端子が接続されたこと
特徴とし、また半導体チップ上に部分的に導電パッド部
を形成した絶縁性テープが接合され、前記半導体チップ
のパッドから前記絶縁性テープの導電パッド部にボンデ
ィングワイヤが接続され、この導電パッド部に外部接続
端子が接続されたことを徴とする。According to the structure of the semiconductor device of the present invention, an insulating resin shaft having a conductive portion formed partially on a semiconductor chip is joined, and a conductive portion of the resin shaft is connected to a pad of the semiconductor chip. A bonding wire is connected to the conductive portion, and an external connection terminal is connected to the conductive portion.An insulating tape having a conductive pad portion partially formed on the semiconductor chip is bonded to the semiconductor chip. A bonding wire is connected to the conductive pad portion of the insulating tape, and an external connection terminal is connected to the conductive pad portion.

【０００６】本発明において、絶縁性テープの導電パッ
ド部が導電ピンを介して外部接続端子に接続されること
もでき、また外部接続端子を半田ボールとしてボールグ
リッドアレイ構造とすることもできる。In the present invention, the conductive pad portion of the insulating tape may be connected to an external connection terminal via a conductive pin, or the external connection terminal may be a solder ball to form a ball grid array structure.

【０００７】さらに本発明の半導体装置の製造方法は、
半導体チップ上に部分的に導電部が形成された絶縁性樹
脂シャフトまたは絶縁性テープを接合し、前記半導体チ
ップのパッドから前記樹脂シャフトまたは絶縁性テープ
の導電部にワイヤボンディングによりワイヤを接続し、
この導電部に外部接続端子を接続することを特徴とし、
また本発明において、ワイヤを接続した半導体チップを
樹脂封入した後、樹脂シャフトまたは絶縁性テープの導
電部表面に半田ボールを接合してボールグリッドアレイ
構造とすることもできる。Further, a method of manufacturing a semiconductor device according to the present invention
Bonding an insulating resin shaft or an insulating tape having a conductive portion formed partially on the semiconductor chip, connecting a wire from the pad of the semiconductor chip to the conductive portion of the resin shaft or the insulating tape by wire bonding,
An external connection terminal is connected to the conductive portion,
Further, in the present invention, after encapsulating the semiconductor chip to which the wires are connected with the resin, solder balls may be bonded to the surface of the conductive portion of the resin shaft or the insulating tape to form a ball grid array structure.

【０００８】本発明の構成によれば、半導体チップから
リードの隙間を通ることなく、最短距離でパッドとリー
ドとを接続することができ、半導体装置を小型化するこ
とが可能となる。According to the structure of the present invention, the pad and the lead can be connected at the shortest distance without passing through the gap between the semiconductor chip and the lead, and the semiconductor device can be reduced in size.

【０００９】[0009]

【発明の実施の形態】次に本発明の実施の形態を図面に
より説明する。図１（ａ）（ｂ）は、本発明の一実施形
態のリードの代りとなる絶縁樹脂シャフトを用いた半導
体装置の部分破砕平面図およびその断面図である。本実
施形態は、従来例のリードの代りに、半田めっき部８等
の低融点金属による導電部を設けた絶縁樹脂シャフト７
を用いている。すなわち図１（ａ）において、半導体チ
ップ１はリードフレーム（２０）のアイランド５上に銀
ペースト６を接着剤にして接合され搭載される。この半
導体チップ１上のパッド２からボンディングワイヤ３に
より絶縁樹脂シャフト７の半田めっき部８に接合され、
この接合の終了した半導体チップ１全体は封止樹脂４に
より封止された後、絶縁樹脂シャフト７の半田めっき部
８の配置に対応する個所に半田ボール１０を搭載し接合
する。Embodiments of the present invention will now be described with reference to the drawings. FIGS. 1A and 1B are a partially broken plan view and a cross-sectional view of a semiconductor device using an insulating resin shaft as a substitute for a lead according to an embodiment of the present invention. In this embodiment, an insulating resin shaft 7 provided with a conductive portion made of a low melting point metal such as a solder plated portion 8 instead of the lead of the conventional example.
Is used. That is, in FIG. 1A, the semiconductor chip 1 is mounted on the island 5 of the lead frame (20) by using the silver paste 6 as an adhesive. The pads 2 on the semiconductor chip 1 are joined to the solder plating portions 8 of the insulating resin shaft 7 by bonding wires 3,
After the entirety of the semiconductor chip 1 after the joining is sealed with the sealing resin 4, the solder balls 10 are mounted on portions of the insulating resin shaft 7 corresponding to the positions of the solder plating portions 8 and joined.

【００１０】この絶縁樹脂シャフト７は、図２の工程順
断面図のように製造される。まず図２（ａ）のように、
絶縁性の樹脂材料で円柱状のシャフト７を形成するが、
このシャフト形状は四角柱でもよい。次に図２（ｂ）の
ように、半田めっきを付けない個所にレジスト１１を塗
布する。次に図２（ｃ）のように、めっきのベース金属
となるパラジウム等の金属を蒸着や薬液によりベース金
属蒸着部１２に被着させる。次に図２（ｄ）のように、
無電解めっき法によりシャフト半田めっき１３を付着さ
せ、図２（ｅ）のように、最初のレジスト１１を除去
し、半田めっき部１３を残す。The insulating resin shaft 7 is manufactured as shown in the sectional view of FIG. First, as shown in FIG.
The cylindrical shaft 7 is formed of an insulating resin material.
This shaft shape may be a square pole. Next, as shown in FIG. 2B, a resist 11 is applied to a portion where no solder plating is applied. Next, as shown in FIG. 2C, a metal such as palladium, which is a base metal for plating, is deposited on the base metal vapor deposition section 12 by vapor deposition or a chemical. Next, as shown in FIG.
The shaft solder plating 13 is adhered by the electroless plating method, and the first resist 11 is removed as shown in FIG.

【００１１】本実施形態の製造方法を、図３，図４によ
り説明する。まず図３（ａ）（ｂ）の平面図および断面
図に示すように、このリードフレーム２０には１つのア
イランド５の両側（左右）の吊りリード１４部分に支持
板１５が垂直に配設されている。このアイランド５上に
半導体チップ１が銀ペースト６を接着剤にして接合し搭
載される。The manufacturing method of this embodiment will be described with reference to FIGS. First, as shown in the plan view and the cross-sectional view of FIGS. 3A and 3B, a support plate 15 is vertically disposed on the suspension frame 14 on both sides (left and right) of one island 5 in the lead frame 20. ing. The semiconductor chip 1 is mounted on the island 5 by bonding using the silver paste 6 as an adhesive.

【００１２】次に図４（ａ）に示すように、半導体チッ
プ１上に、図２で製造した絶縁樹脂シャフト７を絶縁性
接着剤９により接着する。さらに図４（ｂ）に示すよう
に、半導体チップ１上のパッド２から支持板１５に向っ
てボンディングワイヤ３を張り、パッド２およびシャフ
ト半田めっき部１３をワイヤボンディングして接合す
る。次に図４（ｃ）に示すように、シャフト半田めっき
部１３の端部でワイヤ３を切り離し、支持板１５を取り
外す。そして図４（ｄ）に示すように、ワイヤ３の接続
された半導体チップ１を封止樹脂４により封止し、シャ
フト半田めっき部１３に対応する個所に半田ボール１０
を搭載し接合する。Next, as shown in FIG. 4A, the insulating resin shaft 7 manufactured in FIG. Further, as shown in FIG. 4B, a bonding wire 3 is extended from the pad 2 on the semiconductor chip 1 to the support plate 15, and the pad 2 and the shaft solder plating portion 13 are bonded by wire bonding. Next, as shown in FIG. 4C, the wire 3 is cut off at the end of the shaft solder plating portion 13, and the support plate 15 is removed. Then, as shown in FIG. 4D, the semiconductor chip 1 to which the wires 3 are connected is sealed with a sealing resin 4 and solder balls 10 are formed at positions corresponding to the shaft solder plating portions 13.
Is mounted and joined.

【００１３】本実施形態のように、シャフト半田めっき
部１３を設けた絶縁樹脂シャフト７を介在させることに
より、リード１９を用いずにパッド２から半田めっき部
１３を介してワイヤ３を外部端子の半田ボール１０への
接続が可能となり、半導体装置を小形化することができ
る。As in the present embodiment, by interposing the insulating resin shaft 7 provided with the shaft solder plating portion 13, the wire 3 is connected to the external terminal from the pad 2 via the solder plating portion 13 without using the lead 19. Connection to the solder ball 10 becomes possible, and the size of the semiconductor device can be reduced.

【００１４】図５（ａ）（ｂ）は、本発明の第２の実施
形態のリードの代りとなる絶縁テープを用いた半導体装
置の斜視図およびその断面図である。本実施形態では、
図１の絶縁樹脂シャフト７の代りに、導電性テープパッ
ド１８を載置しピン１６を付加した絶縁テープ１７を用
いたものである。このような絶縁テープ１７は、図５
（ａ）に示すように、半導体チップ１上に接合し、この
絶縁テープ１７上のテープパッド１８からワイヤ３にワ
イヤボンディンフを行なう。この際テープパッド１８に
はワイヤ３から延長したピン１６が、テープパッド１８
とほぼ垂直に配設される。この状態から、図５（ｂ）に
示すように、ピン１６、ワイヤ３の接続された半導体チ
ップ１を封止樹脂４により封止し、各ピン１６の個所を
樹脂封止せずに、各ピン１６に対応する個所に半田ボー
ル１０を搭載し接合する。FIGS. 5A and 5B are a perspective view and a sectional view of a semiconductor device using an insulating tape instead of a lead according to a second embodiment of the present invention. In this embodiment,
Instead of the insulating resin shaft 7 of FIG. 1, an insulating tape 17 on which a conductive tape pad 18 is placed and a pin 16 is added is used. Such an insulating tape 17 is shown in FIG.
As shown in FIG. 3A, the semiconductor chip 1 is bonded to the semiconductor chip 1, and the wire 3 is bonded to the wire 3 from the tape pad 18 on the insulating tape 17. At this time, a pin 16 extending from the wire 3 is attached to the tape pad 18.
It is arranged almost vertically. From this state, as shown in FIG. 5B, the semiconductor chip 1 to which the pins 16 and the wires 3 are connected is sealed with the sealing resin 4, and each pin 16 is not sealed with a resin. The solder balls 10 are mounted at the locations corresponding to 16 and joined.

【００１５】図６は、本発明の第３の実施形態のリード
の代りとなる絶縁テープを用いた半導体装置の斜視図お
よびその断面図である。本実施形態では、図５のピン１
６を用いずに、絶縁テープ１７上のテープパッド１８に
直接半田ボール１０を搭載し接合したものである。FIG. 6 is a perspective view of a semiconductor device using an insulating tape instead of a lead according to a third embodiment of the present invention, and a sectional view thereof. In the present embodiment, the pin 1 shown in FIG.
6, the solder balls 10 are directly mounted on the tape pads 18 on the insulating tape 17 and joined.

【００１６】これら第２、第３の実施形態においても、
テープパッド１８をもつ絶縁テープ１７を介在させるこ
とにより、リード１９を用いずにワイヤ３を外部端子の
半田ボール１０へ直接接続することが可能となり、同様
に半導体装置を小形化することができる。In these second and third embodiments,
By interposing the insulating tape 17 having the tape pad 18, the wire 3 can be directly connected to the solder ball 10 of the external terminal without using the lead 19, and similarly, the semiconductor device can be downsized.

【００１７】[0017]

【発明の効果】以上説明したように、本発明の構成によ
れば、従来問題であったリードを用いずに、半導体チッ
プのパッドから外部端子の半田ボールへの接続が可能と
なるため、ワイヤボンディングの自由度が向上し、半導
体装置自体を小形化することができるという効果があ
る。As described above, according to the structure of the present invention, it is possible to connect a pad of a semiconductor chip to a solder ball of an external terminal without using a lead, which has been a problem in the prior art. The degree of freedom in bonding is improved, and the semiconductor device itself can be downsized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施形態の半導体装置の部分破砕平
面図およびその断面図。FIG. 1 is a partially fragmented plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

【図２】図１の半導体装置の絶縁樹脂シャフトの処理方
法を説明する部分側面図。FIG. 2 is a partial side view illustrating a method for processing the insulating resin shaft of the semiconductor device of FIG. 1;

【図３】図１の製造工程の半導体チップ搭載時の平面図
および側面図。3A and 3B are a plan view and a side view when a semiconductor chip is mounted in the manufacturing process of FIG. 1;

【図４】図１の製造工程の絶縁樹脂シャフト組立て時の
工程順の断面図。FIG. 4 is a sectional view in the order of steps when assembling the insulating resin shaft in the manufacturing process of FIG.

【図５】本発明の第２の実施形態を示す斜視図および断
面図。FIG. 5 is a perspective view and a sectional view showing a second embodiment of the present invention.

【図６】本発明の第３の実施形態を示す断面図。FIG. 6 is a sectional view showing a third embodiment of the present invention.

【図７】従来例の半導体装置の構造を示す透視斜視図。FIG. 7 is a perspective view showing the structure of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ パッド ３ ボンディングワイヤ ４ モールド樹脂 ５ リードフレームのアイランド ６ 銀ペースト ７ 絶縁樹脂シャフト ８ 半田めっき ９ 接着剤 １０ 半田ボール １１ レジスト １２ ベース金属蒸着部 １３ シャフト半田めっき １４ 吊りリード １５ 支持板 １６ ピン １７ 絶縁テープ １８ テープパッド １９ リード ２０ リードフレーム ２２ 接着テープ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Pad 3 Bonding wire 4 Mold resin 5 Lead frame island 6 Silver paste 7 Insulating resin shaft 8 Solder plating 9 Adhesive 10 Solder ball 11 Resist 12 Base metal vapor deposition part 13 Shaft solder plating 14 Suspended lead 15 Support plate 16 Pin 17 Insulating tape 18 Tape pad 19 Lead 20 Lead frame 22 Adhesive tape

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体チップ上に部分的に導電部を形成
した絶縁性樹脂シャフトが接合され、前記半導体チップ
のパッドから前記樹脂シャフトの導電部にボンディング
ワイヤが接続され、この導電部に外部接続端子が接続さ
れたことを特徴とする半導体装置。An insulating resin shaft having a conductive portion formed partially on a semiconductor chip is joined, a bonding wire is connected from a pad of the semiconductor chip to a conductive portion of the resin shaft, and an external connection is made to the conductive portion. A semiconductor device having terminals connected thereto. 【請求項２】 半導体チップ上に部分的に導電パッド部
を形成した絶縁性テープが接合され、前記半導体チップ
のパッドから前記絶縁性テープの導電パッド部にボンデ
ィングワイヤが接続され、この導電パッド部に外部接続
端子が接続されたことを特徴とする半導体装置。2. An insulating tape in which a conductive pad portion is partially formed on a semiconductor chip is joined, and a bonding wire is connected from a pad of the semiconductor chip to a conductive pad portion of the insulating tape. An external connection terminal is connected to the semiconductor device. 【請求項３】 絶縁性テープの導電パッド部が導電ピン
を介して外部接続端子に接続された請求項２記載の半導
体装置。3. The semiconductor device according to claim 2, wherein the conductive pad portion of the insulating tape is connected to an external connection terminal via a conductive pin. 【請求項４】 外部接続端子を半田ボールとしてボール
グリッドアレイ構造とした請求項１，２または３記載の
半導体装置。4. The semiconductor device according to claim 1, wherein the external connection terminals have a ball grid array structure using solder balls. 【請求項５】 樹脂シャフトの導電部または絶縁性テー
プの導電パッド部が半田めっきからなり、この部分が外
部接続端子となる請求項１乃至４記載の半導体装置。5. The semiconductor device according to claim 1, wherein the conductive portion of the resin shaft or the conductive pad portion of the insulating tape is made of solder plating, and this portion serves as an external connection terminal. 【請求項６】 半導体チップ上に部分的に導電部が形成
された絶縁性樹脂シャフトまたは絶縁性テープを接合
し、前記半導体チップのパッドから前記樹脂シャフトま
たは絶縁性テープの導電部にワイヤボンディングにより
ワイヤを接続し、この導電部に外部接続端子を接続する
ことを特徴とする半導体装置の製造方法。6. An insulating resin shaft or an insulating tape in which a conductive portion is partially formed on a semiconductor chip, and bonding is performed by wire bonding from a pad of the semiconductor chip to a conductive portion of the resin shaft or the insulating tape. A method for manufacturing a semiconductor device, comprising: connecting a wire; and connecting an external connection terminal to the conductive portion. 【請求項７】 絶縁性テープの導電部がワイヤ接続され
た後、その導電部から前記ワイヤを延長して導電ピンを
形成し、この導電ピンを外部接続端子に接続する請求項
６記載の半導体装置の製造方法。7. The semiconductor according to claim 6, wherein after the conductive portion of the insulating tape is wire-connected, the wire is extended from the conductive portion to form a conductive pin, and the conductive pin is connected to an external connection terminal. Device manufacturing method. 【請求項８】 ワイヤを接続した半導体チップを樹脂封
入した後、樹脂シャフトまたは絶縁性テープの導電部表
面に半田ボールを接合してボールグリッドアレイ構造と
する請求項６または７記載の半導体装置の製造方法。8. The semiconductor device according to claim 6, wherein after encapsulating the semiconductor chip to which the wires are connected with a resin, solder balls are bonded to the surface of the conductive portion of the resin shaft or the insulating tape to form a ball grid array structure. Production method.
JP9256988A 1997-09-22 1997-09-22 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2954108B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP9256988A JP2954108B2 (en) 1997-09-22 1997-09-22 Semiconductor device and manufacturing method thereof
US09/157,474 US6011306A (en) 1997-09-22 1998-09-21 Semiconductor device and method for fabricating same
CN98120024A CN1213176A (en) 1997-09-22 1998-09-22 Semiconductor device and method for fabricating same

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Application Number Priority Date Filing Date Title
JP9256988A JP2954108B2 (en) 1997-09-22 1997-09-22 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH1197472A JPH1197472A (en) 1999-04-09
JP2954108B2 true JP2954108B2 (en) 1999-09-27

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US7071421B2 (en) * 2003-08-29 2006-07-04 Micron Technology, Inc. Stacked microfeature devices and associated methods

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CN1213176A (en) 1999-04-07
US6011306A (en) 2000-01-04
JPH1197472A (en) 1999-04-09

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