JP2000294719A - Lead frame, semiconductor device using the same, and manufacture thereof - Google Patents
Lead frame, semiconductor device using the same, and manufacture thereofInfo
- Publication number
- JP2000294719A JP2000294719A JP10263299A JP10263299A JP2000294719A JP 2000294719 A JP2000294719 A JP 2000294719A JP 10263299 A JP10263299 A JP 10263299A JP 10263299 A JP10263299 A JP 10263299A JP 2000294719 A JP2000294719 A JP 2000294719A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead
- terminal connection
- lead frame
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体製造技術に
関し、特に、小形の半導体装置の半田実装における接続
信頼性向上に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a technology effective when applied to improve connection reliability in solder mounting of a small semiconductor device.
【０００２】[0002]
【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.
【０００３】小形化を図った半導体装置として、ＣＳＰ
（Chip Scale Package) と呼ばれるチップサイズまたは
半導体チップより若干大きい程度の小形パッケージが開
発されている。[0003] As a miniaturized semiconductor device, CSP is used.
A small package called a “Chip Scale Package” having a chip size or slightly larger than a semiconductor chip has been developed.
【０００４】このＣＳＰのうち、少ピン系のＣＳＰに
は、低コスト化のためにＱＦＰ（QuadFlat Package)や
ＳＯＰ（Small Outline Package)用のリードフレームを
使用しているものがあり、この構造のＣＳＰでは、樹脂
封止によって形成された封止部の裏面（半導体装置実装
側の面）内に全てのリードがその端子接続面を露出して
配置される。[0004] Among these CSPs, some CSPs with a small number of pins use a lead frame for a QFP (QuadFlat Package) or SOP (Small Outline Package) for cost reduction. In the CSP, all the leads are arranged on the back surface (the surface on the semiconductor device mounting side) of the sealing portion formed by resin sealing with their terminal connection surfaces exposed.
【０００５】その際、小形化を図るための片面モールド
構造となり、その結果、封止部の裏面において各リード
の端子接続面は、封止部の裏面とほぼ同一の高さに配置
されている。[0005] At this time, a single-sided molded structure for miniaturization is obtained. As a result, the terminal connection surface of each lead is arranged at substantially the same height as the back surface of the sealing portion on the back surface of the sealing portion. .
【０００６】つまり、封止部の裏面とリードの端子接続
面とがほぼ同一面に形成される（このような構造を、以
降、ボトムリードタイプと呼ぶ）。That is, the back surface of the sealing portion and the terminal connection surface of the lead are formed on substantially the same surface (such a structure is hereinafter referred to as a bottom lead type).
【０００７】なお、種々のＣＳＰの構造については、例
えば、日刊工業新聞社１９９７年３月１日発行、「表面
実装技術１９９７／３月号／Ｖｏｌ．７、Ｎｏ．３」、
１〜９頁に記載されている。[0007] Regarding the structure of various CSPs, see, for example, Nikkan Kogyo Shimbun, March 1, 1997, “Surface Mount Technology 1997 / March / Vol.7, No. 3,”
It is described on pages 1-9.
【０００８】[0008]
【発明が解決しようとする課題】ところが、前記した技
術のボトムリードタイプのＣＳＰにおいては、封止部の
裏面とリードの端子接続面とがほぼ同一面に形成されて
いるため、実装基板などに半田付けによってこのＣＳＰ
を実装した際に、ＣＳＰのリードと基板端子との間に形
成される半田フィレット（半田接合部のすみ肉）が非常
に少なくなる。However, in the bottom lead type CSP of the above-mentioned technology, the back surface of the sealing portion and the terminal connection surface of the lead are formed on substantially the same surface, so that the CSP can be mounted on a mounting substrate or the like. This CSP by soldering
When the package is mounted, the amount of solder fillets (fillers at the solder joints) formed between the leads of the CSP and the board terminals becomes very small.
【０００９】その結果、ＣＳＰの基板実装時の接続信頼
性の低下が問題となる。As a result, there is a problem that the connection reliability of the CSP at the time of mounting on a substrate is reduced.
【００１０】本発明の目的は、実装時の半田接続におけ
る接続信頼性の向上を図るリードフレームおよびそれを
用いた半導体装置ならびにその製造方法を提供すること
にある。An object of the present invention is to provide a lead frame for improving connection reliability in solder connection at the time of mounting, a semiconductor device using the same, and a method of manufacturing the same.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００１３】すなわち、本発明のリードフレームは、半
導体チップを支持可能なチップ支持部と、前記チップ支
持部の周囲に配置され、前記半導体チップを樹脂封止し
て形成される封止部の半導体装置実装側の面内にこの面
と同一面となって露出する端子接続面を備え、前記端子
接続面に凹部または凸部が形成された複数のリードとを
有するものである。That is, the lead frame of the present invention comprises a chip supporting portion capable of supporting a semiconductor chip, and a semiconductor of a sealing portion disposed around the chip supporting portion and formed by resin-sealing the semiconductor chip. A terminal connection surface is provided in the surface on the device mounting side and exposed to be flush with the surface, and a plurality of leads having a concave portion or a convex portion formed on the terminal connection surface.
【００１４】また、本発明の半導体装置は、半導体チッ
プを支持するチップ支持部と、前記半導体チップが樹脂
封止されて形成された封止部と、前記チップ支持部の周
囲に配置され、前記封止部の半導体装置実装側の面内に
この面とほぼ同一面となって露出する端子接続面を備
え、前記端子接続面に凹部または凸部が形成された複数
のリードと、前記半導体チップの表面電極とこれに対応
する前記リードとを電気的に接続する接続部材とを有す
るものである。Further, the semiconductor device of the present invention is arranged such that a chip supporting portion for supporting a semiconductor chip, a sealing portion formed by sealing the semiconductor chip with a resin, and a periphery of the chip supporting portion, A plurality of leads provided with a terminal connection surface which is substantially coplanar with the surface and exposed in a surface of the sealing portion on the semiconductor device mounting side, wherein the terminal connection surface is provided with a concave portion or a convex portion; And a connection member for electrically connecting the surface electrode and the corresponding lead.
【００１５】これにより、実装基板などへの半田実装時
に端子接続面の凹部または凸部によって半田接合部の半
田接合面積を増加させることができるとともに、凹部ま
たは凸部により、配置される半田の量を増やすことがで
きる。[0015] With this, the solder joint area of the solder joint can be increased by the concave or convex portion of the terminal connection surface when the solder is mounted on the mounting board or the like, and the amount of the solder to be arranged can be increased by the concave or convex portion. Can be increased.
【００１６】したがって、ボトムリードタイプの小形の
半導体装置の実装時の半田付け強度を向上させることが
でき、その結果、半田接続における接続信頼性を向上で
きる。Therefore, the soldering strength at the time of mounting the small semiconductor device of the bottom lead type can be improved, and as a result, the connection reliability in the solder connection can be improved.
【００１７】また、本発明の半導体装置の製造方法は、
半導体チップを樹脂封止して形成される封止部の半導体
装置実装側の面内にこの面と同一面となって露出する端
子接続面を備え、前記端子接続面に凹部または凸部が形
成された複数のリードを有するリードフレームを準備す
る工程と、前記リードフレームのチップ支持部と前記半
導体チップとを接合する工程と、前記半導体チップの表
面電極とこれに対応する前記リードフレームの前記リー
ドとを電気的に接続する工程と、前記半導体チップを樹
脂封止して、前記凹部または前記凸部が形成された前記
リードの前記端子接続面を前記半導体装置実装側の面内
にこの面と同一面となって露出させて前記封止部を形成
する工程と、複数の前記リードを前記リードフレームの
枠部から分離する工程とを有するものである。Further, a method of manufacturing a semiconductor device according to the present invention
A semiconductor chip is provided with a terminal connection surface which is exposed in the same plane as a semiconductor device mounting side surface of a sealing portion formed by resin sealing the semiconductor chip, and a concave portion or a convex portion is formed on the terminal connection surface. Preparing a lead frame having a plurality of leads formed thereon, bonding a chip supporting portion of the lead frame to the semiconductor chip, and surface electrodes of the semiconductor chip and the corresponding leads of the lead frame. Electrically connecting the semiconductor chip to the semiconductor chip, and sealing the semiconductor chip with a resin, and forming the terminal connection surface of the lead on which the concave portion or the convex portion is formed in a surface on the semiconductor device mounting side. The method includes a step of forming the sealing portion by exposing the same surface, and a step of separating the plurality of leads from a frame of the lead frame.
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１９】図１は本発明によるリードフレームの構造
の実施の形態の一例を示す部分平面図、図２は本発明の
半導体装置の構造の実施の形態の一例を示す図であり、
（ａ）は平面図、（ｂ）は底面図、図３は図２に示す半
導体装置の構造を示す断面図、図４は図２に示す半導体
装置におけるリードの端子接続面の凹部の構造を示す図
であり、（ａ）は図２（ｂ）におけるＡ部の詳細構造を
示す拡大図、（ｂ）は（ａ）のリードのＢ−Ｂ断面を示
す断面図、図５は本発明による半導体装置の製造方法の
実施の形態の一例を示す製造プロセス図と各工程ごとの
断面図、図６は図２に示す半導体装置の実装基板への実
装状態の構造の一例を示す部分断面図である。FIG. 1 is a partial plan view showing an example of an embodiment of the structure of a lead frame according to the present invention, and FIG. 2 is a diagram showing an example of an embodiment of the structure of a semiconductor device of the present invention.
3A is a plan view, FIG. 3B is a bottom view, FIG. 3 is a cross-sectional view showing the structure of the semiconductor device shown in FIG. 2, and FIG. 2A is an enlarged view showing a detailed structure of a portion A in FIG. 2B, FIG. 2B is a cross-sectional view showing a BB cross section of the lead of FIG. 2A, and FIG. FIG. 6 is a partial cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 2 in a state of being mounted on a mounting substrate, showing a manufacturing process diagram illustrating an example of an embodiment of a method of manufacturing a semiconductor device and cross-sectional views of respective steps. is there.
【００２０】図１に示す本実施の形態のリードフレーム
１は、小形・樹脂封止形で、かつ面実装形の半導体装置
に用いられるものであり、本実施の形態ではこの半導体
装置の一例として、図２および図３に示すＣＳＰ７を取
り上げて説明する。The lead frame 1 of this embodiment shown in FIG. 1 is used for a small-sized, resin-sealed, and surface-mounted semiconductor device. In this embodiment, the lead frame 1 is an example of this semiconductor device. , CSP7 shown in FIGS. 2 and 3 will be described.
【００２１】なお、ＣＳＰ７は、チップサイズまたは半
導体チップ２より若干大きい程度の小形パッケージであ
り、本実施の形態のＣＳＰ７は、比較的ピン数が少な
く、主に携帯電子機器などに組み込まれるものであり、
モールドによって形成された封止部３の半導体装置実装
側の面（以降、裏面３ａという）内に外部機器の端子な
どと電気的に接続する複数のリード１ａが配置されたエ
リアアレイタイプのものである。The CSP 7 is a small package having a chip size or slightly larger than the semiconductor chip 2. The CSP 7 according to the present embodiment has a relatively small number of pins and is mainly incorporated in a portable electronic device or the like. Yes,
An area array type in which a plurality of leads 1a electrically connected to terminals of an external device and the like are arranged in a surface (hereinafter, referred to as a back surface 3a) of a semiconductor device mounting side of a sealing portion 3 formed by molding. is there.
【００２２】図１〜図４を用いて、図１に示すリードフ
レーム１の構成について説明すると、半導体チップ２を
支持可能なタブ１ｅ（チップ支持部）と、タブ１ｅの周
囲に配置されるとともに、半導体チップ２を樹脂封止し
て形成される封止部３の裏面３ａ（半導体装置実装側の
面）内にこの裏面３ａと同一面となって露出する端子接
続面１ｂを備え、かつ端子接続面１ｂに凹部１ｄが形成
された複数のリード１ａと、タブ１ｅおよび複数のリー
ド１ａを支持する枠部１ｆとからなる薄板状の金属板で
ある。The configuration of the lead frame 1 shown in FIG. 1 will be described with reference to FIGS. 1 to 4. The tab 1e (chip supporting portion) capable of supporting the semiconductor chip 2 is arranged around the tab 1e. A terminal connecting surface 1b exposed on the same surface as the back surface 3a in a back surface 3a (a surface on the semiconductor device mounting side) of the sealing portion 3 formed by resin-sealing the semiconductor chip 2; This is a thin metal plate comprising a plurality of leads 1a having a recess 1d formed in a connection surface 1b, and a frame 1f supporting the tabs 1e and the plurality of leads 1a.
【００２３】なお、リードフレーム１は、図１に示すよ
うに、１枚のリードフレーム１から複数個のＣＳＰ７を
製造することが可能な長尺状の細長い多連のものであ
る。As shown in FIG. 1, the lead frame 1 is a long and narrow multiple unit capable of manufacturing a plurality of CSPs 7 from one lead frame 1.
【００２４】つまり、１枚のリードフレーム１には、１
個のＣＳＰ７に対応したパッケージ領域が複数個形成さ
れており、さらに、その枠部１ｆには、ダイボンディン
グ時やワイヤボンディング時にリードフレーム１を搬送
する際の複数のガイド用長孔１ｇおよび位置決め孔１ｈ
が形成されている。That is, one lead frame 1 has 1
A plurality of package regions corresponding to the CSPs 7 are formed, and a plurality of guide slots 1g and positioning holes for transporting the lead frame 1 at the time of die bonding or wire bonding are formed in the frame portion 1f. 1h
Are formed.
【００２５】なお、リードフレーム１の材料は、例え
ば、銅（Ｃｕ）、鉄（Ｆｅ）、または、鉄とニッケルと
の合金（Ｆｅ−Ｎｉ）などであり、その厚さは、例え
ば、0.１〜0.２ｍｍ程度であるが、前記材料や前記厚さ
などは、これらに限定されるものではない。The lead frame 1 is made of, for example, copper (Cu), iron (Fe), or an alloy of iron and nickel (Fe-Ni). The thickness is about 1 to 0.2 mm, but the material and the thickness are not limited to these.
【００２６】また、リードフレーム１において、各リー
ド１ａやタブ１ｅ、または、ガイド用長孔１ｇや位置決
め孔１ｈなどの各形状パターンは、エッチングまたはプ
レス抜き金型によるプレスによって形成されるものであ
る。In the lead frame 1, each lead 1a and tab 1e, or each shape pattern such as the guide long hole 1g and the positioning hole 1h is formed by etching or pressing by a press-cutting die. .
【００２７】なお、前記各形状パターンが形成された
後、リードフレーム１の表面には、ワイヤボンディング
可能なようにＡｇやＮｉ−Ｐｄ−Ａｕなどのめっき処理
が行われる。After the formation of the shape patterns, the surface of the lead frame 1 is plated with Ag or Ni-Pd-Au so that wire bonding can be performed.
【００２８】また、本実施の形態のリードフレーム１に
おけるリード１ａの端子接続面１ｂに形成された凹部１
ｄは、図４（ａ）に示すように、細長い端子接続面１ｂ
の長手方向に沿ってその中央付近に細長く形成された溝
状を成すものであり、その深さは、例えば、リードフレ
ーム１の板厚の１／２程度のものである。The recess 1 formed in the terminal connection surface 1b of the lead 1a in the lead frame 1 of the present embodiment.
d is an elongated terminal connection surface 1b as shown in FIG.
Is formed in an elongated shape near its center along the longitudinal direction of the lead frame 1, and has a depth of, for example, about half the plate thickness of the lead frame 1.
【００２９】さらに、この凹部１ｄは、例えば、エッチ
ングによって形成される。The recess 1d is formed by, for example, etching.
【００３０】なお、各リード１ａは、それぞれの端子接
続面１ｂが、半導体チップ２が樹脂封止されて封止部３
が形成された際にこの封止部３の裏面３ａとほぼ同一面
に露出して配置されている。Each of the leads 1a has a terminal connection surface 1b formed by sealing the semiconductor chip 2 with a resin.
Are formed and exposed on substantially the same plane as the back surface 3a of the sealing portion 3.
【００３１】これにより、このリード１ａを有するＣＳ
Ｐ７においては、図６に示すように半田８を用いた実装
を行う際に、リード１ａの端子接続面１ｂの凹部１ｄに
半田８が埋め込まれるため、半田接続における半田接合
部に配置される半田量を増加でき、その結果、半田接続
強度を向上できる。Thus, the CS having the lead 1a
In P7, when the mounting using the solder 8 is performed as shown in FIG. 6, the solder 8 is embedded in the concave portion 1d of the terminal connection surface 1b of the lead 1a. As a result, the solder connection strength can be improved.
【００３２】次に、図２、図３および図４に示す本実施
の形態のＣＳＰ７（半導体装置）の構成について説明す
る。Next, the configuration of the CSP 7 (semiconductor device) of this embodiment shown in FIGS. 2, 3 and 4 will be described.
【００３３】前記ＣＳＰ７は、チップサイズの小形の樹
脂封止形で、かつ面実装形のものであるとともに、図１
に示すリードフレーム１を用いて製造したものであり、
複数のリード１ａが、図２（ｂ）に示すように、封止部
３の裏面３ａ内に各端子接続面１ｂを露出させて配置さ
れたボトムリードタイプのものである。The CSP 7 is a small-sized chip-sized resin-sealed type and a surface-mounted type.
And manufactured using the lead frame 1 shown in FIG.
As shown in FIG. 2B, the plurality of leads 1a are of a bottom lead type in which the respective terminal connection surfaces 1b are exposed in the back surface 3a of the sealing portion 3.
【００３４】前記ＣＳＰ７の構成について説明すると、
主面２ｂに半導体集積回路が形成された半導体チップ２
を支持するチップ支持部であるタブ１ｅと、半導体チッ
プ２がモールドによって樹脂封止されて形成された封止
部３と、タブ１ｅの周囲に配置されるとともに、封止部
３の裏面３ａ（半導体装置実装側の面）側の面内にこの
面と同一面となって露出する端子接続面１ｂを備え、か
つ端子接続面１ｂに凹部１ｄが形成された複数のリード
１ａと、半導体チップ２のパッド２ａ（表面電極）とこ
れに対応するリード１ａのボンディング面１ｃとを電気
的に接続するボンディングワイヤ４（接続部材）とによ
って構成され、封止部３の裏面３ａとほぼ同一面に各リ
ード１ａの端子接続面１ｂが配置されている。The configuration of the CSP 7 will be described.
Semiconductor chip 2 having semiconductor integrated circuit formed on main surface 2b
A tab 1e as a chip supporting portion for supporting the semiconductor chip 2, a sealing portion 3 formed by resin-sealing the semiconductor chip 2 with a mold, and a rear surface 3a of the sealing portion 3 ( A plurality of leads 1a having a terminal connection surface 1b exposed on the same surface as the surface on the side of the semiconductor device mounting side) and having a recess 1d formed in the terminal connection surface 1b; And a bonding wire 4 (connecting member) for electrically connecting the pad 2a (surface electrode) of the sealing member 3 to the bonding surface 1c of the lead 1a corresponding to the pad 2a. The terminal connection surface 1b of the lead 1a is arranged.
【００３５】すなわち、本実施の形態のＣＳＰ７は、封
止部３の裏面３ａとほぼ同一面に配置された各リード１
ａを封止部３から水平方向の外部に突出させることな
く、封止部３の裏面３ａ内に配置したエリアアレイ構造
であり、各リード１ａの端子接続面１ｂが封止部３の裏
面３ａとほぼ同一面となって配置され、この端子接続面
１ｂに凹部１ｄが形成されているものである。That is, the CSP 7 according to the present embodiment is configured such that each of the leads 1 disposed on substantially the same surface as the back surface 3a of the sealing portion 3
a is arranged in the back surface 3a of the sealing portion 3 without protruding from the sealing portion 3 to the outside in the horizontal direction, and the terminal connection surface 1b of each lead 1a is connected to the back surface 3a of the sealing portion 3. And the terminal connection surface 1b is provided with a concave portion 1d.
【００３６】したがって、ＣＳＰ７におけるリード１ａ
は、インナリードとアウタリードとの両者の機能を併せ
持ったものである。Therefore, the lead 1a in the CSP 7
Has both functions of an inner lead and an outer lead.
【００３７】なお、それぞれのリード１ａには、その外
側端部にリードフレーム１の枠部１ｆから切断分離した
際の切断しろが残留するため、図２（ａ）に示すよう
に、各リード１ａの外側端部が封止部３から数十〜数百
μｍ程度突出する構造になっている。Since each lead 1a has a cutting margin at the outer end thereof when the lead 1a is cut and separated from the frame 1f of the lead frame 1, as shown in FIG. Has a structure in which the outer end portion of the second portion projects from the sealing portion 3 by about several tens to several hundreds μm.
【００３８】また、本実施の形態のＣＳＰ７では、図２
（ｂ）に示すように、タブ１ｅも封止部３の裏面３ａと
同一面に露出して配置されている。Further, in the CSP 7 of the present embodiment, FIG.
As shown in (b), the tab 1e is also exposed and arranged on the same surface as the back surface 3a of the sealing portion 3.
【００３９】これは、半導体チップ２の裏面２ｃ側から
タブ１ｅを介して放熱を行う場合や、半導体チップ２の
裏面２ｃからＧＮＤ電位を実装基板９（図６参照）のＧ
ＮＤ端子などに電気的に接続する場合などに露出させる
構造とするものである。This is because heat is radiated from the back surface 2c side of the semiconductor chip 2 through the tab 1e, or the GND potential is applied from the back surface 2c of the semiconductor chip 2 to the G of the mounting substrate 9 (see FIG. 6).
This is a structure that is exposed when electrically connected to an ND terminal or the like.
【００４０】ただし、タブ１ｅは、封止部３の裏面３ａ
に必ずしも露出させなくてもよく、封止部３の内部に埋
め込む構造としてもよい。However, the tab 1e is connected to the back surface 3a of the sealing portion 3.
It is not always necessary to expose the sealing portion 3, and a structure may be employed in which the sealing portion 3 is embedded.
【００４１】また、本実施の形態のＣＳＰ７には、図３
に示すように、各リード１ａの端子接続面１ｂに半田め
っき層６が形成されている。The CSP 7 of the present embodiment has
As shown in FIG. 1, a solder plating layer 6 is formed on the terminal connection surface 1b of each lead 1a.
【００４２】この半田めっき層６は、ＣＳＰ７を半田実
装した際の半田接続強度を高めるためのものであり、モ
ールドによる樹脂封止を行った後に、リード１ａの端子
接続面１ｂとタブ１ｅとに半田めっき処理を行い、半田
めっき層６を形成するものである。The solder plating layer 6 is used to increase the solder connection strength when the CSP 7 is mounted by soldering. After the resin is sealed by molding, the solder plating layer 6 is formed between the terminal connection surface 1b of the lead 1a and the tab 1e. A solder plating process is performed to form a solder plating layer 6.
【００４３】なお、半田めっき層６の厚さは、例えば、
１０μｍ程度である。The thickness of the solder plating layer 6 is, for example,
It is about 10 μm.
【００４４】また、本実施の形態のＣＳＰ７の封止部３
は、フィルムシートを用いたモールドによって形成され
ることがあり、このようなモールドにおいては、ＣＳＰ
７のリード１ａの端子接続面１ｂが前記フィルムシート
にめり込んでモールドされる場合があり、その際、封止
後、リード１ａの端子接続面１ｂが封止部３の裏面３ａ
より僅かに（数μｍ〜数十μｍ程度）突出して形成され
る場合がある。Further, the sealing portion 3 of the CSP 7 of this embodiment
May be formed by a mold using a film sheet. In such a mold, the CSP
In some cases, the terminal connection surface 1b of the lead 1a of the No. 7 may be molded into the film sheet by digging into the film sheet.
In some cases, it is formed to project slightly (about several μm to several tens of μm).
【００４５】したがって、本実施の形態のＣＳＰ７で
は、各リード１ａの端子接続面１ｂが封止部３の裏面３
ａとほぼ同一面となって配置されているものの、半田め
っき層６の厚さ分やモールド時の前記フィルムシートへ
のめり込み分などによって、リード１ａの端子接続面１
ｂが封止部３の裏面３ａより僅かに（数μｍ〜数十μｍ
程度）突出して形成される場合もあり、このような構造
の場合であっても各リード１ａの端子接続面１ｂは、封
止部３の裏面３ａとほぼ同一面となって配置されている
ものとする。Therefore, in the CSP 7 of the present embodiment, the terminal connection surface 1b of each lead 1a is
Although the terminal connection surface 1a of the lead 1a is disposed on the same surface as that of the lead 1a due to the thickness of the solder plating layer 6 and the amount of embedding into the film sheet during molding.
b is slightly smaller than the back surface 3a of the sealing portion 3 (several μm to several tens μm).
In some cases, the terminal connection surface 1b of each lead 1a is disposed so as to be substantially flush with the back surface 3a of the sealing portion 3 even in such a structure. And
【００４６】なお、リード１ａに対しての半田めっき層
６の形成については、例えば、予め、リードフレーム１
の段階でこれの表面に外部装置（例えは、図６に示す実
装基板９や他の測定機器など）との接続を可能にする表
面処理、例えば、ＰｄやＰｄ−Ａｕなどの表面処理が行
われている場合には、樹脂封止後の半田めっき層６の形
成すなわち半田めっき処理は不要となる。For the formation of the solder plating layer 6 on the lead 1a, for example, the lead frame 1
At this stage, a surface treatment for enabling connection with an external device (for example, the mounting board 9 or other measuring instruments shown in FIG. 6), for example, a surface treatment such as Pd or Pd-Au is performed on the surface of the substrate. In this case, the formation of the solder plating layer 6 after resin sealing, that is, the solder plating process is not required.
【００４７】また、本実施の形態のＣＳＰ７には、封止
部３の裏面３ａに露出した各リード１ａの端子接続面１
ｂに細長い溝状の凹部１ｄが形成されている。The CSP 7 of the present embodiment has a terminal connection surface 1 of each lead 1a exposed on the back surface 3a of the sealing portion 3.
An elongated groove-shaped concave portion 1d is formed in b.
【００４８】つまり、図４（ａ),（ｂ）に示すように、
細長い端子接続面１ｂの長手方向に沿ってその中央付近
に細長い凹部１ｄが溝状に形成され、その深さは、例え
ば、リード１ａの板厚（例えば、リード１ａは、厚さ0.
１〜0.２ｍｍ程度）の１／２程度である。That is, as shown in FIGS. 4A and 4B,
An elongated concave portion 1d is formed in a groove shape near the center of the elongated terminal connection surface 1b along the longitudinal direction, and the depth thereof is, for example, the plate thickness of the lead 1a (for example, the lead 1a has a thickness of 0.1 mm).
(About 1 to 0.2 mm).
【００４９】なお、リード１ａの端子接続面１ｂの凹部
１ｄは、例えば、エッチングによって形成されるもので
ある。The recess 1d of the terminal connection surface 1b of the lead 1a is formed by, for example, etching.
【００５０】これにより、図６に示すように、ＣＳＰ７
において半田８を介して実装基板９などに実装を行った
際に、リード１ａの端子接続面１ｂの凹部１ｄに半田８
が埋め込まれるため、半田接続における半田接合部に配
置される半田量を増加でき、これにより、半田接続強度
を向上できる。As a result, as shown in FIG.
When mounting is performed on the mounting board 9 or the like via the solder 8 in the above, the solder 8 is inserted into the concave portion 1d of the terminal connection surface 1b of the lead 1a.
Is embedded, so that the amount of solder arranged at the solder joint portion in the solder connection can be increased, thereby improving the solder connection strength.
【００５１】なお、半導体チップ２は、タブ１ｅ上にボ
ンディング材５（例えば、導電性の熱硬化性あるいは熱
可塑性の接着剤など）によって固定されている。The semiconductor chip 2 is fixed on the tab 1e by a bonding material 5 (for example, a conductive thermosetting or thermoplastic adhesive).
【００５２】さらに、半導体チップ２のパッド２ａとこ
れに対応するリード１ａのボンディング面１ｃとを電気
的に接続するボンディングワイヤ４（接続部材）は、例
えば、金線やアルミニウム線などである。The bonding wire 4 (connection member) for electrically connecting the pad 2a of the semiconductor chip 2 and the bonding surface 1c of the corresponding lead 1a is, for example, a gold wire or an aluminum wire.
【００５３】また、封止部３は、モールド方法による樹
脂封止によって形成され、その際用いられる封止用の樹
脂は、例えば、熱硬化性のエポキシ樹脂などである。The sealing portion 3 is formed by resin sealing by a molding method, and the sealing resin used at this time is, for example, a thermosetting epoxy resin.
【００５４】なお、リード１ａやタブ１ｅは、例えば、
Ｃｕ、ＦｅまたはＦｅ−Ｎｉなどによって形成され、そ
の厚さは、例えば、0.１〜0.２ｍｍ程度の薄板材であ
る。The leads 1a and tabs 1e are, for example,
It is formed of Cu, Fe, Fe-Ni, or the like, and has a thickness of, for example, about 0.1 to 0.2 mm.
【００５５】次に、本実施の形態のＣＳＰ７の製造方法
を図５に示す製造プロセス図にしたがって説明する。Next, a method of manufacturing the CSP 7 according to the present embodiment will be described with reference to a manufacturing process diagram shown in FIG.
【００５６】なお、前記ＣＳＰ７の製造方法は、図１に
示すリードフレーム１を用いて行うものである。The method of manufacturing the CSP 7 is performed using the lead frame 1 shown in FIG.
【００５７】まず、半導体チップ２を樹脂封止して形成
される封止部３の裏面３ａ側の面内にこの面と同一面と
なって露出する端子接続面１ｂを備え、端子接続面１ｂ
に細長い溝状の凹部１ｄが予め形成された複数のリード
１ａを有する図１に示すリードフレーム１を準備する。First, a terminal connection surface 1b is provided in a surface on the back surface 3a side of the sealing portion 3 formed by resin-sealing the semiconductor chip 2 so as to be flush with this surface.
First, a lead frame 1 shown in FIG. 1 having a plurality of leads 1a in which elongated groove-shaped concave portions 1d are formed in advance is prepared.
【００５８】すなわち、予め、各リード１ａの端子接続
面１ｂに細長い溝状の凹部１ｄ（深さは、例えば、リー
ド１ａの板厚の１／２程度）が形成されたリードフレー
ム１を準備する。That is, the lead frame 1 is prepared in which the elongated groove-shaped recess 1d (depth is, for example, about half the plate thickness of the lead 1a) is formed in the terminal connection surface 1b of each lead 1a in advance. .
【００５９】なお、図１に示すリードフレーム１は、１
枚のリードフレーム１から複数個のＣＳＰ７を製造する
ことが可能な長尺状の細長い多連のものである。The lead frame 1 shown in FIG.
This is a long and narrow multiple unit capable of manufacturing a plurality of CSPs 7 from one lead frame 1.
【００６０】つまり、１枚のリードフレーム１には、１
個のＣＳＰ７に対応したパッケージ領域が複数個形成さ
れており、各リード１ａには、その端子接続面１ｂに凹
部１ｄが形成されている。That is, one lead frame 1 has 1
A plurality of package regions corresponding to the CSPs 7 are formed, and each lead 1a is formed with a concave portion 1d on its terminal connection surface 1b.
【００６１】一方、図５のステップＳ１に基づいて主面
２ｂに半導体集積回路が形成された半導体チップ２を準
備する。On the other hand, based on step S1 in FIG. 5, a semiconductor chip 2 having a semiconductor integrated circuit formed on the main surface 2b is prepared.
【００６２】続いて、ステップＳ２のように、リードフ
レーム１を供給し、その後、リードフレーム１のタブ１
ｅと半導体チップ２の裏面２ｃとを接合する。Subsequently, as in step S2, the lead frame 1 is supplied, and then the tab 1 of the lead frame 1 is supplied.
e and the back surface 2c of the semiconductor chip 2 are joined.
【００６３】すなわち、図３および図５のステップＳ３
に示すように、リードフレーム１のタブ１ｅにダイボン
ド材５を介して主面２ｂを上方に向けて半導体チップ２
を固定するチップマウント（ダイボンディングまたはペ
レットボンディングともいう）を行う。That is, step S3 in FIG. 3 and FIG.
As shown in FIG. 3, the semiconductor chip 2 has the main surface 2b facing upward on the tab 1e of the lead frame 1 via the die bonding material 5.
Is fixed (also referred to as die bonding or pellet bonding).
【００６４】その後、半導体チップ２のパッド２ａと、
これに対応するリード１ａのボンディング面１ｃとをワ
イヤボンディング（ステップＳ４）によって電気的に接
続する。Thereafter, the pad 2a of the semiconductor chip 2
The corresponding bonding surface 1c of the lead 1a is electrically connected by wire bonding (step S4).
【００６５】これにより、半導体チップ２のパッド２ａ
とリード１ａのボンディング面１ｃとがボンディングワ
イヤ４によって電気的に接続される。As a result, the pad 2a of the semiconductor chip 2
And the bonding surface 1c of the lead 1a are electrically connected by the bonding wire 4.
【００６６】その後、ステップＳ５に示すように、モー
ルドによる半導体チップ２の樹脂封止を行う。Thereafter, as shown in step S5, resin sealing of the semiconductor chip 2 by molding is performed.
【００６７】ここでは、半導体チップ２をモールドによ
って樹脂封止することにより、凹部１ｄが形成されたリ
ード１ａの端子接続面１ｂを封止部３の裏面３ａとほぼ
同一面となるように、樹脂封止して封止部３を形成す
る。Here, the semiconductor chip 2 is sealed with a resin by molding so that the terminal connection surface 1b of the lead 1a in which the recess 1d is formed is substantially flush with the back surface 3a of the sealing portion 3. The sealing part 3 is formed by sealing.
【００６８】これにより、各リード１ａは、封止部３の
裏面３ａ内に配置されるとともに、端子接続面１ｂが裏
面３ａとほぼ同一面となって配置される。As a result, each lead 1a is arranged in the back surface 3a of the sealing portion 3, and the terminal connection surface 1b is arranged so as to be substantially flush with the back surface 3a.
【００６９】したがって、封止部３の裏面３ａには、各
リード１ａがそれぞれの端子接続面１ｂを露出している
とともに、それぞれの端子接続面１ｂには図４に示すよ
うな細長い凹部１ｄが形成された構造になる。Accordingly, on the back surface 3a of the sealing portion 3, each lead 1a exposes its respective terminal connection surface 1b, and each terminal connection surface 1b has an elongated recess 1d as shown in FIG. It is a formed structure.
【００７０】なお、本実施の形態のＣＳＰ７では、図２
（ｂ）に示すように、タブ１ｅも封止部３の裏面３ａと
ほぼ同一面となって配置される。In the CSP 7 of the present embodiment, FIG.
As shown in (b), the tab 1e is also arranged substantially flush with the back surface 3a of the sealing portion 3.
【００７１】樹脂封止後、各リード１ａの端子接続面１
ｂとタブ１ｅとに図３に示すような半田めっき層６を形
成する。After resin sealing, the terminal connection surface 1 of each lead 1a
A solder plating layer 6 as shown in FIG. 3 is formed on b and the tab 1e.
【００７２】すなわち、ステップＳ６に示すように、各
リード１ａの端子接続面１ｂとタブ１ｅとに半田めっき
を行う。That is, as shown in step S6, the terminal connection surface 1b of each lead 1a and the tab 1e are plated with solder.
【００７３】その後、複数のリード１ａをリードフレー
ム１の枠部１ｆから切断によって切り離すリード切断
（ステップＳ７）を行って、リードフレーム１の枠部１
ｆから封止部３を含むリード１ａを分離して図２（ｂ）
に示す形状とする。Thereafter, lead cutting (step S7) for cutting the plurality of leads 1a from the frame 1f of the lead frame 1 by cutting is performed, and the frame 1 of the lead frame 1 is cut.
FIG. 2 (b) is a view of separating the lead 1a including the sealing portion 3 from FIG.
The shape is as shown in the figure.
【００７４】すなわち、図２または図３に示すＣＳＰ７
を完成させる（ステップＳ８）。That is, the CSP 7 shown in FIG.
Is completed (step S8).
【００７５】ここで、本実施の形態では、ＣＳＰ７の組
み立て後、その実装形態として図６に示すように、実装
基板９上に半田８を介してＣＳＰ７を実装した場合の構
造を説明する。Here, in the present embodiment, a description will be given of a structure in which the CSP 7 is mounted on a mounting substrate 9 via solder 8 as shown in FIG.
【００７６】つまり、図６に示すように、本実施の形態
のＣＳＰ７には、その各リード１ａの端子接続面１ｂに
凹部１ｄが形成されているため、半田実装を行った際
に、リード１ａの端子接続面１ｂの凹部１ｄに半田８が
埋め込まれ（半田８が流れ込み）、この状態でＣＳＰ７
のリード１ａと実装基板９の基板端子９ａとを半田８を
介して、かつ電気的に接続して実装することができる。That is, as shown in FIG. 6, in the CSP 7 of the present embodiment, the recess 1d is formed in the terminal connection surface 1b of each lead 1a. The solder 8 is embedded in the concave portion 1d of the terminal connection surface 1b (the solder 8 flows in), and in this state, the CSP 7
The lead 1a and the board terminal 9a of the mounting board 9 can be mounted via the solder 8 and electrically connected.
【００７７】本実施の形態のリードフレーム１およびそ
れを用いた半導体装置（ＣＳＰ７）ならびにその製造方
法によれば、以下のような作用効果が得られる。According to the lead frame 1 of the present embodiment, the semiconductor device (CSP 7) using the same, and the method of manufacturing the same, the following operational effects can be obtained.
【００７８】すなわち、ボトムリードタイプのＣＳＰ７
において、リード１ａの端子接続面１ｂに凹部１ｄが形
成されたことにより、実装基板９などへの半田実装時に
端子接続面１ｂの凹部１ｄによって半田接合部の半田接
合面積を増加させることができるとともに、凹部１ｄに
よって、前記半田接合部に配置される半田８の量を増や
すことができる。That is, the CSP 7 of the bottom lead type
Since the recess 1d is formed in the terminal connection surface 1b of the lead 1a, the solder connection area of the solder connection portion can be increased by the recess 1d of the terminal connection surface 1b during solder mounting on the mounting board 9 or the like. The amount of the solder 8 arranged at the solder joint can be increased by the concave portion 1d.
【００７９】これにより、ボトムリードタイプのＣＳＰ
７の実装時の半田付け強度を向上させることができる。Thus, the CSP of the bottom lead type
7, the soldering strength at the time of mounting can be improved.
【００８０】したがって、このＣＳＰ７の半田接続にお
ける接続信頼性を向上させることができ、その結果、こ
のＣＳＰ７を実装した電子機器などの信頼性の向上を図
ることができる。Therefore, the connection reliability in the solder connection of the CSP 7 can be improved, and as a result, the reliability of an electronic device having the CSP 7 mounted thereon can be improved.
【００８１】また、リード１ａの端子接続面１ｂに半田
めっき層６が形成されていることにより、ボトムリード
タイプのＣＳＰ７を実装した際のリード１ａと基板端子
９ａとの半田付け強度をさらに向上させることができ、
その結果、このＣＳＰ７の半田接続における接続信頼性
をさらに向上できる。Further, since the solder plating layer 6 is formed on the terminal connection surface 1b of the lead 1a, the soldering strength between the lead 1a and the substrate terminal 9a when the CSP 7 of the bottom lead type is mounted is further improved. It is possible,
As a result, the connection reliability of the CSP 7 in the solder connection can be further improved.
【００８２】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments of the invention, and does not depart from the gist of the invention. It goes without saying that various changes can be made.
【００８３】例えば、前記実施の形態では、ＣＳＰ７の
各リード１ａの端子接続面１ｂに細長い１つの凹部１ｄ
が形成されている場合を説明したが、凹部１ｄは、図７
（ａ）に示す変形例のように、１つのリード１ａの端子
接続面１ｂに分割された複数の小形の凹部１ｄが形成さ
れていてもよい。For example, in the above embodiment, one elongated recess 1d is formed in the terminal connection surface 1b of each lead 1a of the CSP 7.
Is described, but the concave portion 1d is formed as shown in FIG.
As in the modification shown in FIG. 7A, a plurality of small concave portions 1d divided on the terminal connection surface 1b of one lead 1a may be formed.
【００８４】これによれば、半田接合部の半田接合面積
をさらに増加させることができ、これにともなって、前
記半田接合部に配置される半田８（図６参照）の量をさ
らに増やすことができる。According to this, the solder joint area of the solder joint can be further increased, and accordingly, the amount of the solder 8 (see FIG. 6) disposed at the solder joint can be further increased. it can.
【００８５】その結果、ボトムリードタイプの小形の半
導体装置（ＣＳＰ７）の実装時の半田付け強度をさらに
向上させることができ、半田接続における接続信頼性を
さらに向上させることができる。As a result, the soldering strength at the time of mounting the small semiconductor device (CSP7) of the bottom lead type can be further improved, and the connection reliability in the solder connection can be further improved.
【００８６】なお、図７（ａ）に示す凹部１ｄの縦断面
の構造は、図７（ｂ）に示すように、図４（ｂ）に示す
ものと同じである。The structure of the longitudinal section of the recess 1d shown in FIG. 7A is the same as that shown in FIG. 4B, as shown in FIG. 7B.
【００８７】また、凹部１ｄの平面的な形状および縦断
面の形状については、前記実施の形態（図４）もしくは
その変形例（図７）に示したものに限定されることな
く、各リード１ａの端子接続面１ｂに凹状に形成されて
いればよい。The planar shape and vertical cross-sectional shape of the recess 1d are not limited to those shown in the embodiment (FIG. 4) or its modification (FIG. 7). The terminal connection surface 1b may be formed in a concave shape.
【００８８】また、前記実施の形態および前記変形例で
説明した凹部１ｄは、それぞれのリード１ａの端子接続
面１ｂにおいて、その端子接続面１ｂから外部に向かっ
て突出した凸部であってもよい。The concave portion 1d described in the embodiment and the modified example may be a convex portion protruding outward from the terminal connection surface 1b on the terminal connection surface 1b of each lead 1a. .
【００８９】これによっても、半田接合部の半田接合面
積を増加させることができるとともに、そこに配置され
る半田８の量を増やすことができ、その結果、ボトムリ
ードタイプの小形の半導体装置の実装時の半田付け強度
を向上できる。This also makes it possible to increase the solder bonding area of the solder bonding portion and increase the amount of the solder 8 disposed thereon, and as a result, the mounting of a small bottom lead type semiconductor device The soldering strength at the time can be improved.
【００９０】なお、各リード１ａの端子接続面１ｂにお
いて凹部１ｄと前記凸部とを組み合わせて形成してもよ
い。The concave portion 1d and the convex portion may be formed on the terminal connecting surface 1b of each lead 1a in combination.
【００９１】また、前記実施の形態においては、リード
フレーム１を準備する際に、予めリード１ａに凹部１ｄ
が形成されたリードフレーム１を準備する場合を説明し
たが、凹部１ｄが形成されていないリードフレーム１を
準備し、このリードフレーム１を搬入した後、半導体装
置（ＣＳＰ７）の製造工程に、リードフレーム１のリー
ド１ａの端子接続面１ｂに凹部１ｄまたは前記凸部を形
成する工程を含めてもよい。Further, in the above embodiment, when preparing the lead frame 1, the recess 1d is previously formed in the lead 1a.
The case of preparing the lead frame 1 on which the lead frame 1 is formed has been described. However, after preparing the lead frame 1 on which the concave portion 1d is not formed and carrying the lead frame 1, the lead frame 1 is formed in the manufacturing process of the semiconductor device (CSP7). A step of forming the concave portion 1d or the convex portion on the terminal connection surface 1b of the lead 1a of the frame 1 may be included.
【００９２】なお、前記実施の形態においては、半導体
装置が小形のＣＳＰ７の場合について説明したが、前記
半導体装置は、モールドによる樹脂封止形で、かつリー
ドフレーム１を用いて組み立てるボトムリードタイプの
小形のものであれば、ＣＳＰ７以外のもであってもよ
い。In the above embodiment, the case where the semiconductor device is a small-sized CSP 7 is described. However, the semiconductor device is a resin-sealed type by molding and a bottom lead type that is assembled using the lead frame 1. As long as it is small, it may be something other than CSP7.
【００９３】[0093]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.
【００９４】（１）．ボトムリードタイプの小形の半導
体装置においてリードの端子接続面に凹部または凸部が
形成されたことにより、半田接合部の半田接合面積を増
加させることができるとともに、半田接合部に配置され
る半田の量を増やすことができる。これにより、前記半
導体装置の実装時の半田付け強度を向上させることがで
き、その結果、前記半導体装置の半田接続における接続
信頼性を向上させることができる。(1). By forming a concave portion or a convex portion on a terminal connecting surface of a lead in a small semiconductor device of a bottom lead type, it is possible to increase a solder joint area of a solder joint portion, and to reduce a size of a solder arranged in the solder joint portion. The amount can be increased. Thereby, the soldering strength at the time of mounting the semiconductor device can be improved, and as a result, the connection reliability in the solder connection of the semiconductor device can be improved.
【００９５】（２）．前記（１）により、ボトムリード
タイプの小形の半導体装置を実装した電子機器などの信
頼性を向上できる。(2). According to the above (1), the reliability of an electronic device or the like on which a small semiconductor device of a bottom lead type is mounted can be improved.
【００９６】（３）．リードの端子接続面に半田めっき
層が形成されていることにより、ボトムリードタイプの
半導体装置を実装した際のリードと基板端子との半田付
け強度をさらに向上させることができる。(3). Since the solder plating layer is formed on the terminal connection surface of the lead, the soldering strength between the lead and the substrate terminal when the bottom lead type semiconductor device is mounted can be further improved.
【図１】本発明によるリードフレームの構造の実施の形
態の一例を示す部分平面図である。FIG. 1 is a partial plan view showing an example of an embodiment of the structure of a lead frame according to the present invention.
【図２】（ａ),（ｂ）は本発明の半導体装置の構造の実
施の形態の一例を示す図であり、（ａ）は平面図、
（ｂ）は底面図である。FIGS. 2A and 2B are diagrams showing an example of an embodiment of the structure of a semiconductor device according to the present invention, wherein FIG.
(B) is a bottom view.
【図３】図２に示す半導体装置の構造を示す断面図であ
る。FIG. 3 is a sectional view showing a structure of the semiconductor device shown in FIG. 2;
【図４】（ａ),（ｂ）は図２に示す半導体装置における
リードの端子接続面の凹部の構造を示す図であり、
（ａ）は図２（ｂ）におけるＡ部の詳細構造を示す拡大
図、（ｂ）は（ａ）のリードのＢ−Ｂ断面を示す断面図
である。4A and 4B are diagrams showing a structure of a concave portion of a terminal connecting surface of a lead in the semiconductor device shown in FIG. 2;
2A is an enlarged view showing a detailed structure of a portion A in FIG. 2B, and FIG. 2B is a cross-sectional view showing a BB cross section of the lead shown in FIG.
【図５】本発明による半導体装置の製造方法の実施の形
態の一例を示す製造プロセス図と各工程ごとの断面図で
ある。5A and 5B are a manufacturing process diagram showing an example of an embodiment of a method of manufacturing a semiconductor device according to the present invention, and a cross-sectional view showing each step.
【図６】図２に示す半導体装置の実装基板への実装状態
の構造の一例を示す部分断面図である。6 is a partial cross-sectional view illustrating an example of a structure of the semiconductor device illustrated in FIG. 2 in a state of being mounted on a mounting substrate.
【図７】（ａ),（ｂ）は図２に示す半導体装置における
リードの端子接続面の凹部の変形例の構造を示す図であ
り、（ａ）は図２（ｂ）におけるＡ部の変形例の詳細構
造を示す拡大図、（ｂ）は（ａ）のリードのＣ−Ｃ断面
を示す断面図である。7A and 7B are diagrams showing a structure of a modified example of a concave portion of a terminal connection surface of a lead in the semiconductor device shown in FIG. 2, and FIG. 7A is a diagram showing a portion A in FIG. FIG. 7B is an enlarged view showing a detailed structure of a modification, and FIG. 7B is a cross-sectional view showing a cross section taken along line CC of the lead shown in FIG.
１ リードフレーム １ａ リード １ｂ 端子接続面 １ｃ ボンディング面 １ｄ 凹部 １ｅ タブ（チップ支持部） １ｆ 枠部 １ｇ ガイド用長孔 １ｈ 位置決め孔 ２ 半導体チップ ２ａ パッド（表面電極） ２ｂ 主面 ２ｃ 裏面 ３ 封止部 ３ａ 裏面（半導体装置実装側の面） ４ ボンディングワイヤ（接続部材） ５ ダイボンド材 ６ 半田めっき層 ７ ＣＳＰ（半導体装置） ８ 半田 ９ 実装基板 ９ａ 基板端子 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Lead 1b Terminal connection surface 1c Bonding surface 1d Depression 1e Tab (chip support part) 1f Frame part 1g Guide long hole 1h Positioning hole 2 Semiconductor chip 2a Pad (surface electrode) 2b Main surface 2c Back surface 3 Sealing portion 3a Back surface (surface on the semiconductor device mounting side) 4 Bonding wire (connection member) 5 Die bond material 6 Solder plating layer 7 CSP (semiconductor device) 8 Solder 9 Mounting substrate 9a Board terminal
Claims (8)
ードフレームであって、 半導体チップを支持可能なチップ支持部と、 前記チップ支持部の周囲に配置され、前記半導体チップ
を樹脂封止して形成される封止部の半導体装置実装側の
面内にこの面と同一面となって露出する端子接続面を備
え、前記端子接続面に凹部または凸部が形成された複数
のリードとを有することを特徴とするリードフレーム。1. A lead frame used in a resin-sealed semiconductor device, comprising: a chip support portion capable of supporting a semiconductor chip; and a chip support portion disposed around the chip support portion, wherein the semiconductor chip is resin-sealed. A plurality of leads provided with a terminal connection surface which is exposed on the same surface as the surface of the sealing portion formed on the semiconductor device mounting side, and wherein the terminal connection surface is provided with a concave portion or a convex portion. A lead frame, comprising:
と、 前記チップ支持部の周囲に配置され、前記封止部の半導
体装置実装側の面内にこの面と同一面となって露出する
端子接続面を備え、前記端子接続面に凹部または凸部が
形成された複数のリードと、 前記半導体チップの表面電極とこれに対応する前記リー
ドとを電気的に接続する接続部材とを有することを特徴
とする半導体装置。2. A resin-sealed semiconductor device, comprising: a chip supporting portion for supporting a semiconductor chip; a sealing portion formed by resin-sealing the semiconductor chip; and a periphery of the chip supporting portion. A plurality of leads arranged and provided with a terminal connection surface exposed in the same plane as the surface in the semiconductor device mounting side of the sealing portion, and a concave portion or a convex portion is formed on the terminal connection surface, A semiconductor device, comprising: a connection member for electrically connecting a surface electrode of the semiconductor chip and the corresponding lead.
記リードの前記端子接続面に複数の前記凹部または前記
凸部が形成されていることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein a plurality of the concave portions or the convex portions are formed on the terminal connection surface of the lead.
って、前記リードの前記端子接続面に半田めっき層が形
成されていることを特徴とする半導体装置。4. The semiconductor device according to claim 2, wherein a solder plating layer is formed on the terminal connection surface of the lead.
って、 半導体チップを樹脂封止して形成される封止部の半導体
装置実装側の面内にこの面と同一面となって露出する端
子接続面を備え、前記端子接続面に凹部または凸部が形
成された複数のリードを有するリードフレームを準備す
る工程と、 前記リードフレームのチップ支持部と前記半導体チップ
とを接合する工程と、 前記半導体チップの表面電極とこれに対応する前記リー
ドフレームの前記リードとを電気的に接続する工程と、 前記半導体チップを樹脂封止して、前記凹部または前記
凸部が形成された前記リードの前記端子接続面を前記半
導体装置実装側の面内にこの面と同一面となって露出さ
せて前記封止部を形成する工程と、 複数の前記リードを前記リードフレームの枠部から分離
する工程とを有することを特徴とする半導体装置の製造
方法。5. A method for manufacturing a resin-encapsulated semiconductor device, wherein a surface of a sealing portion formed by resin-encapsulating a semiconductor chip on a semiconductor device mounting side is flush with the surface. A step of preparing a lead frame including a plurality of leads having an exposed terminal connection surface and having a concave portion or a convex portion formed in the terminal connection surface; and joining a chip support portion of the lead frame to the semiconductor chip. Electrically connecting a surface electrode of the semiconductor chip and the corresponding lead of the lead frame; and sealing the semiconductor chip with a resin to form the concave portion or the convex portion. Forming the sealing portion by exposing the terminal connection surface of the lead to the same surface as the surface in the surface on the semiconductor device mounting side; and forming the plurality of leads from the frame portion of the lead frame. The method of manufacturing a semiconductor device characterized by a step of releasing.
って、 半導体チップを樹脂封止して形成される封止部の半導体
装置実装側の面内にこの面と同一面となって露出する端
子接続面を備えた複数のリードを有するリードフレーム
を準備する工程と、 前記リードフレームの前記リードの前記端子接続面に凹
部または凸部を形成する工程と、 前記リードフレームのチップ支持部と前記半導体チップ
とを接合する工程と、 前記半導体チップの表面電極とこれに対応する前記リー
ドフレームの前記リードとを電気的に接続する工程と、 前記半導体チップを樹脂封止して、前記凹部または前記
凸部が形成された前記リードの前記端子接続面を前記半
導体装置実装側の面内にこの面と同一面となって露出さ
せて前記封止部を形成する工程と、 複数の前記リードを前記リードフレームの枠部から分離
する工程とを有することを特徴とする半導体装置の製造
方法。6. A method for manufacturing a resin-encapsulated semiconductor device, wherein a surface of a sealing portion formed by resin-sealing a semiconductor chip on a semiconductor device mounting side is flush with the surface. A step of preparing a lead frame having a plurality of leads having an exposed terminal connection surface; a step of forming a concave portion or a convex portion on the terminal connection surface of the lead of the lead frame; and a chip support portion of the lead frame. Bonding the semiconductor chip to the semiconductor chip; electrically connecting a surface electrode of the semiconductor chip to the corresponding lead of the lead frame; sealing the semiconductor chip with a resin to form the recess; Or forming the sealing portion by exposing the terminal connection surface of the lead on which the protrusion is formed to the same surface as the surface in the surface on the semiconductor device mounting side; Separating the lead from the frame of the lead frame.
って、 半導体チップを樹脂封止して形成される封止部の半導体
装置実装側の面内にこの面と同一面となって露出する端
子接続面を備え、前記端子接続面に凹部が形成された複
数のリードを有するリードフレームを準備する工程と、 前記リードフレームのチップ支持部と前記半導体チップ
とを接合する工程と、 前記半導体チップの表面電極とこれに対応する前記リー
ドフレームの前記リードとを電気的に接続する工程と、 前記半導体チップを樹脂封止して、前記凹部が形成され
た前記リードの前記端子接続面を前記半導体装置実装側
の面内にこの面と同一面となって露出させて前記封止部
を形成する工程と、 複数の前記リードを前記リードフレームの枠部から分離
して前記半導体装置を組み立てる工程と、 前記半導体装置組み立て後、前記半導体装置の前記リー
ドの前記端子接続面の前記凹部に半田を埋め込んで前記
半導体装置の前記リードと実装基板の基板端子とを前記
半田を介して電気的に接続して前記実装基板に前記半導
体装置を実装する工程とを有することを特徴とする半導
体装置の製造方法。7. A method of manufacturing a resin-encapsulated semiconductor device, wherein a surface of a sealing portion formed by resin-sealing a semiconductor chip on a semiconductor device mounting side is flush with the surface. A step of preparing a lead frame having a plurality of leads having a terminal connection surface that is exposed and having a recess formed in the terminal connection surface; a step of bonding a chip support portion of the lead frame to the semiconductor chip; Electrically connecting the surface electrode of the semiconductor chip and the corresponding lead of the lead frame; and sealing the semiconductor chip with a resin to form the terminal connection surface of the lead having the recess formed therein. Forming the sealing portion by exposing the same surface as the same surface in the surface on the semiconductor device mounting side, and separating the plurality of leads from a frame portion of the lead frame to form the semiconductor device. And erecting the semiconductor device, after assembling the semiconductor device, burying solder in the concave portion of the terminal connection surface of the lead of the semiconductor device, and electrically connecting the lead of the semiconductor device and a substrate terminal of a mounting board via the solder. Mounting the semiconductor device on the mounting substrate by connecting the semiconductor device to the mounting substrate.
の製造方法であって、前記樹脂封止後、前記リードの前
記端子接続面に半田めっき層を形成することを特徴とす
る半導体装置の製造方法。8. The method for manufacturing a semiconductor device according to claim 5, wherein after the resin sealing, a solder plating layer is formed on the terminal connection surface of the lead. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10263299A JP2000294719A (en) | 1999-04-09 | 1999-04-09 | Lead frame, semiconductor device using the same, and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10263299A JP2000294719A (en) | 1999-04-09 | 1999-04-09 | Lead frame, semiconductor device using the same, and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000294719A true JP2000294719A (en) | 2000-10-20 |
Family
ID=14332626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10263299A Pending JP2000294719A (en) | 1999-04-09 | 1999-04-09 | Lead frame, semiconductor device using the same, and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000294719A (en) |
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004207275A (en) * | 2002-12-20 | 2004-07-22 | Sanyo Electric Co Ltd | Circuit device and its manufacturing method |
| JP2005079372A (en) * | 2003-09-01 | 2005-03-24 | Nec Electronics Corp | Resin-sealed semiconductor device and its manufacturing method |
| JP2005191240A (en) * | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | Semiconductor device and method for manufacturing the same |
| JP2005191574A (en) * | 2003-12-24 | 2005-07-14 | Stmicroelectronics Inc | System and method of improving solder joining reliability in integrated circuit package |
| JP2005311137A (en) * | 2004-04-22 | 2005-11-04 | Sony Corp | Semiconductor device, manufacturing method thereof, and lead frame thereof and mounting structure |
| US7023074B2 (en) * | 2002-12-10 | 2006-04-04 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
| JP2006140258A (en) * | 2004-11-11 | 2006-06-01 | Shindengen Electric Mfg Co Ltd | Resin-sealing semiconductor device |
| JP2006179760A (en) * | 2004-12-24 | 2006-07-06 | Yamaha Corp | Semiconductor package and lead frame used therefor |
| WO2006109566A1 (en) * | 2005-04-08 | 2006-10-19 | Rohm Co., Ltd. | Semiconductor device |
| JP2006332472A (en) * | 2005-05-30 | 2006-12-07 | Mitsui Chemicals Inc | Semiconductor element mounting hollow package |
| JP2008186891A (en) * | 2007-01-29 | 2008-08-14 | Denso Corp | Mold package and its manufacturing method, and mounting structure of the mold package |
| WO2008105437A1 (en) * | 2007-02-27 | 2008-09-04 | Rohm Co., Ltd. | Semiconductor device, leadframe and semiconductor device manufacturing method |
| JP2008300717A (en) * | 2007-06-01 | 2008-12-11 | Denso Corp | Mold package |
| JP2009124095A (en) * | 2007-11-12 | 2009-06-04 | Samsung Sdi Co Ltd | Semiconductor package and mounting method thereof |
| JP2011114136A (en) * | 2009-11-26 | 2011-06-09 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2011169717A (en) * | 2010-02-18 | 2011-09-01 | Hokuriku Electric Ind Co Ltd | Force detector |
| WO2011123220A2 (en) * | 2010-04-01 | 2011-10-06 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
| JP2012089669A (en) * | 2010-10-19 | 2012-05-10 | Dainippon Printing Co Ltd | Semiconductor device and manufacturing method thereof |
| KR101216509B1 (en) | 2010-08-03 | 2012-12-31 | 리니어 테크놀러지 코포레이션 | Laser process for side plating of terminals |
| JP2013062527A (en) * | 2006-10-04 | 2013-04-04 | Rohm Co Ltd | Semiconductor device |
| US8685795B2 (en) | 2011-05-18 | 2014-04-01 | Freescale Semiconductor, Inc. | Flank wettable semiconductor device |
| CN104685615A (en) * | 2014-03-27 | 2015-06-03 | 瑞萨电子株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| JP2015195389A (en) * | 2015-06-17 | 2015-11-05 | 大日本印刷株式会社 | Semiconductor device and manufacturing method thereof |
| JP2016040834A (en) * | 2000-12-28 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | Electronic device manufacturing method |
| CN105720033A (en) * | 2014-12-22 | 2016-06-29 | 意法半导体公司 | Leadframe package with pre-applied filler material |
| JP5946943B1 (en) * | 2015-07-10 | 2016-07-06 | アルス株式会社 | Semiconductor package |
| US9543247B1 (en) | 2015-08-31 | 2017-01-10 | Stmicroelectronics (Tours) Sas | Surface-mount electronic component |
| US11309237B2 (en) | 2019-09-27 | 2022-04-19 | Stmicroelectronics S.R.L. | Semiconductor package with wettable slot structures |
-
1999
- 1999-04-09 JP JP10263299A patent/JP2000294719A/en active Pending
Cited By (45)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016040834A (en) * | 2000-12-28 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | Electronic device manufacturing method |
| US7023074B2 (en) * | 2002-12-10 | 2006-04-04 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
| JP2004207275A (en) * | 2002-12-20 | 2004-07-22 | Sanyo Electric Co Ltd | Circuit device and its manufacturing method |
| US7166919B2 (en) | 2003-09-01 | 2007-01-23 | Nec Electronics Corporation | Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package |
| JP2005079372A (en) * | 2003-09-01 | 2005-03-24 | Nec Electronics Corp | Resin-sealed semiconductor device and its manufacturing method |
| JP2005191574A (en) * | 2003-12-24 | 2005-07-14 | Stmicroelectronics Inc | System and method of improving solder joining reliability in integrated circuit package |
| JP4547252B2 (en) * | 2003-12-24 | 2010-09-22 | エスティーマイクロエレクトロニクス，インコーポレイテッド | System and method for improving solder joint reliability in integrated circuit packages |
| JP2005191240A (en) * | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | Semiconductor device and method for manufacturing the same |
| JP2005311137A (en) * | 2004-04-22 | 2005-11-04 | Sony Corp | Semiconductor device, manufacturing method thereof, and lead frame thereof and mounting structure |
| JP4635471B2 (en) * | 2004-04-22 | 2011-02-23 | ソニー株式会社 | Semiconductor device and manufacturing method thereof, mounting structure of semiconductor device, and lead frame |
| JP2006140258A (en) * | 2004-11-11 | 2006-06-01 | Shindengen Electric Mfg Co Ltd | Resin-sealing semiconductor device |
| JP2006179760A (en) * | 2004-12-24 | 2006-07-06 | Yamaha Corp | Semiconductor package and lead frame used therefor |
| TWI382499B (en) * | 2005-04-08 | 2013-01-11 | Rohm Co Ltd | Semiconductor device |
| JP2006294809A (en) * | 2005-04-08 | 2006-10-26 | Rohm Co Ltd | Semiconductor device |
| WO2006109566A1 (en) * | 2005-04-08 | 2006-10-19 | Rohm Co., Ltd. | Semiconductor device |
| JP2006332472A (en) * | 2005-05-30 | 2006-12-07 | Mitsui Chemicals Inc | Semiconductor element mounting hollow package |
| JP2013062527A (en) * | 2006-10-04 | 2013-04-04 | Rohm Co Ltd | Semiconductor device |
| JP2008186891A (en) * | 2007-01-29 | 2008-08-14 | Denso Corp | Mold package and its manufacturing method, and mounting structure of the mold package |
| WO2008105437A1 (en) * | 2007-02-27 | 2008-09-04 | Rohm Co., Ltd. | Semiconductor device, leadframe and semiconductor device manufacturing method |
| JP2008211041A (en) * | 2007-02-27 | 2008-09-11 | Rohm Co Ltd | Semiconductor device, lead frame, and method for manufacturing semiconductor device |
| TWI421998B (en) * | 2007-02-27 | 2014-01-01 | Rohm Co Ltd | Semiconductor device, lead frame and semiconductor device manufacturing method |
| US8115299B2 (en) | 2007-02-27 | 2012-02-14 | Rohm Co., Ltd. | Semiconductor device, lead frame and method of manufacturing semiconductor device |
| JP2008300717A (en) * | 2007-06-01 | 2008-12-11 | Denso Corp | Mold package |
| US8319319B2 (en) | 2007-11-12 | 2012-11-27 | Samsung Sdi Co., Ltd. | Semiconductor package and mounting method thereof |
| JP2009124095A (en) * | 2007-11-12 | 2009-06-04 | Samsung Sdi Co Ltd | Semiconductor package and mounting method thereof |
| JP2011114136A (en) * | 2009-11-26 | 2011-06-09 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2011169717A (en) * | 2010-02-18 | 2011-09-01 | Hokuriku Electric Ind Co Ltd | Force detector |
| WO2011123220A3 (en) * | 2010-04-01 | 2012-01-05 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
| US8329509B2 (en) | 2010-04-01 | 2012-12-11 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
| WO2011123220A2 (en) * | 2010-04-01 | 2011-10-06 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
| KR101216509B1 (en) | 2010-08-03 | 2012-12-31 | 리니어 테크놀러지 코포레이션 | Laser process for side plating of terminals |
| JP2012089669A (en) * | 2010-10-19 | 2012-05-10 | Dainippon Printing Co Ltd | Semiconductor device and manufacturing method thereof |
| US8685795B2 (en) | 2011-05-18 | 2014-04-01 | Freescale Semiconductor, Inc. | Flank wettable semiconductor device |
| KR20160136208A (en) | 2014-03-27 | 2016-11-29 | 르네사스 일렉트로닉스 가부시키가이샤 | Method for manufacturing semiconductor device and semiconductor device |
| CN104685615A (en) * | 2014-03-27 | 2015-06-03 | 瑞萨电子株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| WO2015145651A1 (en) | 2014-03-27 | 2015-10-01 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN104685615B (en) * | 2014-03-27 | 2018-12-21 | 瑞萨电子株式会社 | The manufacturing method and semiconductor devices of semiconductor devices |
| US9601415B2 (en) | 2014-03-27 | 2017-03-21 | Renesas Electronics Corporation | Method of manufacturing semiconductor device and semiconductor device |
| CN105720033A (en) * | 2014-12-22 | 2016-06-29 | 意法半导体公司 | Leadframe package with pre-applied filler material |
| US9578744B2 (en) | 2014-12-22 | 2017-02-21 | Stmicroelectronics, Inc. | Leadframe package with pre-applied filler material |
| US11227776B2 (en) | 2014-12-22 | 2022-01-18 | Stmicroelectronics, Inc. | Leadframe package with pre-applied filler material |
| JP2015195389A (en) * | 2015-06-17 | 2015-11-05 | 大日本印刷株式会社 | Semiconductor device and manufacturing method thereof |
| JP5946943B1 (en) * | 2015-07-10 | 2016-07-06 | アルス株式会社 | Semiconductor package |
| US9543247B1 (en) | 2015-08-31 | 2017-01-10 | Stmicroelectronics (Tours) Sas | Surface-mount electronic component |
| US11309237B2 (en) | 2019-09-27 | 2022-04-19 | Stmicroelectronics S.R.L. | Semiconductor package with wettable slot structures |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000294719A (en) | Lead frame, semiconductor device using the same, and manufacture thereof | |
| JP3780122B2 (en) | Manufacturing method of semiconductor device | |
| JP3526788B2 (en) | Method for manufacturing semiconductor device | |
| JP3691993B2 (en) | Semiconductor device and manufacturing method thereof, carrier substrate and manufacturing method thereof | |
| JP3947750B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JP4091050B2 (en) | Manufacturing method of semiconductor device | |
| WO2004004005A1 (en) | Semiconductor device and its manufacturing method | |
| JPH11312706A (en) | Resin encapsulating semiconductor device and its manufacture, and lead frame | |
| KR20030007040A (en) | A semiconductor device and method of manufacturing the same | |
| JP2005317998A5 (en) | ||
| JP2003017518A (en) | Method for manufacturing hybrid integrated circuit device | |
| JP2000299423A (en) | Lead frame, semiconductor device using the same and manufacture thereof | |
| JP5378643B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2007157846A (en) | Method of manufacturing semiconductor device | |
| JP2001177005A (en) | Semiconductor device and manufacturing method thereof | |
| JPH10256460A (en) | Terminal land frame, resin sealed type semiconductor device using it, and manufacture of the device | |
| JP2956659B2 (en) | Semiconductor device and its lead frame | |
| JPH11260989A (en) | Resin-sealed semiconductor device and its manufacture | |
| JP4137981B2 (en) | Manufacturing method of semiconductor device | |
| JP2001135767A (en) | Semiconductor device and method of manufacturing the same | |
| JP2954108B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0888295A (en) | Semiconductor device | |
| JP2001267484A (en) | Semiconductor device and manufacturing method thereof | |
| JPH07122701A (en) | Semiconductor device, its manufacture, and lead frame for pga | |
| JP4021115B2 (en) | Resin-sealed semiconductor device and manufacturing method thereof |