JP2011114136A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
JP2011114136A
JP2011114136A JP2009268764A JP2009268764A JP2011114136A JP 2011114136 A JP2011114136 A JP 2011114136A JP 2009268764 A JP2009268764 A JP 2009268764A JP 2009268764 A JP2009268764 A JP 2009268764A JP 2011114136 A JP2011114136 A JP 2011114136A
Authority
JP
Japan
Prior art keywords
lead
groove
resin
island
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009268764A
Other languages
Japanese (ja)
Inventor
Kiyoshi Mita
清志 三田
Isao Nakatsuka
功 中塚
Yuji Umetani
祐二 梅谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
System Solutions Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2009268764A priority Critical patent/JP2011114136A/en
Publication of JP2011114136A publication Critical patent/JP2011114136A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To solve such the problem that mounting strength in leads can not be easily improved in the conventional semiconductor device since a package is more microfabricated. <P>SOLUTION: A semiconductor device has parts of leads 4 exposed from the rear surface 5 of a resin package 2 and also has grooves 8 arranged in the leads 4. Each of the grooves 8 is arranged in a region inside the outer peripheral end of a lead 4, and a flat surface 9 is arranged at the periphery of the groove 8. In this structure, the inner side surface of the groove 8 is used as a mounting region for the lead 4 to improve mounting strength of the lead 4. Further, infiltration of a resin is restricted by the flat surface 9 of the lead 4 to greatly reduce formation of resin burrs. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、実装時のリードの実装強度を向上させる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device that improves the mounting strength of a lead during mounting and a method for manufacturing the same.

従来の半導体装置として、下記の構造が知られている。   The following structure is known as a conventional semiconductor device.

図８（Ａ）に示す如く、半導体装置５１は、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）型の樹脂パッケージ５２から成る。そして、アイランド５３上面にはヒートシンク５４が固着され、ヒートシンク５４上面に接着材５５により半導体素子５６が固着される。半導体素子５６の電極パッド（図示せず）とリード５７とは、金属細線５８により電気的に接続される。   As shown in FIG. 8A, the semiconductor device 51 includes a QFN (Quad Flat Package) type resin package 52. A heat sink 54 is fixed to the upper surface of the island 53, and a semiconductor element 56 is fixed to the upper surface of the heat sink 54 with an adhesive 55. An electrode pad (not shown) of the semiconductor element 56 and the lead 57 are electrically connected by a thin metal wire 58.

図８（Ｂ）に示す如く、樹脂パッケージ５２の裏面５９からは、アイランド５３やリード５７が露出し、アイランド５３やリード５７の露出面は、樹脂パッケージ５２の裏面５９と、実質、同一面を形成する。そして、露出するアイランド５３やリード５７は、実装領域として用いられる（例えば、特許文献１参照。）。   As shown in FIG. 8B, the island 53 and the lead 57 are exposed from the back surface 59 of the resin package 52, and the exposed surface of the island 53 and the lead 57 is substantially the same surface as the back surface 59 of the resin package 52. Form. The exposed islands 53 and leads 57 are used as a mounting area (see, for example, Patent Document 1).

特開２００６−１４７９１８号公報（第７−９頁、第１図）JP 2006-147918 A (pages 7-9, FIG. 1)

ＱＦＮ型の樹脂パッケージ５２では、一般的には、樹脂モールド時にリードフレームの裏面側にモールド用のシートを貼り合わせることで、リード５７の実装面６０側への樹脂ばりの発生を抑止する。   In the QFN type resin package 52, generally, a resin sheet on the mounting surface 60 side of the lead 57 is suppressed by attaching a molding sheet to the back side of the lead frame during resin molding.

しかしながら、モールド用のシートを用いた場合でも、リード５７とシートとの接着状況等により、リード５７の実装面６０側に樹脂ばり６１が発生する。そして、樹脂ばり６１の発生量に応じて実装領域が低減し、実装強度が低下し、半導体装置５１が導電パターンから剥離し、実装不良となる問題がある。この問題を解決するためには、ウォータージェット等により樹脂ばり６１の除去工程が必要となり、製造コストが余分に掛かるという問題もある。   However, even when a molding sheet is used, a resin flash 61 is generated on the mounting surface 60 side of the lead 57 depending on the adhesion state between the lead 57 and the sheet. Then, there is a problem that the mounting area is reduced according to the amount of the resin flash 61 generated, the mounting strength is reduced, and the semiconductor device 51 is peeled from the conductive pattern, resulting in a mounting failure. In order to solve this problem, a step of removing the resin beam 61 is required by a water jet or the like, and there is a problem that the manufacturing cost is excessive.

また、昨今の半導体装置５１の微細化の流れにより、樹脂パッケージ５２から露出するリード５７の実装面６０自体が狭くなり、前述したウォータージェット等によっても樹脂ばり６１を除去し難いという問題もある。そして、その除去工程にて、樹脂ばり６１だけでなく、リード５７周囲の樹脂まで除去された場合には、リード５７が樹脂パッケージ５２から抜け落ちる等の新たな問題も発生し、作業の簡略化が図り難いという問題がある。更に言うと、前述した微細化の流れにより、リード５７の実装面６０自体が狭くなり、リード５７の実装領域を増大させ、実装強度を向上させたいという願望がある。   Further, due to the recent trend of miniaturization of the semiconductor device 51, the mounting surface 60 itself of the lead 57 exposed from the resin package 52 becomes narrow, and there is a problem that it is difficult to remove the resin beam 61 by the above-described water jet or the like. If not only the resin beam 61 but also the resin around the lead 57 is removed in the removal process, a new problem such as the lead 57 falling off from the resin package 52 occurs, and the work is simplified. There is a problem that it is difficult to plan. Furthermore, there is a desire to increase the mounting strength of the leads 57 by increasing the mounting surface 60 of the leads 57 due to the above-described miniaturization flow, thereby increasing the mounting area of the leads 57.

また、図示したように、アイランド５３の実装面６２にも樹脂ばり６３が発生し、前述したリード５７と同様な実装強度が低下する問題がある。更に、アイランド５３を実装領域として用いる場合には、アイランド５３の実装面６２は、リード５７の実装面６０と比較して面積が大きく、実装用の接着材内にボイドが発生し易いという問題がある。   Further, as shown in the figure, the resin flash 63 is generated on the mounting surface 62 of the island 53, and there is a problem that the mounting strength similar to that of the lead 57 described above is lowered. Further, when the island 53 is used as a mounting region, the mounting surface 62 of the island 53 has a larger area than the mounting surface 60 of the lead 57, and there is a problem that voids are likely to occur in the mounting adhesive. is there.

前述した各事情に鑑みて成されたものであり、本発明の半導体装置では、アイランドと、前記アイランドの周囲に配置されたリードと、前記アイランド上に接着材を介して固着された半導体素子と、前記半導体素子と前記リードとを電気的に接続する金属細線と、前記アイランド、前記リード、前記金属細線及び前記半導体素子を被覆する樹脂パッケージとを有する半導体装置において、前記リードの一部は、前記樹脂パッケージの実装面から露出し、前記リードには、前記リードの外周端部よりも内側に前記露出面側から溝が配置され、前記溝と前記外周端部との間には前記リードの平坦面が配置されることを特徴とする。   In view of the circumstances described above, the semiconductor device according to the present invention includes an island, a lead disposed around the island, and a semiconductor element fixed on the island via an adhesive. In the semiconductor device having a thin metal wire that electrically connects the semiconductor element and the lead, and a resin package that covers the island, the lead, the fine metal wire, and the semiconductor element, a part of the lead is The lead is exposed from the mounting surface of the resin package, and the lead is provided with a groove from the exposed surface inside the outer peripheral end of the lead, and the lead is disposed between the groove and the outer peripheral end. A flat surface is arranged.

また、本発明の半導体装置の製造方法では、アイランドと、前記アイランドの周囲に配置された複数のリードとを有する搭載部が設けられたリードフレームを準備し、前記アイランドの一主面上に半導体素子を固着し、前記半導体素子の電極パッドと前記リードの一主面とを金属細線によりワイヤーボンディングし、前記搭載部を樹脂で被覆し、少なくとも前記リードフレームの一主面側を被覆するように樹脂パッケージを形成する半導体装置の製造方法において、前記リードの他の主面側に前記リードの外周端部から連続した平坦面の内側に溝を形成した後、前記リードフレームの他の主面にシートを貼り合わせ、前記溝が前記シートにより塞がれた状態にて前記樹脂パッケージを形成する樹脂モールド工程を行うことを特徴とする。   In the method for manufacturing a semiconductor device according to the present invention, a lead frame provided with a mounting portion having an island and a plurality of leads arranged around the island is prepared, and a semiconductor is formed on one main surface of the island. The element is fixed, the electrode pad of the semiconductor element and one main surface of the lead are wire-bonded with a thin metal wire, the mounting portion is covered with resin, and at least one main surface side of the lead frame is covered In the method of manufacturing a semiconductor device for forming a resin package, after forming a groove on the other main surface side of the lead on the inner side of a flat surface continuous from the outer peripheral end of the lead, the other main surface of the lead frame is formed. A resin molding step is performed in which the sheet is bonded and the resin package is formed in a state where the groove is closed by the sheet.

本発明では、樹脂パッケージから露出するリードに溝が形成され、溝の内側面が実装領域として用いられ、リードの実装強度が向上される。   In the present invention, a groove is formed in the lead exposed from the resin package, and the inner side surface of the groove is used as a mounting region, thereby improving the mounting strength of the lead.

また、本発明では、リードの露出面側の溝の周囲に平坦面が配置されることで、リードの実装面への樹脂ばりの発生が大幅に低減される。   Further, in the present invention, since the flat surface is disposed around the groove on the exposed surface side of the lead, the occurrence of resin flash on the mounting surface of the lead is greatly reduced.

また、本発明では、樹脂パッケージの側面からリードの溝を露出させることで、実装用の接着材内に偏ったボイドの発生が抑止される。   Further, in the present invention, by exposing the groove of the lead from the side surface of the resin package, occurrence of a biased void in the mounting adhesive is suppressed.

また、本発明では、アイランドの露出面に溝が配置されることで、溝よりも内側のアイランドの露出面への樹脂ばりの発生が抑止される。   Moreover, in this invention, generation | occurrence | production of the resin flash to the exposed surface of an island inside a groove | channel is suppressed by arrange | positioning a groove | channel on the exposed surface of an island.

また、本発明では、溝よりも内側のアイランドの露出面にボイド拡散用の溝が形成されることで、実装強度が向上される。   Further, according to the present invention, the mounting strength is improved by forming the void diffusion groove on the exposed surface of the island inside the groove.

また、本発明では、リードの露出面に溝を形成した後に樹脂モールド工程を行うことで、リードの露出面側への樹脂ばりの発生を抑止できる。   Moreover, in this invention, generation | occurrence | production of the resin flash to the exposed surface side of a lead can be suppressed by performing a resin molding process after forming a groove | channel in the exposed surface of a lead.

本発明の実施の形態における半導体装置を説明するための（Ａ）斜視図、（Ｂ）平面図、（Ｃ）断面図である。1A is a perspective view, FIG. 1B is a plan view, and FIG. 1C is a cross-sectional view for explaining a semiconductor device according to an embodiment of the present invention. 本発明の実施の形態における半導体装置を説明するための（Ａ）断面図、（Ｂ）断面図、（Ｃ）断面図である。1A is a cross-sectional view, FIG. 1B is a cross-sectional view, and FIG. 1C is a cross-sectional view for explaining a semiconductor device in an embodiment of the present invention; 本発明の実施の形態における半導体装置を説明するための（Ａ）平面図、（Ｂ）平面図、（Ｃ）平面図である。BRIEF DESCRIPTION OF THE DRAWINGS (A) Top view, (B) Top view, (C) Top view for demonstrating the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の製造方法を説明するための平面図である。It is a top view for demonstrating the manufacturing method of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の製造方法を説明するための（Ａ）平面図、（Ｂ）平面図である。It is (A) top view and (B) top view for demonstrating the manufacturing method of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の製造方法を説明するための（Ａ）断面図、（Ｂ）断面図、（Ｃ）断面図である。1A is a cross-sectional view for explaining a method of manufacturing a semiconductor device in an embodiment of the present invention, FIG. 2B is a cross-sectional view, and FIG. 本発明の実施の形態における半導体装置の製造方法を説明するための（Ａ）平面図、（Ｂ）断面図である。It is (A) top view and (B) sectional drawing for demonstrating the manufacturing method of the semiconductor device in embodiment of this invention. 従来の実施の形態における半導体装置を説明するための（Ａ）断面図、（Ｂ）平面図である。It is (A) sectional drawing and (B) top view for demonstrating the semiconductor device in conventional embodiment.

以下に、本発明の一実施の形態である半導体装置について説明する。図１（Ａ）は、半導体装置を説明する斜視図である。図１（Ｂ）は、図１（Ａ）半導体装置の裏面側を説明する平面図である。図１（Ｃ）は、図１（Ａ）に示す半導体装置のＡ−Ａ線方向の断面図である。図２（Ａ）及び図２（Ｃ）は、リードの溝を説明する断面図であり、図２（Ｂ）は、リードの溝を説明する平面図である。   A semiconductor device according to an embodiment of the present invention will be described below. FIG. 1A is a perspective view illustrating a semiconductor device. FIG. 1B is a plan view illustrating the back side of the semiconductor device in FIG. FIG. 1C is a cross-sectional view of the semiconductor device illustrated in FIG. 2A and 2C are cross-sectional views for explaining the lead grooves, and FIG. 2B is a plan view for explaining the lead grooves.

先ず、図１（Ａ）に示す如く、半導体装置１は、例えば、ＭＡＰ（Ｍａｔｒｉｘ Ａｒｒａｙ Ｐａｃｋａｇｉｎｇ ｍｅｔｏｄ）型の樹脂パッケージ２から成る。詳細は製造方法の説明にて後述するが、リードフレームの複数の搭載部を一括して封止した後、ダイシングにより個片化するため、樹脂パッケージ２の側面３からリード４が露出する。そして、露出するリード４は、樹脂パッケージ２の側面３とほぼ同一面を形成する。   First, as shown in FIG. 1A, the semiconductor device 1 is composed of, for example, a MAP (Matrix Array Packaging Method) type resin package 2. Although details will be described later in the description of the manufacturing method, the leads 4 are exposed from the side surface 3 of the resin package 2 because the plurality of mounting portions of the lead frame are collectively sealed and then separated into pieces by dicing. The exposed lead 4 forms substantially the same surface as the side surface 3 of the resin package 2.

次に、図１（Ｂ）に示す如く、樹脂パッケージ２の裏面５にはアイランド６が露出し、アイランド６の露出面は、樹脂パッケージ２の裏面５とほぼ同一面を形成する。また、樹脂パッケージ２の裏面５にはリード４が露出し、アイランド６を囲むように配置される。そして、丸印７にて示すように、アイランド６のコーナー部の一部を切り欠くことで、アイランド６の露出形状が位置認識マークとして利用される。   Next, as shown in FIG. 1B, the island 6 is exposed on the back surface 5 of the resin package 2, and the exposed surface of the island 6 forms substantially the same surface as the back surface 5 of the resin package 2. Further, the lead 4 is exposed on the back surface 5 of the resin package 2 and is disposed so as to surround the island 6. Then, as shown by a circle 7, the exposed shape of the island 6 is used as a position recognition mark by cutting out a part of the corner portion of the island 6.

また、図示したように、溝８がリード４に形成され、リード４の中央領域が露出面側から窪んだ領域となる。溝８は樹脂パッケージ２の側面３まで配置され、溝８の内側面は実装領域となり、リード４での実装強度が向上される。そして、リード４の露出面では、溝８の周囲に平坦面９が配置される。平坦面９は、例えば、幅Ｗ１の領域と幅Ｗ２の領域から構成される。尚、平坦面９の幅Ｗ１、Ｗ２は同一の場合でも良く、任意の設計変更が可能である。   Further, as shown in the drawing, the groove 8 is formed in the lead 4, and the central region of the lead 4 becomes a region recessed from the exposed surface side. The groove 8 is arranged up to the side surface 3 of the resin package 2, and the inner side surface of the groove 8 becomes a mounting region, and the mounting strength at the lead 4 is improved. A flat surface 9 is disposed around the groove 8 on the exposed surface of the lead 4. The flat surface 9 is composed of, for example, a region having a width W1 and a region having a width W2. The widths W1 and W2 of the flat surface 9 may be the same, and arbitrary design changes are possible.

次に、図１（Ｃ）に示す如く、アイランド６上には、例えば、Ａｇペースト、半田等の接着材１０により半導体素子１１が固着される。半導体素子１１上面には複数の電極パッド３７（図５（Ｂ）参照）が形成され、電極パッド３７とリード４とは金属細線１２により接続される。金属細線１２としては、金線や銅線が用いられる。図示したように、金属細線１２は、溝８の形成領域上に接続されるが、溝８の深さＴ１が調整され、ワイヤーボンディング時のリード４の機械的強度は維持される。尚、リード４の平坦面９の領域上にワイヤーボンディングされる場合でも良い。   Next, as shown in FIG. 1C, the semiconductor element 11 is fixed on the island 6 by an adhesive material 10 such as Ag paste or solder. A plurality of electrode pads 37 (see FIG. 5B) are formed on the upper surface of the semiconductor element 11, and the electrode pads 37 and the leads 4 are connected by the fine metal wires 12. As the thin metal wire 12, a gold wire or a copper wire is used. As shown in the drawing, the fine metal wire 12 is connected on the formation region of the groove 8, but the depth T1 of the groove 8 is adjusted, and the mechanical strength of the lead 4 during wire bonding is maintained. Note that wire bonding may be performed on the region of the flat surface 9 of the lead 4.

次に、図２（Ａ）は、図１（Ｂ）に示す樹脂パッケージ２のＢ−Ｂ線方向の断面図の一部を示す。先ず、詳細は製造方法の説明にて後述するが、樹脂モールド工程ではリード４の露出面側に樹脂モールド用シートを貼り合わせることで、リード４の露出面への樹脂の廻り込みを防止する。しかしながら、図示したように、その接着状況等に応じて、リード４の外周端部１３からリード４の露出面へと樹脂が廻り込み、樹脂ばり１４が発生する場合もある。   Next, FIG. 2A shows a part of a cross-sectional view of the resin package 2 shown in FIG. First, although details will be described later in the description of the manufacturing method, in the resin molding process, the resin mold sheet is bonded to the exposed surface side of the lead 4 to prevent the resin from getting around the exposed surface of the lead 4. However, as shown in the drawing, depending on the bonding state, the resin may go from the outer peripheral end 13 of the lead 4 to the exposed surface of the lead 4, and a resin flash 14 may be generated.

そこで、半導体装置１では、溝８が、リード４の外周端部１３の内側に配置され、溝８の深さＴ１は、例えば、リード４の厚みの１／２〜１／３程度となる。この構造により、樹脂モールド時にリード４の露出面に樹脂が廻り込んだ場合には、溝８は、廻り込んだ樹脂を溜め込む領域となる。そして、リード４の露出面の大部分が樹脂ばり１４により被覆され、実装領域が大幅に低減されることが防止される。   Therefore, in the semiconductor device 1, the groove 8 is disposed inside the outer peripheral end portion 13 of the lead 4, and the depth T <b> 1 of the groove 8 is, for example, about ½ to ３ of the thickness of the lead 4. With this structure, when the resin wraps around the exposed surface of the lead 4 at the time of resin molding, the groove 8 becomes a region for storing the wrapping resin. Then, most of the exposed surface of the lead 4 is covered with the resin beam 14 to prevent the mounting area from being significantly reduced.

尚、詳細は図６を用いて説明するが、リード４に溝８が形成されることで、リード４の露出面側の平坦面９の幅Ｗ１、Ｗ２が狭まる。そして、樹脂モールド時には、リード４の平坦面９は、シートの粘着層内に食い込み易くなり、樹脂が廻り込み難い構造となり、樹脂ばり１４の発生自体が大幅に低減される。   Although details will be described with reference to FIG. 6, by forming the groove 8 in the lead 4, the widths W <b> 1 and W <b> 2 of the flat surface 9 on the exposed surface side of the lead 4 are narrowed. When the resin molding is performed, the flat surface 9 of the lead 4 is easy to bite into the adhesive layer of the sheet, and the resin does not easily enter, and the occurrence of the resin flash 14 is greatly reduced.

次に、図２（Ｂ）は、図２（Ａ）に示す領域の平面図を示し、リード４の露出面への樹脂ばり１４の発生状況を示す。前述したように、リード４に溝８を形成することで、紙面右側のリード４のように、樹脂ばり１４の発生自体が抑止され易くなる。しかしながら、紙面中央や左側のリード４ように、リード４に樹脂ばり１４が発生した場合でも、リード４の溝８の内面が実装領域として用いられることで、リード４の実装面積が確保される。   Next, FIG. 2B shows a plan view of the region shown in FIG. 2A, and shows the state of occurrence of the resin flash 14 on the exposed surface of the lead 4. As described above, by forming the groove 8 in the lead 4, the occurrence of the resin flash 14 is easily suppressed as in the case of the lead 4 on the right side of the drawing. However, even when the resin flash 14 is generated on the lead 4 like the lead 4 at the center or the left side of the paper surface, the mounting area of the lead 4 is secured by using the inner surface of the groove 8 of the lead 4 as a mounting region.

この構造により、リード４への樹脂ばり１４の発生量が、実装強度に影響を与えない場合には、ウォータージェット等により樹脂ばり１４の除去工程が不要となる。また、従来の構造に対してリード４の実装領域が増大することで、樹脂ばり１４の除去工程の作業時間を短縮しても所望の実装強度は維持され、製造方法の簡略化が実現される。更に、樹脂パッケージ２が微細化され、リード４の露出面積が狭くなる場合でも、前述したように、溝８により実装領域が増大することで、樹脂ばり１４の除去工程の精度が悪化しても所望の実装強度は維持される。そして、樹脂ばり１４の除去の際に、リード４周囲の樹脂まで除去することが防止され、リード４が樹脂パッケージ２から抜け落ちる等の不良化が防止される。   With this structure, when the amount of the resin burrs 14 generated on the leads 4 does not affect the mounting strength, the step of removing the resin burrs 14 by a water jet or the like becomes unnecessary. Further, since the mounting area of the lead 4 is increased compared to the conventional structure, the desired mounting strength is maintained even if the working time of the resin beam 14 removal process is shortened, and the manufacturing method is simplified. . Further, even when the resin package 2 is miniaturized and the exposed area of the lead 4 is reduced, as described above, the mounting area is increased by the groove 8, so that the accuracy of the removal process of the resin beam 14 is deteriorated. The desired mounting strength is maintained. Then, when the resin beam 14 is removed, it is possible to prevent the resin around the leads 4 from being removed, and it is possible to prevent defects such as the leads 4 coming off the resin package 2.

次に、図２（Ｃ）は、図２（Ａ）に示す断面における実装状況を示す。樹脂パッケージ２は、実装基板１５の導電パターン１６上に接着材１７を介して実装される。接着材１７は、溝６の内面とも接合することで、実装強度も向上され、実装不良による歩留まりが低下することもない。そして、溝８は、樹脂パッケージ２の側面３まで配置されることで、実装時に接着材１７内に含まれる空気は、側面３側から外部へと排出され、接着材１７内にボイドが発生し難い構造となる。   Next, FIG. 2C shows a mounting state in the cross section shown in FIG. The resin package 2 is mounted on the conductive pattern 16 of the mounting substrate 15 via an adhesive material 17. By bonding the adhesive material 17 to the inner surface of the groove 6 as well, the mounting strength is improved, and the yield due to mounting defects is not reduced. Since the groove 8 is arranged up to the side surface 3 of the resin package 2, the air contained in the adhesive 17 at the time of mounting is discharged from the side 3 to the outside, and a void is generated in the adhesive 17. Difficult structure.

尚、図２（Ｃ）では、樹脂ばり１４の除去工程を省略し、リード４に樹脂ばり１４が形成された状態でも所望の実装強度が得られ、実装不良を招くこともない状況を示す。しかしながら、樹脂ばり１４の除去工程を行い、樹脂ばり１４を除去する場合でもよく、この場合には更に実装強度が向上し、半導体装置１の実装不良が回避される。   FIG. 2C shows a situation in which the step of removing the resin flash 14 is omitted, and a desired mounting strength can be obtained even when the resin flash 14 is formed on the lead 4 and no mounting failure is caused. However, the resin flash 14 may be removed and the resin flash 14 may be removed. In this case, the mounting strength is further improved and the mounting failure of the semiconductor device 1 is avoided.

次に、本発明の他の実施の形態である半導体装置について説明する。図３（Ａ）〜図３（Ｃ）は、樹脂パッケージの裏面から露出するアイランドを説明する平面図である。尚、図１及び図２に示す構造と同一の構成部材には同じ符番を付し、その説明を参照することとする。   Next, a semiconductor device according to another embodiment of the present invention will be described. FIGS. 3A to 3C are plan views illustrating islands exposed from the back surface of the resin package. In addition, the same number is attached | subjected to the same structural member as the structure shown in FIG.1 and FIG.2, and it shall refer to the description.

図３（Ａ）〜図３（Ｃ）では、樹脂パッケージ２から露出するアイランド６の裏面を半導体装置１の実装領域として用いる構造について説明する。図３（Ａ）に示すように、アイランド６の裏面を実装領域として用いる場合には、前述したリード４の場合と同様にアイランド６の裏面への樹脂ばり１８対策やアイランド６と導電パターンを接合する接着材へのボイド対策を行う必要がある。   3A to 3C, a structure in which the back surface of the island 6 exposed from the resin package 2 is used as a mounting region of the semiconductor device 1 will be described. As shown in FIG. 3A, when the back surface of the island 6 is used as a mounting region, the countermeasure against the resin flash 18 on the back surface of the island 6 and the island 6 and the conductive pattern are joined as in the case of the lead 4 described above. It is necessary to take measures against voids in the adhesive.

先ず、樹脂ばり１８対策について説明する。アイランド６の裏面に樹脂ばり１８が発生し、実装領域が偏ることで実装不良が発生し易くなる。また、樹脂ばり１８により実装領域が低減し、アイランド６での実装強度が低下する。そこで、アイランド６の裏面の外周端部１９の近傍に溝２０が配置される。そして、溝２０の深さが、例えば、アイランド６の厚みの１／２〜１／３程度となり、溝２０は、樹脂モールド時には樹脂ばり１８と成る樹脂を溜め込む領域となる。   First, a countermeasure against the resin beam 18 will be described. Resin burrs 18 are generated on the back surface of the island 6, and the mounting area is biased, so that mounting defects are likely to occur. Further, the mounting area is reduced by the resin beam 18 and the mounting strength on the island 6 is reduced. Therefore, the groove 20 is disposed in the vicinity of the outer peripheral end 19 on the back surface of the island 6. The depth of the groove 20 is, for example, about ½ to ３ of the thickness of the island 6, and the groove 20 is a region for accumulating a resin serving as the resin flash 18 during resin molding.

この構造により、アイランド６の裏面の端部１９から溝２０までの領域Ｗ３は、樹脂ばり１８の形成領域として用いられる。そして、アイランド６の裏面の領域Ｗ３では、端部１９からの平坦領域にて、アイランド６の露出面側への樹脂の廻り込みを規制し、樹脂ばり１８の発生自体を低減させる。   With this structure, a region W3 from the end 19 on the back surface of the island 6 to the groove 20 is used as a region where the resin beam 18 is formed. Then, in the region W3 on the back surface of the island 6, in a flat region from the end portion 19, the wrapping of the resin to the exposed surface side of the island 6 is restricted, and the generation of the resin flash 18 itself is reduced.

一方、アイランド６の裏面の溝２０より内側に位置する領域Ｗ４は、実装領域として用いられ、樹脂ばり１８が発生しない領域となる。これは、製造方法にて後述するリード４の場合と同様に、樹脂モールド用シートの粘着層により溝２０が塞がれることで、樹脂が領域Ｗ４へと廻り込むことが抑止されるからである。そして、アイランド６の領域Ｗ４は、露出領域として一定面積を有するため、確実に実装領域として利用でき、安定した実装強度も得られる。更に、領域Ｗ４には樹脂ばり１８が形成されることもなく、樹脂ばり１８を除去する工程を省くことができ、製造コストが低減される。また、樹脂パッケージ２が微細化された場合でも、溝２０により樹脂ばり１８の発生領域が調整され、樹脂ばり１８を除去する工程を省くことができ、製造方法の簡略化が実現される。   On the other hand, a region W4 located inside the groove 20 on the back surface of the island 6 is used as a mounting region and is a region where the resin flash 18 is not generated. This is because, as in the case of the lead 4 described later in the manufacturing method, the groove 20 is blocked by the adhesive layer of the resin mold sheet, thereby preventing the resin from entering the region W4. . And since the area | region W4 of the island 6 has a fixed area as an exposure area | region, it can utilize reliably as a mounting area | region and the stable mounting intensity | strength is also obtained. Further, the resin beam 18 is not formed in the region W4, and the process of removing the resin beam 18 can be omitted, and the manufacturing cost is reduced. Further, even when the resin package 2 is miniaturized, the region where the resin beam 18 is generated is adjusted by the groove 20, the step of removing the resin beam 18 can be omitted, and the manufacturing method can be simplified.

次に、接着材へのボイド対策について説明する。アイランド６の裏面の領域Ｗ４は、リード４の実装領域と比較してもその面積は大きく、使用される接着材の量も増大する。そのため、固着時に接着材内に含まれる空気や水分も多くなる。その結果、接着材内の空気やガスの量も多くなり、その空気やガスが偏った状態にて接着材が硬化することで、ボイドが発生する。そして、ボイドの発生により実装強度が低下し、半導体装置１が導電パターンから剥離する原因にもなる。その他、ボイド領域に水分が溜まり、駆動熱により気化し爆発し、また、半導体装置１の放熱性を悪化させる等、ボイドにより製品品質が劣化する原因となる。   Next, countermeasures against voids in the adhesive will be described. The area W4 on the back surface of the island 6 is larger than the area where the leads 4 are mounted, and the amount of adhesive used is also increased. Therefore, the air and moisture contained in the adhesive at the time of fixing increase. As a result, the amount of air and gas in the adhesive increases, and voids are generated when the adhesive is cured in a state where the air and gas are biased. Then, the generation of voids reduces the mounting strength, which also causes the semiconductor device 1 to peel from the conductive pattern. In addition, moisture accumulates in the void region, vaporizes and explodes due to driving heat, and causes the product quality to deteriorate due to voids such as deterioration of the heat dissipation of the semiconductor device 1.

そこで、実装領域として用いられる領域Ｗ４に溝２１〜２４を配置することで、接着材の硬化時に溝２１〜２４を介して空気やガスを領域Ｗ４全体に拡散させる。そして、ボイドが接着材内に偏って形成されることを防止し、実装強度等を向上させ、製品品質の劣化が防止される。そして、接着材内のボイドの発生を低減させるためのアイランド６の裏面の溝形状としては、様々な形状が採用される。例えば、図３（Ｂ）に示すように、領域Ｗ４の中心から外周側の４方向へと広がる花びら形状の溝２５が形成される場合でも良い。また、図３（Ｃ）に示すように、領域Ｗ４に×形状の溝２６が形成され、その溝２６に対し四角形状の溝２７〜２９が連結して形成される場合でも良い。   Therefore, by arranging the grooves 21 to 24 in the region W4 used as the mounting region, air and gas are diffused throughout the region W4 through the grooves 21 to 24 when the adhesive is cured. And it prevents that a void is unevenly formed in an adhesive material, improves mounting strength etc. and prevents deterioration of product quality. And various shapes are employ | adopted as a groove | channel shape of the back surface of the island 6 for reducing generation | occurrence | production of the void in an adhesive material. For example, as shown in FIG. 3B, a petal-shaped groove 25 extending from the center of the region W4 in four directions on the outer peripheral side may be formed. In addition, as shown in FIG. 3C, a case where the X-shaped groove 26 is formed in the region W <b> 4 and the rectangular grooves 27 to 29 are connected to the groove 26 may be used.

尚、本実施の形態では、ＭＡＰ型の樹脂パッケージ２について説明したが、この場合に限定するものではない。例えば、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄｅｄ Ｐａｃｋａｇｅ）型の樹脂パッケージにおいても、リード形状やアイランド形状を前述した形状と同様に加工することで、同様な効果が得られる。   In the present embodiment, the MAP type resin package 2 has been described. However, the present invention is not limited to this case. For example, even in a QFN (Quad Flat Non-Leaded Package) type resin package, the same effect can be obtained by processing the lead shape and the island shape in the same manner as described above.

また、樹脂パッケージ２の裏面５からアイランド６が露出する場合について説明したが、この場合に限定するものではない。少なくともリード４が樹脂パッケージ２から露出する構造において、そのリード４に溝８が形成されることで前述した効果が得られれば良い。そして、樹脂パッケージ２の裏面５からアイランド６が露出し、図３を用いた説明した構造とする場合には、その効果も得られる。その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。   Moreover, although the case where the island 6 is exposed from the back surface 5 of the resin package 2 has been described, the present invention is not limited to this case. In the structure in which at least the lead 4 is exposed from the resin package 2, the above-described effect may be obtained by forming the groove 8 in the lead 4. When the island 6 is exposed from the back surface 5 of the resin package 2 and the structure described with reference to FIG. 3 is used, the effect is also obtained. In addition, various modifications can be made without departing from the scope of the present invention.

次に、本発明の他の実施の形態である半導体装置の製造方法について説明する。図４は、リードフレームを説明する平面図である。図５（Ａ）及び（Ｂ）は、ボンディング工程を説明する平面図である。図６（Ａ）〜図６（Ｃ）は、樹脂モールド工程を説明する断面図である。図７はスクライブ工程を説明する（Ａ）平面図、（Ｂ）断面図である。尚、本実施の形態では、図１及び図２に示す構造の製造方法を説明するため、同一の構成部材には同一の符番を付している。   Next, a method for manufacturing a semiconductor device according to another embodiment of the present invention will be described. FIG. 4 is a plan view for explaining the lead frame. 5A and 5B are plan views illustrating the bonding process. 6A to 6C are cross-sectional views illustrating a resin molding process. FIG. 7A is a plan view and FIG. 7B is a sectional view for explaining a scribe process. In the present embodiment, the same components are denoted by the same reference numerals in order to describe the manufacturing method of the structure shown in FIGS.

先ず、図４に示す如く、例えば、銅を主材料とするリードフレーム３１を準備する。リードフレーム３１には、一点鎖線で示すように、複数の搭載部３２が形成される。リードフレーム３１の長手方向（紙面Ｘ軸方向）は、スリット３３により一定間隔に区切られる。そして、スリット３３にて区切られたリードフレーム３１の１区間には、例えば、４つの搭載部３２の集合から成る１つの集合ブロックが形成される。複数の集合ブロックが、リードフレーム３１の長手方向に形成される。また、リードフレーム３１の長手方向には、その上下端部領域にインデックス孔３４が設けられ、各工程での位置決めに用いられる。   First, as shown in FIG. 4, for example, a lead frame 31 mainly made of copper is prepared. A plurality of mounting portions 32 are formed on the lead frame 31 as indicated by a one-dot chain line. The longitudinal direction (paper surface X-axis direction) of the lead frame 31 is divided at regular intervals by the slits 33. In one section of the lead frame 31 delimited by the slits 33, for example, one collective block made up of a set of four mounting portions 32 is formed. A plurality of collective blocks are formed in the longitudinal direction of the lead frame 31. In the longitudinal direction of the lead frame 31, index holes 34 are provided in the upper and lower end regions, and are used for positioning in each process.

次に、図５（Ａ）では、リードフレーム３１に形成された１つの搭載部３２を示す。搭載部３２は、主に、アイランド６と、アイランド６を支持する吊りリード３５と、アイランド６の４側辺の近傍にその一端が位置するリード４と、複数のリード４を支持するタイバー３６とから構成される。そして、吊りリード３５はアイランド６の４つのコーナー部から延在し、タイバー３６と連結し、アイランド６がリードフレーム３１に支持される。図示したように、リード４、アイランド６及び吊りリード３５の斜線のハッチングにて示す領域は、リードフレーム３１の裏面側からハーフエッチングされ、窪んだ領域となる。この工程により、リード４の実装面側に溝８（図１（Ｂ）参照）が形成される。   Next, FIG. 5A shows one mounting portion 32 formed on the lead frame 31. The mounting portion 32 mainly includes an island 6, a suspension lead 35 that supports the island 6, a lead 4 having one end located near the four sides of the island 6, and a tie bar 36 that supports the plurality of leads 4. Consists of The suspension leads 35 extend from the four corners of the island 6, are connected to the tie bars 36, and the island 6 is supported by the lead frame 31. As shown in the drawing, the hatched areas of the lead 4, the island 6, and the suspension lead 35 are half-etched from the back side of the lead frame 31 to become a depressed area. By this step, a groove 8 (see FIG. 1B) is formed on the mounting surface side of the lead 4.

次に、図５（Ｂ）に示す如く、ダイボンド装置の載置台上にリードフレーム３１を配置し、リードフレーム３１の搭載部３２毎にダイボンディングを行う。具体的には、リードフレーム３１のアイランド６上にＡｇペースト、半田等の接着材１０（図１（Ｃ）参照）を塗布し、半導体素子１１を固着する。次に、ワイヤーボンディング装置の載置台上にリードフレーム３１を配置し、リードフレーム３１の搭載部３２毎にワイヤーボンディングを行う。具体的には、金属細線１２が、電極パッド３７上面にボールボンディングされ、リード４上面にステッチボンディングされることで、半導体素子１１の電極パッド３７とリード４とが金属細線１２により電気的に接続される。   Next, as shown in FIG. 5B, the lead frame 31 is placed on the mounting table of the die bonding apparatus, and die bonding is performed for each mounting portion 32 of the lead frame 31. Specifically, an adhesive 10 such as an Ag paste or solder (see FIG. 1C) is applied on the island 6 of the lead frame 31 to fix the semiconductor element 11. Next, the lead frame 31 is disposed on the mounting table of the wire bonding apparatus, and wire bonding is performed for each mounting portion 32 of the lead frame 31. Specifically, the fine metal wire 12 is ball-bonded to the upper surface of the electrode pad 37 and stitch-bonded to the upper surface of the lead 4 so that the electrode pad 37 of the semiconductor element 11 and the lead 4 are electrically connected by the fine metal wire 12. Is done.

次に、図６（Ａ）に示す如く、リードフレーム３１上の集合ブロック毎に樹脂モールドし、共通の樹脂パッケージを形成する。例えば、リードフレーム３１の裏面側に樹脂モールド用のシート３８を貼り合せた後、樹脂封止金型の下金型３９上面にシート３８が当接するようにリードフレーム３１を配置する。そして、各集合ブロック間に位置するリードフレーム３１を上金型４０と下金型３９にて挟持するように、樹脂封止金型内にリードフレーム３１を固定する。このとき、１つのキャビティ４１内には、４つの搭載部３２が配置され、一体に樹脂モールドされる。尚、図示していないが、例えば、下金型３９に吸引機構を設けることで、下金型３９とシート３８の密着性が向上され、樹脂パッケージ裏面（実装面）側の平坦性が実現され、樹脂ばりが発生し難い状況にて樹脂モールドが行われる。   Next, as shown in FIG. 6A, resin molding is performed for each assembly block on the lead frame 31 to form a common resin package. For example, after a resin mold sheet 38 is bonded to the back side of the lead frame 31, the lead frame 31 is disposed so that the sheet 38 contacts the upper surface of the lower mold 39 of the resin-sealed mold. Then, the lead frame 31 is fixed in the resin-sealed mold so that the lead frame 31 positioned between the assembly blocks is sandwiched between the upper mold 40 and the lower mold 39. At this time, four mounting portions 32 are disposed in one cavity 41 and integrally molded with resin. Although not shown, for example, by providing the lower mold 39 with a suction mechanism, the adhesion between the lower mold 39 and the sheet 38 is improved, and flatness on the back surface (mounting surface) side of the resin package is realized. Resin molding is performed in a situation where resin burrs are unlikely to occur.

図６（Ｂ）に示すように、樹脂モールド用のシート３８は、例えば、破断強度が大きく、簡単には伸縮しない材料であるＰＥＴ材からなる基材４２上面に３μｍ程度の粘着層４３が全面に設けられている。そのため、リードフレーム３１をシート３８に貼り合わせ、樹脂封止金型内に固定すると、リードフレーム３１が粘着層４３へと入り込む。そして、リード４の溝８の形成領域では、リード４に押し流された粘着層５３が溝８へと入り込む。このとき、溝８周辺のリード４の平坦面９は粘着層４３と密着し、溝８内では粘着層４３は若干盛り上がり、溝８は粘着層４３により塞がれた状態となる。そして、図２（Ｂ）に示すように、リード４に溝８を形成することで、粘着層４３へと入り込むリード４の平坦面９の幅Ｗ１、Ｗ２は狭まる。そのため、樹脂封止金型の挟持による押圧力によりリード４の平坦面９はより粘着層４３内へと入り込み、前述した密着性が強まり、平坦面９は剥がれ難い領域となる。   As shown in FIG. 6B, the resin mold sheet 38 has, for example, an adhesive layer 43 of about 3 μm on the entire upper surface of a base material 42 made of a PET material that has a high breaking strength and does not easily expand and contract. Is provided. Therefore, when the lead frame 31 is bonded to the sheet 38 and fixed in the resin-sealed mold, the lead frame 31 enters the adhesive layer 43. In the region where the groove 8 of the lead 4 is formed, the adhesive layer 53 pushed away by the lead 4 enters the groove 8. At this time, the flat surface 9 of the lead 4 around the groove 8 is in close contact with the adhesive layer 43, the adhesive layer 43 rises slightly in the groove 8, and the groove 8 is closed by the adhesive layer 43. Then, as shown in FIG. 2B, by forming the groove 8 in the lead 4, the widths W1 and W2 of the flat surface 9 of the lead 4 entering the adhesive layer 43 are narrowed. Therefore, the flat surface 9 of the lead 4 further enters the adhesive layer 43 due to the pressing force by sandwiching the resin-sealed mold, and the above-described adhesion becomes stronger, and the flat surface 9 becomes a region that is difficult to peel off.

図６（Ｃ）では、樹脂モールド工程によりリード４に樹脂ばり１４が発生した状況を示す。リード４と粘着層４３とが密着した状態により樹脂モールド工程を行うが、樹脂の圧力等によりリード４の端部１３から粘着層４３が若干剥がれ、樹脂ばり１４が発生する場合もある。この場合でも、段々と粘着層４３が剥がれることでリード４の露出面側に廻り込む樹脂量は規制され、樹脂ばり１４の厚みも数十μｍ程度である。   FIG. 6C shows a situation in which the resin flash 14 is generated on the lead 4 by the resin molding process. The resin molding process is performed in a state where the lead 4 and the adhesive layer 43 are in close contact with each other. However, the adhesive layer 43 may be slightly peeled off from the end portion 13 of the lead 4 due to the pressure of the resin, and the resin flash 14 may be generated. Even in this case, the amount of the resin that goes around the exposed surface side of the lead 4 is regulated by gradually peeling off the adhesive layer 43, and the thickness of the resin beam 14 is about several tens of μm.

そして、樹脂ばり１４を形成する樹脂が溝８まで到達した場合、丸印４４で示すように、先ず、リード４の端部１３側から溝８内へと樹脂が入り込み、端部１３側の溝８内から充填される。この場合、丸印４５で示すように、溝８内の粘着層４３がその他の領域へと追いやられ、その領域では平坦面９と粘着層４３との密着度が更に強くなり、その領域から溝８内への樹脂の流入が防止される。更に、前述したように、リード４の平坦面９と粘着層４３との密着性が強いため、そもそも樹脂の廻り込み自体が大幅に低減される。その結果、溝８内全てが樹脂で充填されることはなく、樹脂ばり１４の除去工程を省略した場合でも、実装領域が確保され易く、所望の実装強度が得られる。   When the resin forming the resin beam 14 reaches the groove 8, first, as indicated by a circle 44, the resin enters the groove 8 from the end 13 side of the lead 4, and the groove on the end 13 side is first. 8 is filled from within. In this case, as indicated by a circle 45, the adhesive layer 43 in the groove 8 is driven to another region, and in that region, the degree of adhesion between the flat surface 9 and the adhesive layer 43 is further increased, and from that region, the groove The inflow of resin into 8 is prevented. Furthermore, as described above, since the adhesion between the flat surface 9 of the lead 4 and the adhesive layer 43 is strong, the wraparound of the resin itself is greatly reduced in the first place. As a result, the entire groove 8 is not filled with resin, and even when the step of removing the resin beam 14 is omitted, a mounting area is easily secured and desired mounting strength can be obtained.

尚、樹脂ばり１４の除去工程は必ずしも省略される訳ではなく、樹脂ばり１４の除去工程を行うことで、更なる実装強度が向上される。また、樹脂モールド時には、リードフレーム３１に形成された溝８の全周囲は平坦面９により囲まれている。   In addition, the removal process of the resin beam 14 is not necessarily omitted, and the mounting strength is further improved by performing the removal process of the resin beam 14. Further, during resin molding, the entire periphery of the groove 8 formed in the lead frame 31 is surrounded by the flat surface 9.

次に、図７（Ａ）に示す如く、樹脂モールド工程によりリードフレーム３１上には、集合ブロック毎に共通の樹脂パッケージ４６が形成される。上述したように、共通の樹脂パッケージ４６内には、４つの搭載部３２が含まれる。   Next, as shown in FIG. 7A, a common resin package 46 is formed on each lead block 31 on the lead frame 31 by a resin molding process. As described above, the four mounting portions 32 are included in the common resin package 46.

最後に、図７（Ｂ）に示す如く、リードフレーム３１から搭載部３２毎に共通の樹脂パッケージ４６を切断して、個々の樹脂パッケージ２に個片化する。切断にはスクライブ装置のダイシングブレード４７を用い、ダイシングライン４８に沿って共通の樹脂パッケージ４６とリードフレーム３１とを同時に切断する。このとき、シート３８は、その一部のみが切断されることで、個片化された個々の樹脂パッケージ２はシート３８上に支持される。また、ダイシングライン４８はリード４の溝８の形成領域に配置されるため、共通の樹脂パッケージ４６を個片化することで、樹脂パッケージ２の側面３からリード４及び溝８が露出することとなる。   Finally, as shown in FIG. 7B, the resin package 46 common to each mounting portion 32 is cut from the lead frame 31 and separated into individual resin packages 2. For cutting, a dicing blade 47 of a scribing device is used, and the common resin package 46 and the lead frame 31 are simultaneously cut along the dicing line 48. At this time, only a part of the sheet 38 is cut so that the individual resin packages 2 separated into pieces are supported on the sheet 38. In addition, since the dicing line 48 is disposed in the formation region of the groove 8 of the lead 4, by separating the common resin package 46, the lead 4 and the groove 8 are exposed from the side surface 3 of the resin package 2. Become.

尚、本実施の形態では、ワイヤーボンディング工程後にリードフレーム３１に樹脂モールド用のシート３８を貼り合せる工程について説明したが、この場合に限定するものではない。例えば、リードフレームに樹脂モールド用のシート３８を貼り合せた後にリードフレームに対しダイボンディング、ワイヤーボンディング工程を行う場合でも良い。   In the present embodiment, the step of bonding the resin mold sheet 38 to the lead frame 31 after the wire bonding step has been described. However, the present invention is not limited to this case. For example, a die bonding and wire bonding process may be performed on the lead frame after the resin mold sheet 38 is bonded to the lead frame.

また、図３を用いて前述したように、リード４に溝８を形成する工程、あるいは別工程にて、アイランド６に溝２０〜２９を形成する場合でも良い。その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。   Further, as described above with reference to FIG. 3, the grooves 20 to 29 may be formed in the island 6 in the step of forming the groove 8 in the lead 4 or in another step. In addition, various modifications can be made without departing from the scope of the present invention.

１ 半導体装置
２ 樹脂パッケージ
４ リード
６ アイランド
８ 溝
１４ 樹脂ばり 1 Semiconductor Device 2 Resin Package 4 Lead 6 Island 8 Groove 14 Resin Beam

Claims (8)

アイランドと、前記アイランドの周囲に配置されたリードと、前記アイランド上に接着材を介して固着された半導体素子と、前記半導体素子と前記リードとを電気的に接続する金属細線と、前記アイランド、前記リード、前記金属細線及び前記半導体素子を被覆する樹脂パッケージとを有する半導体装置において、
前記リードの一部は、前記樹脂パッケージの実装面から露出し、前記リードには、前記リードの外周端部よりも内側に前記露出面側から溝が配置され、前記溝と前記外周端部との間には前記リードの平坦面が配置されることを特徴とする半導体装置。 An island, a lead disposed around the island, a semiconductor element fixed on the island via an adhesive, a thin metal wire electrically connecting the semiconductor element and the lead, the island, In the semiconductor device having the lead, the thin metal wire, and a resin package covering the semiconductor element,
A part of the lead is exposed from the mounting surface of the resin package, and the lead is provided with a groove from the exposed surface side inside the outer peripheral end of the lead, and the groove, the outer peripheral end, A semiconductor device, wherein a flat surface of the lead is disposed between the two. 前記リード及び前記溝は前記樹脂パッケージの側面から露出することを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the lead and the groove are exposed from a side surface of the resin package. 前記溝の内側面は、前記リードの実装領域として用いられることを特徴とする請求項１または請求項２に記載の半導体装置。 The semiconductor device according to claim 1, wherein an inner surface of the groove is used as a mounting region for the lead. 前記アイランドの一部は、前記樹脂パッケージの実装面から露出し、前記アイランドには、前記アイランドの外周端部よりも内側に前記露出面側から一環状の溝が配置され、少なくとも前記溝の内側に位置する前記アイランドの露出面は実装領域として用いられることを特徴とする請求項１から請求項３のいずれか１項に記載の半導体装置。 A part of the island is exposed from the mounting surface of the resin package, and the island is provided with an annular groove from the exposed surface side inside the outer peripheral end of the island, and at least the inside of the groove 4. The semiconductor device according to claim 1, wherein an exposed surface of the island located at a position is used as a mounting region. 5. 前記溝の内側に位置する前記アイランドの露出面には、前記露出面に塗布される接着材内の空気を拡散させるボイド拡散溝が形成されることを特徴とする請求項１から請求項４のいずれか１項に記載の半導体装置。 5. The void diffusion groove for diffusing air in the adhesive applied to the exposed surface is formed on the exposed surface of the island located inside the groove. The semiconductor device according to any one of the above. アイランドと、前記アイランドの周囲に配置された複数のリードとを有する搭載部が設けられたリードフレームを準備し、
前記アイランドの一主面上に半導体素子を固着し、前記半導体素子の電極パッドと前記リードの一主面とを金属細線によりワイヤーボンディングし、
前記搭載部を樹脂で被覆し、少なくとも前記リードフレームの一主面側を被覆するように樹脂パッケージを形成する半導体装置の製造方法において、
前記リードの他の主面側に前記リードの外周端部から連続した平坦面の内側に溝を形成した後、前記リードフレームの他の主面にシートを貼り合わせ、前記溝が前記シートにより塞がれた状態にて前記樹脂パッケージを形成する樹脂モールド工程を行うことを特徴とする半導体装置の製造方法。 Preparing a lead frame provided with a mounting portion having an island and a plurality of leads arranged around the island;
A semiconductor element is fixed on one main surface of the island, and an electrode pad of the semiconductor element and one main surface of the lead are wire-bonded with a thin metal wire,
In the method of manufacturing a semiconductor device in which the mounting portion is covered with a resin and a resin package is formed so as to cover at least one main surface side of the lead frame.
After forming a groove on the other main surface side of the lead inside a flat surface continuous from the outer peripheral end of the lead, a sheet is bonded to the other main surface of the lead frame, and the groove is closed by the sheet. A method of manufacturing a semiconductor device, comprising performing a resin molding step of forming the resin package in a peeled state. 前記リードの他の主面では、前記リードの平坦面が前記シートを構成する粘着層と密着し、前記溝が前記粘着層により塞がれた状態にて前記樹脂モールド工程を行うことを特徴とする請求項６に記載の半導体装置の製造方法。 In the other main surface of the lead, the resin molding step is performed in a state where the flat surface of the lead is in close contact with the adhesive layer constituting the sheet and the groove is closed by the adhesive layer. A method for manufacturing a semiconductor device according to claim 6. 前記樹脂モールド工程では、複数の前記搭載部を一括して樹脂モールドした後、前記溝が形成された領域のリードフレームを切断し、前記樹脂パッケージの側面から前記リード及び前記溝を露出させることを特徴とする請求項６または請求項７に記載の半導体装置の製造方法。 In the resin molding step, the plurality of mounting portions are collectively resin-molded, and then the lead frame in the region where the groove is formed is cut to expose the lead and the groove from the side surface of the resin package. 8. A method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is manufactured.
JP2009268764A 2009-11-26 2009-11-26 Semiconductor device and method of manufacturing the same Pending JP2011114136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009268764A JP2011114136A (en) 2009-11-26 2009-11-26 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009268764A JP2011114136A (en) 2009-11-26 2009-11-26 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2011114136A true JP2011114136A (en) 2011-06-09

Family

ID=44236243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009268764A Pending JP2011114136A (en) 2009-11-26 2009-11-26 Semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2011114136A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016709A (en) * 2011-07-05 2013-01-24 Toshiba Corp Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294719A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Lead frame, semiconductor device using the same, and manufacture thereof
JP2008244043A (en) * 2007-03-27 2008-10-09 Denso Corp Mounting structure of mold package
JP2009188147A (en) * 2008-02-06 2009-08-20 Sanyo Electric Co Ltd Manufacturing method of circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294719A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Lead frame, semiconductor device using the same, and manufacture thereof
JP2008244043A (en) * 2007-03-27 2008-10-09 Denso Corp Mounting structure of mold package
JP2009188147A (en) * 2008-02-06 2009-08-20 Sanyo Electric Co Ltd Manufacturing method of circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013016709A (en) * 2011-07-05 2013-01-24 Toshiba Corp Semiconductor device

Similar Documents

Publication Publication Date Title
JP4159431B2 (en) Manufacturing method of semiconductor device
JP5634033B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
KR101160694B1 (en) Manufacturing Method of Semiconductor Device
US9793194B2 (en) Leadframe
JP2001320007A (en) Frame for resin sealed semiconductor device
JP2011077278A (en) Semiconductor device, and method of manufacturing the same
US9984958B2 (en) Leadframe and semiconductor device
JP2005026466A (en) Semiconductor device and lead frame
JP2011091145A (en) Semiconductor device and method of manufacturing the same
US20130320527A1 (en) Semiconductor device and semiconductor device manufacturing method
JP2004349316A (en) Semiconductor device and its manufacturing method
US8999761B2 (en) Method of manufacturing semiconductor device
US8829685B2 (en) Circuit device having funnel shaped lead and method for manufacturing the same
JP2011142337A (en) Method of manufacturing semiconductor device
JP2011114136A (en) Semiconductor device and method of manufacturing the same
JP6322853B2 (en) LED package, multi-row LED lead frame, and manufacturing method thereof
US20020048851A1 (en) Process for making a semiconductor package
JP2006210941A (en) Semiconductor device
JP4732138B2 (en) Semiconductor device and manufacturing method thereof
JP5285289B2 (en) Circuit device and manufacturing method thereof
JP5467506B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP2009188147A (en) Manufacturing method of circuit device
JP4455166B2 (en) Lead frame
JP2002026192A (en) Lead frame
KR20020093250A (en) ELP type leadframe and ELP using the same

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20110606

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121105

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20130218

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130408

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130521

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20131029