JPH1126643A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized resin-sealed semiconductor device having outer terminals made from solder balls disposed like a lattice on the bottom face. SOLUTION: A small-sized resin-sealed semiconductor device is obtained by fixing a lead frame fixed through adhesives 7 to the bottom of a chip 1 having pads 8 at the periphery, sealing it with a resin so that protrusions on the opposite side of the lead frame to the chip mounting side are exposed after electric connection of the pads 8 to the lead frame through wires 3, and mounting solder balls on the exposed protrusion 5 to form the balls like a matrix on the bottom face.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a resin-encapsulated semiconductor device in which solder balls serving as external electrode terminals are arranged in a lattice pattern on the bottom surface.

[0002]

2. Description of the Related Art FIG. 4 shows the structure of a conventional resin-encapsulated semiconductor device having external terminals on the bottom surface. 4A is a cross-sectional view, and FIG. 4B is a plan view as viewed from an external terminal side.

Referring to FIG. 4, a semiconductor chip (hereinafter, referred to as a “chip”) 1 is bonded to an internal lead 4 via an adhesive 7 on an element surface side. 3 are electrically connected. The chip 1, the internal lead, the wire, and the like are resin-sealed with the resin 2, the end of the internal lead 4 is adhered to the chip, and is bent and bent at a dimple-processed portion (hereinafter referred to as "Dp-processed portion") 9 in the middle. One main surface of the other end of the internal lead is exposed from the resin to form an external terminal 16.

In the semiconductor device having such a structure, since the processing of the Dp processing portion 9 is generally performed by a press die, it is difficult to obtain the processing accuracy, and resin burrs are formed on the surface of the external terminal 16 during resin sealing. There is a problem that it easily occurs.

Further, since the external terminals 16 are arranged along each side of the semiconductor device (see FIG. 4B), they can be arranged only in one row of each side, and the number of external terminals arranged is limited. Have a point.

[0006] Furthermore, because of the LOC (Lead on Chip) structure in which leads are bonded to the elements of the chip, there is a restriction that the electrode pads on the chip must be arranged at the center of the chip. That is, in general, the electrode pads on the chip are generally arranged on the periphery of the chip. In this case, when the LOC structure is used, it is necessary to pass leads between the electrode pads. However, the LOC structure cannot be adopted unless the lead width is 0.1 to 0.2 mm or more.

[0007]

As a conventional method intended to solve such a problem in the LOC structure, for example, Japanese Unexamined Patent Publication No. 8-148603 discloses a method as shown in FIG. CO bonded with chip element side up
An L (Chip on Lead) structure has been proposed. FIG. 5 (a) is a plan view from the solder ball side, and FIG. 5 (b)
FIG. 6 is a sectional view taken along line AA ′ of FIG.

Referring to FIG. 5, a chip 1 is bonded on an internal lead 4 via an adhesive tape 13 with an element surface facing upward, and an electrode pad arranged on the periphery of the chip surface and the internal lead 4 are connected to a wire 3. Are electrically connected. The chip 1, the internal leads 4, the wires 3, and the like are sealed with a resin. The lower package 15 is provided with a hole 12. The solder ball 6 is adhered to the hole 12, and a lattice is formed on the bottom surface of the semiconductor device as an external terminal. And are electrically connected to the internal leads.

In such a structure, it can be easily performed when the electrode pads on the chip surface are arranged on the periphery of the chip, and since the solder balls as the external terminals can be arranged in a lattice, the external terminals can be arranged. The number can be doubled without any pitch reduction.

However, since the holes 12 for connecting the solder balls are formed by drilling or laser processing after resin sealing, there is a problem that the number of processing steps increases and processing time is required.

It is conceivable to omit the hole forming step by forming a hole in the encapsulation mold in the conventional transfer mold in advance and forming a hole at the same time as the resin encapsulation. Due to the limitations of processing technology, it is difficult to make the interval between protrusions less than 0.8 mm, and it is not possible to respond to a narrow pitch of less than 0.8 mm, and if the number of external terminals increases, There is a problem that the package becomes large.

Further, a projection is provided on the encapsulating mold to form a hole 12.
When forming solder balls, if the arrangement of solder balls is changed with the same package size, an encapsulation mold must be manufactured for each ball arrangement, which is enormous and expensive. When the resin residue is generated, there is a problem that the maintainability such as a resin removing operation is significantly inferior to that of a normal sealing mold.

The problems of the prior art described above are summarized as follows.

The first problem is a resin-encapsulated semiconductor device having external terminals on the bottom surface of the semiconductor device. When the inside has a LOC structure, the arrangement of electrode pads on the chip surface is limited to the center of the chip. This means that it is difficult to cope with the case where the chips are arranged on the periphery of the chip.

[0015] The reason is that in the case of the LOC structure, the leads are adhered on the chip. However, if the electrode pads are arranged on the periphery of the chip, it is necessary to pass the leads between the electrode pads. This is because it is difficult to deal with it unless it is wide enough.

The second problem is a resin-encapsulated semiconductor device having an external terminal on the bottom surface of the semiconductor device. When the inside has a COL structure, a solder ball as an external terminal is connected to an internal lead. That is, a processing step is required.

The reason for this is that a hole is formed after sealing with a resin, so that a laser or drill processing step is required and processing time is required.

Also, in a resin-sealed semiconductor device having an external terminal on the bottom surface of the semiconductor device, when the inside has a LOC structure, one end of an internal lead is bonded to a chip, the middle is bent, and the other end is used as an external terminal. In the case of a structure that is exposed from the resin surface, the arrangement of external terminals is limited to a line on each side of the semiconductor device due to the structure, and the number of external terminals is limited because external terminals cannot be arranged in a grid pattern. There is a problem in that it is difficult to control the bending accuracy and resin burrs are easily generated during resin sealing.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a resin-encapsulated semiconductor device having external terminals on the bottom surface of the semiconductor device.
It is possible to cope with the case where the electrode pads on the chip surface are arranged on the periphery of the chip, and it is also possible to arrange the external terminals in a grid pattern, and to expose the internal leads which are the connection portions of the solder balls to be the external terminals. It is an object of the present invention to provide a semiconductor device which can form an exposed surface at the same time as resin sealing without requiring.

[0020]

In order to achieve the above object, in a resin-encapsulated semiconductor device according to the present invention, a semiconductor back surface is fixed to a front end surface of an internal lead group via an adhesive, and an electrode on a chip surface is provided. The pad and the other end surface of the internal lead group are connected by a wire, and a protrusion is formed on the back surface side of the internal lead group. At least the chip, the internal lead group, the wire, and the like except for one main surface of the protrusion It includes means in which the solder ball is joined to one main surface of the projection by resin sealing.

[0021]

Embodiments of the present invention will be described below. According to a preferred embodiment of the present invention, in a resin-sealed semiconductor device having external terminals formed in a lattice pattern on a bottom surface, an internal lead (4 in FIG. 1) is provided.
The back surface of the semiconductor chip (1 in FIG. 1) is fixed to the front surface of the group via an adhesive (7 in FIG. 1), and the semiconductor chip (FIG.
1) The electrode pads on the surface and the other end surface of the group of internal leads (3 in FIG. 1) are connected by wires (3 in FIG. 1), and the protrusions (4) on the rear side of the group of internal leads (4 in FIG. 1). 1) is formed, and the semiconductor chip, the internal lead group, the wires, and the like are sealed with a resin (2 in FIG. 1) except for one main surface of the projection (5 in FIG. 1). 1-5) has a structure in which a solder ball (6 in FIG. 1) is joined to one main surface.

In the embodiment of the present invention, the back surface of the chip is fixed to the front end surface of the internal lead group, and the electrode pad on the chip surface and the other end surface of the internal lead group are connected by a wire. Because of the on-lead structure, it is possible to easily cope with the case where the electrode pads are arranged on the periphery of the chip. In addition, since the solder balls serving as the external terminals are formed on the protrusions formed on the back surface of the internal lead group, a grid-like external terminal arrangement is possible. It is possible to form an exposed portion on one main surface of the projection.

The semiconductor device of the present invention has a preferable second
In the embodiment, the back surface of the semiconductor chip is fixed to the front end surface of the group of internal leads (2 in FIG. 2) via an adhesive (7 in FIG. 2), and the group of internal leads (4 in FIG. 2) is connected to the semiconductor chip. (1 in FIG. 2) At the position outside the edge, it is bent upward (9 in FIG. 2), and the other end of the internal lead group bent upward and the electrode pad of the semiconductor chip are wires (FIG. 2). They are connected in 2) 3).

The semiconductor device of the present invention has a preferable third
In the embodiment, the back surface of the semiconductor chip is fixed to the front surface of the group of internal leads via an adhesive (7 in FIG. 3), and the protrusion (FIG. 3) is formed on the surface of the other end of the group of internal leads (4 in FIG. 3). 2 10) is formed, and the electrode pads of the semiconductor chip (1 in FIG. 3) and the protrusions are connected by wires.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] FIG. 1 is a view showing the structure of an embodiment of the present invention. FIG. 1 (a) is a side sectional view, and FIG.
(B) is a plan view as seen from the solder ball side.

Referring to FIG. 1, in a resin-encapsulated semiconductor device according to an embodiment of the present invention, a portion other than a portion serving as a protrusion 5 of an internal lead 4 is reduced in thickness by half-etching or the like to form a protrusion. The chip 1 is mounted on the lead frame on which the protrusion 5 is formed on the surface opposite to the protrusion surface via an adhesive 7, and the electrode pad 8 and the internal lead 4 are electrically connected by the wire 3, and then the protrusion 5 is exposed. And the solder balls 6 are attached to the exposed protrusions 5.

In the resin-sealed semiconductor device according to one embodiment of the present invention, the lower package portion of the encapsulation mold is flat, and the pitch of the solder balls 6 depends on the processing technology of the lead frame, and is less than 0.8 mm. Even if the number of external terminals increases, the package size does not increase due to the shrinkage of the solder ball pitch.If the number of external terminals is the same, the package can be adjusted according to the chip size. It is possible to reduce the size.

Further, even in the case of the same semiconductor device size, even when the chip to be mounted is different and the arrangement of the solder balls is changed to a full grid type, a flange type, or the like, only the lead frame needs to be changed, and it is easy to cope. .

As shown in FIG. 1, the resin-sealed semiconductor device of one embodiment of the present invention has a COL structure.
It can be easily manufactured when the electrode pads 8 on the surface of the chip 1 are arranged on the peripheral portion of the chip 1, and controls the loop shape of the wire 3 even if the electrode pads are arranged on the center of the chip 1. By doing so, it is possible to respond.

Since the exposed surface of the internal lead 4 to which the solder ball 6 is bonded is the surface of the projection 5 formed on the internal lead in advance, the exposed surface is formed simultaneously with the resin sealing. It is not necessary to perform additional processing later to form the exposed surface.

Further, since the projections 5 are formed by half etching and the thickness of the internal lead 4 having the projections is the thickness of the raw material for manufacturing the lead frame, the thickness accuracy is extremely good and the projection surfaces are parallel to each other. This has the advantage that the degree of resin burr is good and the occurrence of resin burrs during resin sealing is small.

Next, a method of manufacturing a resin-sealed semiconductor device according to one embodiment of the present invention will be described.

A lead frame similar to the conventional resin-encapsulated semiconductor device having at least internal leads is prepared, and projections are formed at predetermined positions on the internal leads. This projection
The protrusions can be formed by half-etching the internal leads other than the protrusions at the time of manufacturing the lead frame.

Next, a single-layer adhesive tape serving as an adhesive or an insulating tape of polyimide or the like having an adhesive applied to one side or an adhesive was applied to both sides of the internal lead on the side opposite to the projection-formed side. An insulating tape such as polyimide is attached via an adhesive. The thinner the adhesive is, the better
In the case of a single layer to maintain insulation, 10 to 100 μm
m, 5 to 3 when having a base tape such as polyimide
Set to 0 μm.

Next, as shown in FIG. 1, the chip is fixed to the lead frame to which the insulating tape has been attached via the adhesive 7 of the insulating tape with the surface of the chip 1 facing upward.
When an insulating tape having an adhesive applied on one side is used, there is no adhesive layer on the chip fixing surface, so that an adhesive such as Ag paste is applied on the insulating tape to fix the chip.

Next, the electrode pads of the chip 1 and the internal leads 4 are connected with the wires 3, and the whole including the chip 1 and the internal leads 4 is sealed with the resin 2 by the transfer molding method, and at the same time, the surface of the projection 5 is exposed. Let it.

Next, the semiconductor device of the present invention is completed through a stamping process, a process of attaching the solder balls 6 to the exposed protruding surfaces, a process of cutting the outer shape of the semiconductor device to separate it from the lead frame, and an electrical sorting process.

[Embodiment 2] Next, a second embodiment of the present invention will be described. FIG. 2 is a sectional view showing the configuration of the second embodiment of the present invention.

Referring to FIG. 2, in the second embodiment of the present invention, a protrusion 5 is formed on the internal lead 4 similarly to the first embodiment, and the inner lead 4 has a surface on which the protrusion is formed. The chip 1 is fixed to the opposite surface via an adhesive 7 with the element surface facing upward. The electrode pads 8 on the chip surface and the internal leads are connected by wires 3, and the entire chip 1, the internal leads 4, the wires 3, etc. are sealed with the resin 2 except for one main surface of the protrusion 5, and are exposed. A solder ball 6 is joined to one main surface of the projection 5.

Further, the tip of the internal lead 4 is fixed to the tip 1 via an adhesive at the front side, and the projection 5 is formed on the rear side. However, the lead extends upward in the middle of the internal lead. The wire 3 is bent, and the wire 3 is bonded at the other end bent upward.

The bent portion of the internal lead 4 is bent by a press die. This uses a processing method generally performed in a lead frame manufacturing method as dimple processing. The Dp processing part 9 is located outside the edge of the chip 1 and the processing depth thereof is set to about 50 μm to 500 μm.

With such a structure, when bonding the electrode pads of the chip 1 and the internal leads 4 with the wires 3, the step between the chip surface and the internal lead surface is reduced, so that the wire loop formation is stabilized. In addition, it is possible to prevent a defect that the wire 3 is short-circuited with the edge of the chip 1.

Since the semiconductor device according to the second embodiment of the present invention has the COL structure, the thickness of the adhesive for bonding the chip and the internal lead is large, and the step between the chip surface and the internal lead surface is reduced. Although it has become large and it is difficult to form a wire loop, the formation of the wire loop can be stabilized by performing Dp processing. In general, this type of semiconductor device requires a semiconductor device size close to the chip size, and the wire length needs to be reduced to about 0.5 mm, so it is particularly difficult to form a wire loop. It is important to reduce the step between the chip surface and the lead surface by the Dp processing.

Such a reduction in the level difference enables further short wire bonding and a reduction in the size of the semiconductor device.

Another problem of the resin-encapsulated semiconductor device is that the semiconductor device is warped. In general, warpage occurs due to an imbalance in the amount of resin between the upper and lower leads and the upper and lower portions of the chip. That is, since the thermal expansion coefficient of the resin is larger than that of other constituent materials, when the resin is cooled to room temperature from a state of equilibrium at a high temperature of about 170 ° C., the resin having a large thermal expansion coefficient contracts. And warpage occurs due to imbalance between the upper and lower resin amounts.

Since this type of semiconductor device is mounted via a solder ball formed on the bottom surface, there is a problem that the warpage of the semiconductor device causes a defect that the solder ball does not contact the substrate to be mounted.

In FIGS. 1 and 5, the amount of resin above the chip 1 and the amount of resin below the internal leads 3 can be made substantially equal by making the resin thicknesses above the chip and the inner leads lower.

However, on the outside of the chip edge,
Since only the internal leads 3 are present, the amount of resin in the upper part of the internal leads 3 is larger than the amount of resin in the lower part. Therefore, there is a problem that the semiconductor device is likely to be warped due to an imbalance in the amount of resin.

On the other hand, in the embodiment shown in FIG. 2, since the internal lead 3 is provided with the Dp processing portion 9 and the internal lead is bent upward, the imbalance of the resin amount in the upper and lower portions of the internal lead is reduced. As a result, there is an advantage that the warpage of the semiconductor device can be reduced.

[Embodiment 3] A third embodiment of the present invention will be described below. FIG. 3 is a sectional view showing a third embodiment of the present invention. In a third embodiment of the present invention,
As in the first and second embodiments, the chip 1 is fixed to the front side of the internal lead 3 via an adhesive 7, and the projection 5 is formed on the back side of the internal lead 3. The electrode pads 8 and the internal leads are connected by wires 3. The chip, internal leads, wires, and the like are sealed with the resin 2 except for one main surface of the protrusion 5, and a solder ball 6 is bonded to the exposed main surface of the protrusion 5.

Further, a bonding protrusion 10 is provided on the other end of the internal lead 4 opposite to the one end to which the chip 1 is fixed.
Is formed, and the wire 3 is bonded to that portion.

The projections 10 for bonding can be formed by half-etching other than the portions where the projections are formed, similarly to the projections 5 for joining the solder balls.

With such a structure, the step between the chip surface and the bonding surface of the internal lead can be reduced, and the short wire bonding and the formation of the wire loop can be stabilized. Further, by forming the bonding protrusions, the amount of resin above the internal leads can be reduced, and the imbalance in the amount of resin above and below the internal leads can be reduced, so that the warpage of the semiconductor device can be reduced. Having.

Further, in the case of the second embodiment shown in FIG. 2, since the Dp processing is performed, the Dp processing portion 9 is formed to have a diameter of about 0.1 to 0.2 mm in order to stably form. Although the minimum length is required, in the case of the third embodiment of the present invention, since the protrusion can be formed closer to the chip edge, the size of the semiconductor device can be further reduced by shortening the wire.

[0056]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that it is possible to easily cope with the case where the electrode pads are arranged on the periphery of the chip surface.

The reason is that, in the present invention, the back surface of the chip is fixed to the surface of one end of the internal lead via an adhesive, and the electrode pad on the surface of the chip is connected to the surface of the other end of the internal lead by a wire. Because it is.

A second effect of the present invention is that it is possible to form solder balls as external terminals in a lattice pattern on the bottom surface of a semiconductor device,
In addition, the exposed surface of the internal lead serving as a solder ball attachment portion can be formed simultaneously with resin sealing, thereby facilitating a manufacturing process and suppressing an increase in manufacturing cost.

The reason is that, in the present invention, a projection is formed on the back surface of the internal lead, and the resin is sealed so as to expose one main surface of the projection. This is because one main surface of the projection can be exposed and the projection can be formed at an appropriate position on the back surface of the internal lead group, so that solder balls serving as external terminals can be arranged in a grid.

A third effect of the present invention is that it is possible to stabilize the formation of a wire loop and to shorten the wire required for reducing the size of a semiconductor device.

The reason is that, in the present invention, the other end is bent upward by Dp processing or a projection is formed at the other end with respect to one end of the internal lead to which the chip is bonded, and the other end and the chip are connected to each other. This is because the electrode pad and the electrode pad are connected by a wire.

As a fourth effect of the present invention, the warpage of the semiconductor device is reduced by reducing the imbalance in the amount of resin between the upper and lower portions of the internal leads.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention;
(A) is a sectional view, and (b) is a plan view.

FIG. 2 is a sectional view showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a sectional view showing a configuration of a third exemplary embodiment of the present invention.

4A and 4B are diagrams illustrating a configuration of a conventional resin-encapsulated semiconductor device, wherein FIG. 4A is a cross-sectional view and FIG. 4B is a plan view.

5A and 5B are diagrams showing a configuration of another conventional resin-encapsulated semiconductor device, wherein FIG. 5A is a plan view and FIG. 5B is a cross-sectional view.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Chip 2 Resin 3 Wire 4 Internal lead 5 Projection 6 Solder ball 7 Adhesive 8 Electrode pad 9 Dp processing part 10 Bonding projection 12 Hole 13 Adhesive tape 14 Upper package 15 Lower package 16 External terminal

Claims (3)

[Claims] In a resin-encapsulated semiconductor device having external terminals formed in a lattice pattern on the bottom surface, a back surface of a semiconductor chip is fixed to a front surface of a group of internal leads via an adhesive, and an electrode pad on the surface of the semiconductor chip is connected to an electrode pad on the surface of the semiconductor chip. The other end surface of the internal lead group is connected with a wire, and a protrusion is formed on the back surface side of the internal lead group. At least the semiconductor chip, the internal lead group, the wire, and the like except for one main surface of the protrusion A resin ball, and a solder ball is joined to one main surface of the protrusion. 2. The semiconductor chip back surface is fixed to the front end surface of the internal lead group via an adhesive, and the internal lead group is bent upward at a position outside the semiconductor chip edge. 2. The resin-encapsulated semiconductor device according to claim 1, wherein the other end of the bent internal lead group and an electrode pad of the semiconductor chip are connected by a wire. 3. The semiconductor chip back surface is fixed to the front end surface of the internal lead group via an adhesive, and a projection is formed on the other end surface of the internal lead group. The resin-encapsulated semiconductor device according to claim 1, wherein the projection and the projection are connected by a wire.