JP3300525B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device

Info

Publication number
JP3300525B2
JP3300525B2 JP07071594A JP7071594A JP3300525B2 JP 3300525 B2 JP3300525 B2 JP 3300525B2 JP 07071594 A JP07071594 A JP 07071594A JP 7071594 A JP7071594 A JP 7071594A JP 3300525 B2 JP3300525 B2 JP 3300525B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
die
fixing member
bonding material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07071594A
Other languages
Japanese (ja)
Other versions
JPH07283248A (en
Inventor
至洋 冨田
秀之 一山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP07071594A priority Critical patent/JP3300525B2/en
Publication of JPH07283248A publication Critical patent/JPH07283248A/en
Application granted granted Critical
Publication of JP3300525B2 publication Critical patent/JP3300525B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、半導体素子とダイパ
ットまたは内部リードとを固定部材にて固定する半導体
装置および半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element and a die pad or an internal lead are fixed by a fixing member, and a method of manufacturing the semiconductor device.

【0002】[0002]

【従来の技術】図7は従来の半導体装置の構成を示す断
面図である。図において、1は半導体素子で例えばシリ
コンから成る。2はこの半導体素子1を載置するための
ダイパットで、例えば42アロイや銅合金等から成る。
3は半導体素子1とダイパット2とを固定するための固
定部材としてのダイボンド材で、例えばエポキシ樹脂を
主成分とし、フィラーとして銀粉を混成したもので成
る。尚、半導体素子1の集積回路(図示せず)によって
は、ダイパット2にてアースをとる必要がある場合があ
り、このような時は、半導体素子1とダイパット2とを
電気的に導通させるために、ダイボンド材3を、エポキ
シ樹脂に銀粉を80wt%程度混成して導電性を有した
ものとしている。
2. Description of the Related Art FIG. 7 is a sectional view showing the structure of a conventional semiconductor device. In the figure, reference numeral 1 denotes a semiconductor element made of, for example, silicon. Reference numeral 2 denotes a die pad on which the semiconductor element 1 is mounted, which is made of, for example, 42 alloy or copper alloy.
Reference numeral 3 denotes a die bonding material as a fixing member for fixing the semiconductor element 1 and the die pad 2, and is made of, for example, an epoxy resin as a main component and a mixture of silver powder as a filler. Note that, depending on the integrated circuit (not shown) of the semiconductor element 1, it may be necessary to ground the die pad 2. In such a case, it is necessary to electrically connect the semiconductor element 1 and the die pad 2. In addition, the die bonding material 3 is made of an epoxy resin mixed with about 80 wt% of silver powder to have conductivity.

【0003】4は半導体素子1と後述するリード端子と
を接続するワイヤで、例えば金あるいはアルミニウムで
成る。10は、半導体素子1上のワイヤ4を接続するた
めの電極、5は半導体素子1の電気信号をワイヤ4を介
して外部に伝達するためのリード端子で、例えば42ア
ロイや銅合金等から成る。6は半導体素子1、ダイパッ
ト2、ダイボンド材3、ワイヤ4及びリード端子5の一
部を包み込み外部の諸条件から保護するための封止部材
としてのモールド樹脂で、例えばエポキシ樹脂に60〜
70%シリカを充填したもので成る。以上のように形成
されている半導体装置に使用されている一般的な材料の
線膨張係数および縦弾性係数のそれぞれの値を図9に示
しておく。
[0003] Reference numeral 4 denotes a wire connecting the semiconductor element 1 to a lead terminal described later, which is made of, for example, gold or aluminum. Reference numeral 10 denotes an electrode for connecting the wire 4 on the semiconductor element 1, and 5 denotes a lead terminal for transmitting an electric signal of the semiconductor element 1 to the outside via the wire 4, and is made of, for example, 42 alloy or copper alloy. . Reference numeral 6 denotes a molding resin as a sealing member for enclosing a part of the semiconductor element 1, the die pad 2, the die bonding material 3, the wire 4, and the lead terminal 5 and protecting it from external conditions.
Consists of 70% silica. FIG. 9 shows the respective values of the linear expansion coefficient and the longitudinal elastic coefficient of a general material used for the semiconductor device formed as described above.

【0004】次に上記のように構成された半導体装置の
製造方法について図7及び図8にもとづいて説明する。
まず、例えばディスペンス法を用いて(他に、スタンピ
ングやスクリーン印刷などの方法もある)シリンジ7の
先端のノズル7aからダイボンド材3aをダイパット2
上に定量吐出する(図8(a))。次に、半導体素子1
をダイパット2のダイボンド材3a上の所定の位置に設
置し、コレット8にて半導体素子1を例えば50g/m
程度にて加圧しながら、ダイパット2と半導体素子
1とをダイボンド材3にて固定する(図8(b))。
Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS.
First, the die bonding material 3a is die-patched from the nozzle 7a at the tip of the syringe 7 using, for example, a dispensing method (there are other methods such as stamping and screen printing).
The fixed amount is discharged upward (FIG. 8A). Next, the semiconductor element 1
Is placed at a predetermined position on the die bonding material 3a of the die pad 2, and the semiconductor element 1 is
The die pad 2 and the semiconductor element 1 are fixed with the die bonding material 3 while pressing at about m 2 (FIG. 8B).

【0005】次に、キャピラリ9にてワイヤ4を電極1
0とリード端子5とにそれぞれ圧着する(図8
(c))。次に、図7に示すように半導体素子1、ダイ
パット2、ワイヤ4及びリード端子5の一部をモールド
樹脂6にて封止し、所望の形状に形成し、例えばプリン
ト基板等へハンダ付け等により実装する。以上のように
形成された半導体装置の動作は、外部より電気信号がリ
ード端子5に与えられ、ワイヤ4を介して半導体素子1
上の集積回路(図示せず)にこの電気信号が伝達され
る。そして、集積回路にて所定の動作(演算等)が行わ
れた後、再びワイヤ4を介してリード端子5より外部へ
電気信号が取り出される。
Next, the wire 4 is connected to the electrode 1 by the capillary 9.
0 and the lead terminals 5 respectively (FIG. 8
(C)). Next, as shown in FIG. 7, a part of the semiconductor element 1, the die pad 2, the wire 4, and the lead terminal 5 is sealed with a mold resin 6 to form a desired shape, and for example, soldering to a printed board or the like is performed. Implement by The operation of the semiconductor device formed as described above is such that an electric signal is externally applied to the lead terminal 5 and the semiconductor element 1 is connected via the wire 4.
This electrical signal is transmitted to the upper integrated circuit (not shown). After a predetermined operation (operation or the like) is performed in the integrated circuit, an electric signal is taken out from the lead terminal 5 to the outside again via the wire 4.

【0006】次いで、上記従来例と異なる半導体装置に
ついて説明する。図10は従来の半導体装置の構成を示
す断面図である。図において、上記従来の場合と同様の
部分は同一符号を付して説明を省略する。5aはリード
端子5のうちモールド樹脂6に封止されている内部リー
ド、5bはリード端子5のモールド樹脂6に封止されて
いない外部リード、11は半導体素子1と内部リード5
aとを固定するための固定部材としての例えば両面テー
プのようなものでなる接着テープである。
Next, a semiconductor device different from the conventional example will be described. FIG. 10 is a sectional view showing a configuration of a conventional semiconductor device. In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and the description is omitted. 5a is an internal lead of the lead terminal 5 sealed with the molding resin 6, 5b is an external lead not sealed with the molding resin 6 of the lead terminal 5, and 11 is the semiconductor element 1 and the internal lead 5.
The adhesive tape is, for example, a double-sided tape as a fixing member for fixing the adhesive tape a.

【0007】次に上記のように構成された半導体装置の
製造方法について図10ないし図12にもとづいて説明
する。まず、半導体素子1をトレイ12に載置させ、半
導体素子1の電極10および内部リード5aの配置を考
慮に入れて半導体素子1上の所望の箇所に接着テープ1
1を接着する(図11及び図12(a))。次に、接着
テープ11上の所定の箇所に内部リード5aを載置させ
(図12(b))、ツール13にて内部リード5a上か
ら押さえ接着テープ11にて半導体素子1と内部リード
5aとを固定する(図12(c))。
Next, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, the semiconductor element 1 is placed on the tray 12, and the adhesive tape 1 is placed at a desired position on the semiconductor element 1 in consideration of the arrangement of the electrodes 10 and the internal leads 5a of the semiconductor element 1.
1 (FIGS. 11 and 12 (a)). Next, the internal leads 5a are placed at predetermined positions on the adhesive tape 11 (FIG. 12B), and the semiconductor element 1 and the internal leads 5a are held down with the adhesive tape 11 by holding down the internal leads 5a with the tool 13. Is fixed (FIG. 12C).

【0008】次に、ワイヤ4を電極10と内部リード5
aとに接続する(図12(d))。次に、図10に示す
ように半導体素子1、ワイヤ4および内部リード5aを
モールド樹脂6にて封止し所望の形状に形成し、例えば
プリント基板等へハンダ付け等により実装する。
Next, the wire 4 is connected to the electrode 10 and the inner lead 5.
a (FIG. 12D). Next, as shown in FIG. 10, the semiconductor element 1, the wires 4, and the internal leads 5a are sealed with a mold resin 6 to form a desired shape, and are mounted on, for example, a printed board by soldering or the like.

【0009】[0009]

【発明が解決しようとする課題】従来の半導体装置は以
上のように、線膨張係数が図9に示すようにモールド樹
脂6と異なるダイボンド材3にて半導体素子1とダイパ
ット2とを固定していたり、半導体素子1と内部リード
5aとを接着テープ11で固定したりして構成されてい
るので、実装時の半導体装置をプリント基板へハンダ付
けにより取り付ける際に生じる熱により、モールド樹脂
6とダイボンド材3及び接着テープ11の間に熱応力が
発生したり、又、実装時に半導体装置の外部から侵入す
る水蒸気をダイボンド材3や接着テープ11が多く吸湿
し、半導体素子1からダイボンド材3や接着テープ11
が剥離したりし、これらに伴い、モールド樹脂6にクラ
ックが発生してワイヤ4が切断され半導体装置の信頼性
が低下するという問題点があった。
As described above, in the conventional semiconductor device, as shown in FIG. 9, the semiconductor element 1 and the die pad 2 are fixed by the die bonding material 3 different from the molding resin 6 as shown in FIG. Or the semiconductor element 1 and the internal leads 5a are fixed with an adhesive tape 11, so that the heat generated when the semiconductor device at the time of mounting is attached to a printed circuit board by soldering is used to form a die bond with the mold resin 6. A thermal stress is generated between the material 3 and the adhesive tape 11, and the die-bonding material 3 and the adhesive tape 11 absorb a large amount of water vapor that enters from the outside of the semiconductor device at the time of mounting, and the die-bonding material 3 and the adhesive Tape 11
Are peeled off, and the cracks are generated in the mold resin 6 along with these, and the wires 4 are cut, so that the reliability of the semiconductor device is reduced.

【0010】この発明は上記のような問題点を解消する
ためになされたもので、封止部材のクラックの発生を防
止して信頼性を向上させる半導体装置および半導体装置
の製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and provides a semiconductor device and a method of manufacturing a semiconductor device, in which cracks in a sealing member are prevented and reliability is improved. With the goal.

【0011】[0011]

【課題を解決するための手段】この発明の請求項に係
る半導体装置は、半導体素子と内部リードとを固定する
固定部材の線膨張係数が封止部材の線膨張係数の0.7
〜1.5倍にて成るものである。
According to a first aspect of the present invention, in a semiconductor device, a linear expansion coefficient of a fixing member for fixing a semiconductor element and an internal lead is 0.7 times a linear expansion coefficient of a sealing member.
.About.1.5 times.

【0012】又、この発明の請求項に係る半導体装置
は、請求項において、固定部材がエポキシ樹脂にシリ
カを70〜80wt%充填し、線膨張係数が10.5〜
30×10−61/℃にて成るものである。
[0012] Further, the semiconductor device according to claim 2 of the present invention resides in that in Claim 1, the securing member silica was filled 70~80Wt% epoxy resin, a linear expansion coefficient of 10.5
30 × 10 −6 1 / ° C.

【0013】又、この発明の請求項に係る半導体装置
の製造方法は、所望の厚みを有するシート状の固定部材
を内部リードと半導体素子との間の所定の箇所にはさみ
こみ、固定部材を加熱および加圧して硬化し、内部リー
ドと半導体素子とを封止部材にて封止するものである。
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-shaped fixing member having a desired thickness is inserted into a predetermined portion between the internal lead and the semiconductor element, and the fixing member is heated. Then, the inner lead and the semiconductor element are sealed with a sealing member.

【0014】[0014]

【作用】この発明の請求項1における半導体装置の固定
部材は、封止部材との熱応力を低減する。
According to the first aspect of the present invention, the fixing member of the semiconductor device reduces thermal stress with the sealing member.

【0015】又、この発明の請求項における半導体装
置の固定部材は吸湿を低減し、熱応力を低減することが
できる封止部材を容易に得る。
Further, the fixing member of the semiconductor device according to the second aspect of the present invention can easily obtain a sealing member capable of reducing moisture absorption and reducing thermal stress.

【0016】又、この発明の請求項における半導体装
置の製造方法は、所望の厚みを有するシート状の固定部
材を内部リードと半導体素子との間の所定の箇所にはさ
みこみ、固定部材を加熱および加圧して硬化し、内部リ
ードと半導体素子とを封止部材にて封止するようにした
ので、固定部材と封止部材との熱応力を低減する。
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-like fixing member having a desired thickness is inserted into a predetermined portion between the internal lead and the semiconductor element, and the fixing member is heated and heated. Since the internal leads and the semiconductor element are sealed with a sealing member by applying pressure and cured, the thermal stress between the fixing member and the sealing member is reduced.

【0017】[0017]

【実施例】実施例1. 以下、この発明の実施例を図について説明する。図1は
この発明の実施例1の半導体装置の構成を示す断面図で
ある。図において、従来の場合と同様の部分は同一符号
を付して説明を省略する。14は半導体素子1とダイパ
ット2とを固定するための固定部材としてのダイボンド
材で、例えばエポキシ樹脂にシリカを70〜80wt%
高充填させ、線膨張係数を10.5〜30×10−6
/℃としたものである。
[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 14 denotes a die bonding material as a fixing member for fixing the semiconductor element 1 and the die pad 2, for example, 70 to 80 wt% of silica in epoxy resin.
High filling, linear expansion coefficient 10.5-30 × 10 -6 1
/ ° C.

【0018】次に上記のように構成された半導体装置の
製造方法について図1ないし図3に基づいて説明する。
まず、例えばバルク状のダイボンド材14aをダイ15
に載置し(図2(a))、プランジャ16を用いてダイ
ボンド材14aを加圧、加熱することにより溶融し、こ
の際、ダイ15の底部に設けられている真空孔15aよ
りダイボンド材14a内の空気を脱泡して、例えば50
μm以下の厚みのシート状のダイボンド材14bに成形
する(図2(b))。この際、ダイボンド材14bを5
0μm以下の厚みに成形するのは、後述する仕上がり時
の厚みである20μm以下に形成しやすいようにするた
めである。次に、このダイボンド材14bを例えば機械
的または化学処理などを用いて所望の形状に加工する。
Next, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS.
First, for example, a bulk die bond material 14a is
(FIG. 2 (a)), and the die bonding material 14a is melted by pressing and heating using the plunger 16, and at this time, the die bonding material 14a is formed through a vacuum hole 15a provided at the bottom of the die 15. Degas the air inside, for example, 50
It is formed into a sheet-like die bond material 14b having a thickness of not more than μm (FIG. 2B). At this time, the die bonding material 14b is
The reason why it is formed to a thickness of 0 μm or less is to make it easy to form a thickness of 20 μm or less, which is a finished thickness described later. Next, the die bond material 14b is processed into a desired shape using, for example, a mechanical or chemical treatment.

【0019】このような工程を経て、シート状である所
望の形状のダイボンド材14bとして形成するようにし
ているのは、このダイボンド材14の粘度が従来の場合
のダイボンド材3の粘度と比較して非常に高く、流動性
が悪いので、従来使用していたディスペンス法やスタン
ピングやスクリーン印刷などの工程を用いることができ
ないためである。
The reason why the die bond material 14b having a desired shape in the form of a sheet is formed through such a process is that the viscosity of the die bond material 14 is compared with the viscosity of the die bond material 3 in the conventional case. This is because it is extremely high and the fluidity is poor, so that it is not possible to use processes such as a dispensing method, stamping, and screen printing which have been conventionally used.

【0020】次に、ダイパット2を加熱台17に載置
し、このダイパット2上の所定の位置にダイボンド材1
4bを置く(図3(a))、そして、この上の所定の位
置に半導体素子1を置く(図3(b))。次に、ダイボ
ンド材14bに、加熱台17にてダイパット2を介して
一般的にダイボンド材14bの溶融温度である例えば1
50〜200℃の熱を加え、且つ、ツール18にて半導
体素子1を介して半導体素子1などに影響を与えない例
えば30kg/mm程度の圧力を加えて溶融させ、一
般的に用いられている例えば20μm以下の厚みのダイ
ボンド材14にして固定させる(図3(c))。(尚、
この際ツール18に加熱機構を有するようにして、ツー
ル18にて半導体素子1を介してダイボンド材14bに
熱を加えるようにしてもよい。)
Next, the die pad 2 is placed on the heating table 17, and the die bonding material 1 is placed at a predetermined position on the die pad 2.
4b is placed (FIG. 3A), and the semiconductor element 1 is placed at a predetermined position thereon (FIG. 3B). Next, the heating temperature is applied to the die bonding material 14b via the die pad 2 on the heating table 17, for example, the melting temperature of the die bonding material 14b, for example, 1
It is generally used by applying a heat of 50 to 200 ° C. and applying a pressure of, for example, about 30 kg / mm 2 which does not affect the semiconductor element 1 or the like via the semiconductor element 1 by the tool 18. The die bond material 14 having a thickness of, for example, 20 μm or less is fixed (FIG. 3C). (still,
At this time, the tool 18 may be provided with a heating mechanism so that the tool 18 applies heat to the die bonding material 14b via the semiconductor element 1. )

【0021】以下、従来の場合と同様に、キャピラリ9
にてワイヤ4を電極10とリード端子5とにそれぞれ圧
着する(図3(d))。次に、図1に示すように半導体
素子1、ダイパット2、ワイヤ4及びリード端子5の一
部をモールド樹脂6にて封止し、所望の形状に形成し、
例えばプリント基板等へハンダ付け等により実装する。
Hereinafter, as in the conventional case, the capillary 9
The wire 4 is crimped to the electrode 10 and the lead terminal 5 respectively (FIG. 3D). Next, as shown in FIG. 1, a part of the semiconductor element 1, the die pad 2, the wire 4, and the lead terminal 5 are sealed with a mold resin 6 and formed into a desired shape.
For example, it is mounted on a printed circuit board or the like by soldering or the like.

【0022】上記のように構成された実施例1の半導体
装置および他にダイボンド材14より線膨張係数の高い
ダイボンド材を使用した半導体装置およびダイボンド材
14より線膨張係数の低いダイボンド材を使用した半導
体装置のクラックの発生率を比較する実験を行った。実
験条件としては温度を85℃、温度を85%RHとし、
24時間〜72時間それぞれの半導体装置を保管し、そ
の後リフローを行い(例えば、温風や熱赤外線の230
℃の雰囲気に通すこと)クラックの発生率を比較した。
以上の実験結果から、ダイボンド材14の線膨張係数が
モールド樹脂6の線膨張係数の0.7〜1.5倍の範囲
内にあれば、クラックの発生率が特に低くなることが判
明した。
The semiconductor device of the first embodiment configured as described above, a semiconductor device using a die bond material having a higher linear expansion coefficient than the die bond material 14, and a die bond material having a lower linear expansion coefficient than the die bond material 14 were used. An experiment was conducted to compare the incidence of cracks in semiconductor devices. As the experimental conditions, the temperature was 85 ° C., the temperature was 85% RH,
Each of the semiconductor devices is stored for 24 hours to 72 hours, and then reflowed (for example, a hot air or a thermal infrared ray of 230 hours).
C.) The cracking rates were compared.
From the above experimental results, it was found that when the coefficient of linear expansion of the die bond material 14 was within the range of 0.7 to 1.5 times the coefficient of linear expansion of the mold resin 6, the crack generation rate was particularly low.

【0023】実施例2. 上記実施例1では半導体素子1とダイパット2とを電気
的に導通させない場合について説明したが、実施例2で
は半導体素子1とダイパット2とを電気的に導通させる
場合について説明する。まず、上記実施例1の図2
(b)にて示したようなシート状のダイボンド材14b
を形成した後、例えば、メッキ、蒸着またはスパッタリ
ング等の方法により、ダイボンド材14bの表面を例え
ば銀、銅、アルミニウム等の金属薄膜にて覆うように
し、ダイボンド材14bに導電性を持たせる。そして以
下、上記実施例1と同様の工程を経て半導体装置を形成
する。このようにすれば、半導体素子1とダイパット2
とを電気的に導通させることができ、半導体素子1のア
ースをダイパット2にてとることができる。
Embodiment 2 FIG. In the first embodiment, the case where the semiconductor element 1 and the die pad 2 are not electrically connected is described. In the second embodiment, the case where the semiconductor element 1 and the die pad 2 are electrically connected is described. First, FIG.
Sheet-like die bonding material 14b as shown in (b)
Is formed, the surface of the die bonding material 14b is covered with a metal thin film of, for example, silver, copper, aluminum, or the like by a method such as plating, vapor deposition, or sputtering, so that the die bonding material 14b has conductivity. Thereafter, a semiconductor device is formed through the same steps as in the first embodiment. By doing so, the semiconductor element 1 and the die pad 2
Can be electrically conducted, and the semiconductor element 1 can be grounded by the die pad 2.

【0024】実施例3. 図4はこの発明の実施例3の構成を示す断面図である。
図において、上記従来の場合と同様の部分は同一符号を
付して説明を省略する。19は半導体素子1と内部リー
ド5aとを固定するための固定部材としてのダイボンド
材で、例えばエポキシ樹脂にシリカを70〜80wt%
高充填させ、線膨張係数を10.5〜30×10−6
/℃としたものである。
Embodiment 3 FIG. FIG. 4 is a sectional view showing the configuration of the third embodiment of the present invention.
In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and the description is omitted. Reference numeral 19 denotes a die bonding material as a fixing member for fixing the semiconductor element 1 and the internal lead 5a, for example, 70 to 80 wt% of silica in epoxy resin.
High filling, linear expansion coefficient 10.5-30 × 10 -6 1
/ ° C.

【0025】次に上記のように構成された半導体装置の
製造方法について図4ないし図6に基づいて説明する。
まず、上記実施例1の場合と同様の工程を経てダイボン
ド材19aを例えば50μm以下のシート状に成形し、
このダイボンド材19aを例えば機械的または化学的処
理などを用いて所望の形状に加工する。そして、従来の
場合と同様に半導体素子1をトレイ12に載置させ、加
工されたダイボンド材19aを半導体素子1上の所定の
位置に載置する(図5及び図6(a))。
Next, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS.
First, the die bonding material 19a is formed into a sheet having a size of, for example, 50 μm or less through the same process as that of the first embodiment.
The die bond material 19a is processed into a desired shape using, for example, a mechanical or chemical treatment. Then, similarly to the conventional case, the semiconductor element 1 is placed on the tray 12, and the processed die bonding material 19a is placed at a predetermined position on the semiconductor element 1 (FIGS. 5 and 6A).

【0026】次に、ダイボンド材19a上の所定の箇所
に内部リード5aを載置させ(図6(b))、加熱手段
を備えたツール20にて内部リード5aを介してダイボ
ンド材19aに、一般的にダイボンド材19aの溶融温
度である例えば150〜200℃の熱を加え、且つ、半
導体素子1などに影響を与えない例えば30kg/mm
程度の圧力を加えて溶融させ、一般的に用いられてい
る例えば20μm以下の厚みのダイボンド材19にして
固定させる(図6(c))。
Next, the internal lead 5a is placed at a predetermined position on the die bonding material 19a (FIG. 6B), and the tool 20 having a heating means is applied to the die bonding material 19a via the internal lead 5a. Generally, heat of, for example, 150 to 200 ° C., which is the melting temperature of the die bonding material 19 a, is applied, and does not affect the semiconductor element 1 or the like, for example, 30 kg / mm.
A pressure of about 2 is applied to melt and fix to a generally used die bond material 19 having a thickness of, for example, 20 μm or less (FIG. 6C).

【0027】以下、従来の場合と同様に、ワイヤ4を電
極10と内部リード5aとに接続する(図6(d))。
次に、図4に示すように半導体素子1、ワイヤ4および
内部リード5aをモールド樹脂6にて封止し所望の形状
に形成し、例えばプリント基板等へハンダ付け等により
実装する。
Subsequently, the wire 4 is connected to the electrode 10 and the internal lead 5a as in the conventional case (FIG. 6 (d)).
Next, as shown in FIG. 4, the semiconductor element 1, the wires 4 and the internal leads 5a are sealed with a mold resin 6 to form a desired shape, and are mounted on a printed circuit board or the like by soldering or the like.

【0028】上記のように構成された実施例4の半導体
装置は上記実施例1と同様のダイボンド材19にて形成
するようにしているので、上記実施例1と同様の効果を
奏することは言うまでもない。
Since the semiconductor device of the fourth embodiment configured as described above is formed using the same die bonding material 19 as that of the first embodiment, it goes without saying that the same effect as that of the first embodiment can be obtained. No.

【0029】実施例4. 上記各実施例ではモールド樹脂6の線膨張係数が15〜
20×10−61/℃の場合、ダイボンド材14および
19の一例としてエポキシ樹脂にシリカを70〜80w
t%高充填させ、線膨張係数を10.5〜30×10
−61/℃としたものを用いる例を示したけれども、こ
れに限られることなく、他のモールド樹脂を用いる場合
についても、このモールド樹脂の線膨張係数の0.7〜
1.5倍のダイボンド材を用いるようにすれば、ダイボ
ンド材の吸湿およびダイボンド材とモールド樹脂との熱
応力を低減することができるため、上記各実施例と同様
の効果を奏することは言うまでもない。
Embodiment 4 FIG. In each of the above embodiments, the linear expansion coefficient of the mold resin 6 is 15 to
In the case of 20 × 10 −6 1 / ° C., as an example of the die bonding materials 14 and 19, 70 to 80 w
t% high filling, linear expansion coefficient 10.5-30 × 10
Although an example in which the temperature is set to −6 1 / ° C. has been described, the present invention is not limited to this.
The use of a 1.5-fold die-bonding material can reduce the moisture absorption of the die-bonding material and the thermal stress between the die-bonding material and the molding resin. .

【0030】[0030]

【発明の効果】以上のように、この発明の請求項によ
れば、半導体素子と内部リードとを固定する固定部材の
線膨張係数が封止部材の線膨張係数の0.7〜1.5倍
にて成るようにしたので、封止部材のクラックの発生を
防止して信頼性を向上させる半導体装置を提供すること
ができる。
As described above, according to the first aspect of the present invention, the linear expansion coefficient of the fixing member for fixing the semiconductor element and the internal lead is 0.7 to 1.0 of the linear expansion coefficient of the sealing member. Since the ratio is made five times, it is possible to provide a semiconductor device in which cracking of the sealing member is prevented and reliability is improved.

【0031】又、この発明の請求項によれば、請求項
において、固定部材がエポキシ樹脂にシリカを70〜
80wt%充填し、線膨張係数が10.5〜30×10
−61/℃にて成るようにしたので、固定部材の吸湿性
を低減するとともに、固定部材との熱応力を低減するこ
とができる封止部材を容易に得ることが可能な半導体装
置を提供することができる。
According to the second aspect of the present invention,
1 , the fixing member is made of epoxy resin with silica of 70 to
80 wt% filling, linear expansion coefficient 10.5-30 × 10
A semiconductor device capable of easily obtaining a sealing member capable of reducing the hygroscopicity of the fixing member and reducing thermal stress with the fixing member because the temperature is set to −6 1 / ° C. can do.

【0032】又、この発明の請求項によれば、請求項
または請求項において、所望の厚みを有するシート
状の固定部材を内部リードと半導体素子との間の所定の
箇所にはさみこみ、固定部材を加熱および加圧して硬化
し、内部リードと半導体素子とを封止部材にて封止する
ようにしたので、封止部材のクラックの発生を防止して
信頼性を向上させる半導体装置の製造方法を提供するこ
とができる。
Further, according to claim 3 of the present invention, claim
In 1 or claim 2, the desired sandwiching a sheet-like fixing member having a thickness in a predetermined position between the inner leads and the semiconductor element, and curing the fixing member heated and pressurized, the internal lead and the semiconductor element Is sealed with a sealing member, so that it is possible to provide a method of manufacturing a semiconductor device in which cracking of the sealing member is prevented and reliability is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明の実施例1における半導体装置の構
成を示す断面図である。
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.

【図2】 図1に示す半導体装置の製造方法の一工程を
示す断面図である。
FIG. 2 is a sectional view showing one step of a method of manufacturing the semiconductor device shown in FIG.

【図3】 図1に示す半導体装置の製造方法の一工程を
示す断面図である。
FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device shown in FIG.

【図4】 この発明の実施例3における半導体装置の構
成を示す断面図である。
FIG. 4 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

【図5】 図4に示す半導体装置の製造方法の一工程を
示す断面図である。
5 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device shown in FIG.

【図6】 図4に示す半導体装置の製造方法の一工程を
示す断面図である。
6 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device shown in FIG.

【図7】 従来の半導体装置の構成を示す断面図であ
る。
FIG. 7 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

【図8】 図7に示す半導体装置の製造方法の工程を示
す断面図である。
8 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device shown in FIG.

【図9】 図7に示す半導体装置の材料の物性を示す図
である。
9 is a view illustrating physical properties of materials of the semiconductor device illustrated in FIG. 7;

【図10】 他の従来の半導体装置の構成を示す断面図
である。
FIG. 10 is a cross-sectional view showing a configuration of another conventional semiconductor device.

【図11】 図10に示す半導体装置の製造方法の一工
程を示す断面図である。
11 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device shown in FIG.

【図12】 図10に示す半導体装置の製造方法の一工
程を示す断面図である。
12 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device shown in FIG.

【符号の説明】[Explanation of symbols]

1 半導体素子、2 ダイパット、5 リード端子、5
a 内部リード、5b 外部リード、6 封止樹脂、1
4,14a,14b,19,19a ダイボンド材、1
5 ダイ、15a 真空孔、16 プランジャ、17
加熱台、18 ツール、20 ツール。
1 semiconductor device, 2 die pad, 5 lead terminal, 5
a internal lead, 5b external lead, 6 sealing resin, 1
4, 14a, 14b, 19, 19a Die bond material, 1
5 die, 15a vacuum hole, 16 plunger, 17
Heating table, 18 tools, 20 tools.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−235063(JP,A) 特開 平1−293640(JP,A) 特開 平1−166530(JP,A) 特開 平2−168635(JP,A) 特開 昭59−181628(JP,A) 特開 平7−288262(JP,A) 特開 昭55−130134(JP,A) 特開 平6−236899(JP,A) 特開 昭63−104455(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/52 H01L 21/58 H01L 23/28 - 23/31 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-5-235063 (JP, A) JP-A-1-293640 (JP, A) JP-A-1-166530 (JP, A) JP-A-2- 168635 (JP, A) JP-A-59-181628 (JP, A) JP-A-7-288262 (JP, A) JP-A 55-130134 (JP, A) JP-A-6-236899 (JP, A) JP-A-63-104455 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/52 H01L 21/58 H01L 23/28-23/31

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子と、内部リードと、上記半導
体素子の電極が形成されている面上であって上記電極の
近傍に上記半導体素子と上記内部リードとを固定する固
定部材と、上記半導体素子と上記内部リードとを封止す
る封止部材とを備えた半導体装置において、上記固定部
材の線膨張係数が上記封止部材の線膨張係数の0.7〜
1.5倍にて成ることを特徴とする半導体装置。
1. A semiconductor device, an internal lead, and the semiconductor
On the surface on which the electrodes of the
In a semiconductor device comprising a fixing member for fixing the semiconductor element and the internal lead in the vicinity, and a sealing member for sealing the semiconductor element and the internal lead, the linear expansion coefficient of the fixing member is 0.7 to the linear expansion coefficient of the stop member
A semiconductor device comprising 1.5 times.
【請求項2】 固定部材はエポキシ樹脂にシリカが70
〜80wt%充填され、線膨張係数が10.5〜30×
10−61/℃にて成ることを特徴とする請求項記載
の半導体装置。
2. The fixing member is made of epoxy resin containing 70% silica.
~ 80wt% filling, linear expansion coefficient 10.5-30x
2. The semiconductor device according to claim 1 , wherein the temperature is 10 −6 1 / ° C.
【請求項3】 所望の厚みを有するシート状の固定部材
を内部リードと半導体素子との間の所定の箇所にはさみ
こむ工程と、上記固定部材を加熱および加圧して硬化す
る工程と、上記内部リードと上記半導体素子とを封止部
材にて封止する工程とを備えたことを特徴とする請求項
または請求項2に記載の半導体装置の製造方法。
3. A step of inserting a sheet-shaped fixing member having a desired thickness into a predetermined position between the internal lead and the semiconductor element, a step of heating and pressurizing the fixing member, and a step of curing the internal lead. And sealing the semiconductor element with a sealing member.
The method for manufacturing a semiconductor device according to claim 1.
JP07071594A 1994-04-08 1994-04-08 Semiconductor device and method of manufacturing semiconductor device Expired - Fee Related JP3300525B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
JP07071594A JP3300525B2 (en) 1994-04-08 1994-04-08 Semiconductor device and method of manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH07283248A JPH07283248A (en) 1995-10-27
JP3300525B2 true JP3300525B2 (en) 2002-07-08

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026382B2 (en) 2002-04-24 2006-04-11 Shin-Etsu Chemical Co., Ltd. Conductive resin composition

Families Citing this family (2)

* Cited by examiner, † Cited by third party
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JPH1123613A (en) 1997-07-04 1999-01-29 Tokai Rika Co Ltd Sensor utilizing diaphragm type sensor chip
JP4537555B2 (en) * 2000-09-11 2010-09-01 新日鐵化学株式会社 Semiconductor package manufacturing method and semiconductor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026382B2 (en) 2002-04-24 2006-04-11 Shin-Etsu Chemical Co., Ltd. Conductive resin composition

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