JPH07283248A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH07283248A
JPH07283248A JP6070715A JP7071594A JPH07283248A JP H07283248 A JPH07283248 A JP H07283248A JP 6070715 A JP6070715 A JP 6070715A JP 7071594 A JP7071594 A JP 7071594A JP H07283248 A JPH07283248 A JP H07283248A
Authority
JP
Japan
Prior art keywords
semiconductor element
fixing member
semiconductor device
die pad
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6070715A
Other languages
Japanese (ja)
Other versions
JP3300525B2 (en
Inventor
Yoshihiro Tomita
至洋 冨田
Hideyuki Ichiyama
秀之 一山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP07071594A priority Critical patent/JP3300525B2/en
Publication of JPH07283248A publication Critical patent/JPH07283248A/en
Application granted granted Critical
Publication of JP3300525B2 publication Critical patent/JP3300525B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Abstract

PURPOSE:To obtain a semiconductor device enhanced in reliability by protecting a sealing member against cracking. CONSTITUTION:A semiconductor device is provided with a semiconductor element 1, a die pad 2, a die bonding material 14 used for fixing the element 1 to the die pad 2 and having a linear expansion coefficient 10.5 to 30X10<-6>1/ deg.C, and a molding resin 6 used for sealing in the semiconductor element 1 and the die pad 2 and having a linear expansion coefficient 15 to 20X10<-6>1/ deg.C.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体素子とダイパ
ットまたは内部リードとを固定部材にて固定する半導体
装置および半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element and a die pad or an internal lead are fixed by a fixing member, and a method of manufacturing the semiconductor device.

【0002】[0002]

【従来の技術】図7は従来の半導体装置の構成を示す断
面図である。図において、1は半導体素子で例えばシリ
コンから成る。2はこの半導体素子1を載置するための
ダイパットで、例えば42アロイや銅合金等から成る。
3は半導体素子1とダイパット2とを固定するための固
定部材としてのダイボンド材で、例えばエポキシ樹脂を
主成分とし、フィラーとして銀粉を混成したもので成
る。尚、半導体素子1の集積回路(図示せず)によって
は、ダイパット2にてアースをとる必要がある場合があ
り、このような時は、半導体素子1とダイパット2とを
電気的に導通させるために、ダイボンド材3を、エポキ
シ樹脂に銀粉を80wt%程度混成して導電性を有した
ものとしている。
2. Description of the Related Art FIG. 7 is a sectional view showing the structure of a conventional semiconductor device. In the figure, reference numeral 1 denotes a semiconductor element made of, for example, silicon. Reference numeral 2 is a die pad for mounting the semiconductor element 1, which is made of, for example, 42 alloy or copper alloy.
Reference numeral 3 denotes a die bonding material as a fixing member for fixing the semiconductor element 1 and the die pad 2, which is composed of, for example, an epoxy resin as a main component and a silver powder mixed as a filler. Depending on the integrated circuit (not shown) of the semiconductor element 1, it may be necessary to ground the die pad 2, and in such a case, the semiconductor element 1 and the die pad 2 are electrically connected to each other. In addition, the die bond material 3 is made to have conductivity by mixing about 80 wt% of silver powder with epoxy resin.

【0003】4は半導体素子1と後述するリード端子と
を接続するワイヤで、例えば金あるいはアルミニウムで
成る。10は、半導体素子1上のワイヤ4を接続するた
めの電極、5は半導体素子1の電気信号をワイヤ4を介
して外部に伝達するためのリード端子で、例えば42ア
ロイや銅合金等から成る。6は半導体素子1、ダイパッ
ト2、ダイボンド材3、ワイヤ4及びリード端子5の一
部を包み込み外部の諸条件から保護するための封止部材
としてのモールド樹脂で、例えばエポキシ樹脂に60〜
70%シリカを充填したもので成る。以上のように形成
されている半導体装置に使用されている一般的な材料の
線膨張係数および縦弾性係数のそれぞれの値を図9に示
しておく。
Reference numeral 4 is a wire connecting the semiconductor element 1 and a lead terminal described later, and is made of, for example, gold or aluminum. Reference numeral 10 is an electrode for connecting the wire 4 on the semiconductor element 1, and 5 is a lead terminal for transmitting an electric signal of the semiconductor element 1 to the outside through the wire 4, and is made of, for example, 42 alloy or copper alloy. . 6 is a mold resin as a sealing member for enclosing a part of the semiconductor element 1, the die pad 2, the die bond material 3, the wire 4 and the lead terminal 5 and protecting them from various external conditions.
It consists of 70% silica. FIG. 9 shows respective values of the linear expansion coefficient and the longitudinal elastic coefficient of general materials used in the semiconductor device formed as described above.

【0004】次に上記のように構成された半導体装置の
製造方法について図7及び図8にもとづいて説明する。
まず、例えばディスペンス法を用いて(他に、スタンピ
ングやスクリーン印刷などの方法もある)シリンジ7の
先端のノズル7aからダイボンド材3aをダイパット2
上に定量吐出する(図8(a))。次に、半導体素子1
をダイパット2のダイボンド材3a上の所定の位置に設
置し、コレット8にて半導体素子1を例えば50g/m
2程度にて加圧しながら、ダイパット2と半導体素子
1とをダイボンド材3にて固定する(図8(b))。
Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS.
First, the die bonding material 3a is applied from the nozzle 7a at the tip of the syringe 7 to the die pad 2 using, for example, a dispensing method (in addition, there are methods such as stamping and screen printing).
A fixed amount is discharged on the upper side (FIG. 8A). Next, the semiconductor device 1
Is placed at a predetermined position on the die-bonding material 3a of the die pad 2 and the semiconductor element 1 is collected by the collet 8 at, for example, 50 g / m.
The die pad 2 and the semiconductor element 1 are fixed to each other with the die bond material 3 while being pressurized at about m 2 (FIG. 8B).

【0005】次に、キャピラリ9にてワイヤ4を電極1
0とリード端子5とにそれぞれ圧着する(図8
(c))。次に、図7に示すように半導体素子1、ダイ
パット2、ワイヤ4及びリード端子5の一部をモールド
樹脂6にて封止し、所望の形状に形成し、例えばプリン
ト基板等へハンダ付け等により実装する。以上のように
形成された半導体装置の動作は、外部より電気信号がリ
ード端子5に与えられ、ワイヤ4を介して半導体素子1
上の集積回路(図示せず)にこの電気信号が伝達され
る。そして、集積回路にて所定の動作(演算等)が行わ
れた後、再びワイヤ4を介してリード端子5より外部へ
電気信号が取り出される。
Next, the wire 4 is connected to the electrode 1 by the capillary 9.
0 and the lead terminal 5 are crimped (see FIG. 8).
(C)). Next, as shown in FIG. 7, a part of the semiconductor element 1, the die pad 2, the wire 4 and the lead terminal 5 is sealed with a mold resin 6 to form a desired shape, and for example soldered to a printed circuit board or the like. Implemented by. In the operation of the semiconductor device formed as described above, an electric signal is externally applied to the lead terminal 5 and the semiconductor element 1 is connected via the wire 4.
This electrical signal is transmitted to the upper integrated circuit (not shown). Then, after a predetermined operation (calculation or the like) is performed in the integrated circuit, an electric signal is taken out from the lead terminal 5 to the outside again via the wire 4.

【0006】次いで、上記従来例と異なる半導体装置に
ついて説明する。図10は従来の半導体装置の構成を示
す断面図である。図において、上記従来の場合と同様の
部分は同一符号を付して説明を省略する。5aはリード
端子5のうちモールド樹脂6に封止されている内部リー
ド、5bはリード端子5のモールド樹脂6に封止されて
いない外部リード、11は半導体素子1と内部リード5
aとを固定するための固定部材としての例えば両面テー
プのようなものでなる接着テープである。
Next, a semiconductor device different from the above conventional example will be described. FIG. 10 is a sectional view showing the structure of a conventional semiconductor device. In the figure, the same parts as those in the above-mentioned conventional case are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 5a is an internal lead of the lead terminal 5 which is sealed in the mold resin 6, 5b is an external lead of the lead terminal 5 which is not sealed in the mold resin 6, and 11 is the semiconductor element 1 and the internal lead 5
It is an adhesive tape made of, for example, a double-sided tape as a fixing member for fixing a.

【0007】次に上記のように構成された半導体装置の
製造方法について図10ないし図12にもとづいて説明
する。まず、半導体素子1をトレイ12に載置させ、半
導体素子1の電極10および内部リード5aの配置を考
慮に入れて半導体素子1上の所望の箇所に接着テープ1
1を接着する(図11及び図12(a))。次に、接着
テープ11上の所定の箇所に内部リード5aを載置させ
(図12(b))、ツール13にて内部リード5a上か
ら押さえ接着テープ11にて半導体素子1と内部リード
5aとを固定する(図12(c))。
Next, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS. First, the semiconductor element 1 is placed on the tray 12, and the adhesive tape 1 is placed at a desired position on the semiconductor element 1 in consideration of the arrangement of the electrodes 10 and the internal leads 5a of the semiconductor element 1.
1 is bonded (FIGS. 11 and 12 (a)). Next, the internal lead 5a is placed at a predetermined location on the adhesive tape 11 (FIG. 12B), and the tool 13 presses the internal lead 5a from above the semiconductor chip 1 and the internal lead 5a with the adhesive tape 11. Is fixed (FIG. 12 (c)).

【0008】次に、ワイヤ4を電極10と内部リード5
aとに接続する(図12(d))。次に、図10に示す
ように半導体素子1、ワイヤ4および内部リード5aを
モールド樹脂6にて封止し所望の形状に形成し、例えば
プリント基板等へハンダ付け等により実装する。
Next, the wire 4 is connected to the electrode 10 and the inner lead 5.
It is connected to a (FIG. 12 (d)). Next, as shown in FIG. 10, the semiconductor element 1, the wires 4 and the internal leads 5a are sealed with a molding resin 6 to form a desired shape, and mounted on a printed circuit board or the like by soldering or the like.

【0009】[0009]

【発明が解決しようとする課題】従来の半導体装置は以
上のように、線膨張係数が図9に示すようにモールド樹
脂6と異なるダイボンド材3にて半導体素子1とダイパ
ット2とを固定していたり、半導体素子1と内部リード
5aとを接着テープ11で固定したりして構成されてい
るので、実装時の半導体装置をプリント基板へハンダ付
けにより取り付ける際に生じる熱により、モールド樹脂
6とダイボンド材3及び接着テープ11の間に熱応力が
発生したり、又、実装時に半導体装置の外部から侵入す
る水蒸気をダイボンド材3や接着テープ11が多く吸湿
し、半導体素子1からダイボンド材3や接着テープ11
が剥離したりし、これらに伴い、モールド樹脂6にクラ
ックが発生してワイヤ4が切断され半導体装置の信頼性
が低下するという問題点があった。
As described above, in the conventional semiconductor device, the semiconductor element 1 and the die pad 2 are fixed by the die bond material 3 having a linear expansion coefficient different from that of the mold resin 6 as shown in FIG. Alternatively, since the semiconductor element 1 and the inner leads 5a are fixed by the adhesive tape 11, the heat generated when the semiconductor device is mounted on the printed circuit board by soldering and the die resin is die-bonded to the mold resin 6. Thermal stress is generated between the material 3 and the adhesive tape 11, and the die bond material 3 and the adhesive tape 11 absorb a lot of water vapor that enters from the outside of the semiconductor device during mounting, and the semiconductor element 1 and the die bond material 3 and the adhesive tape 11 are bonded. Tape 11
However, there is a problem that the mold resin 6 is cracked and the wire 4 is cut and the reliability of the semiconductor device is deteriorated.

【0010】この発明は上記のような問題点を解消する
ためになされたもので、封止部材のクラックの発生を防
止して信頼性を向上させる半導体装置および半導体装置
の製造方法を提供することを目的とする。
The present invention has been made to solve the above problems, and provides a semiconductor device and a method for manufacturing the semiconductor device, which prevent the occurrence of cracks in the sealing member and improve reliability. With the goal.

【0011】[0011]

【課題を解決するための手段】この発明の請求項1に係
る半導体装置は、半導体素子とダイパットとを固定する
固定部材の線膨張係数が封止部材の線膨張係数の0.7
〜1.5倍にて成るものである。
In the semiconductor device according to the first aspect of the present invention, the linear expansion coefficient of the fixing member for fixing the semiconductor element and the die pad is 0.7 of the linear expansion coefficient of the sealing member.
~ 1.5 times.

【0012】又、この発明の請求項2に係る半導体装置
は、半導体素子と内部リードとを固定する固定部材の線
膨張係数が封止部材の線膨張係数の0.7〜1.5倍に
て成るものである。
Further, in the semiconductor device according to claim 2 of the present invention, the linear expansion coefficient of the fixing member for fixing the semiconductor element and the internal lead is 0.7 to 1.5 times the linear expansion coefficient of the sealing member. It consists of

【0013】又、この発明の請求項3に係る半導体装置
は、請求項1において、固定部材がエポキシ樹脂にシリ
カを70〜80wt%充填し、線膨張係数が10.5〜
30×10-61/℃にて成るものである。
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the fixing member has an epoxy resin filled with 70 to 80 wt% of silica, and a linear expansion coefficient of 10.5 to.
It is composed of 30 × 10 −6 1 / ° C.

【0014】又、この発明の請求項4に係る半導体装置
は、請求項1または請求項3において、固定部材の表面
が金属薄膜で覆われているものである。
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first or third aspect, wherein the surface of the fixing member is covered with a metal thin film.

【0015】又、この発明の請求項5に係る半導体装置
は、請求項2において、固定部材がエポキシ樹脂にシリ
カを70〜80wt%充填し、線膨張係数が10.5〜
30×10-61/℃にて成るものである。
According to a fifth aspect of the present invention, in the second aspect, the fixing member has an epoxy resin filled with silica of 70 to 80 wt% and a linear expansion coefficient of 10.5 to.
It is composed of 30 × 10 −6 1 / ° C.

【0016】又、この発明の請求項6に係る半導体装置
の製造方法は、所望の厚みを有するシート状の固定部材
をダイパットと半導体素子との間の所定の箇所にはさみ
こみ、固定部材を加熱および加圧して硬化し、ダイパッ
トと半導体素子とを封止部材にて封止するものである。
According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-shaped fixing member having a desired thickness is sandwiched at a predetermined position between the die pad and the semiconductor element, and the fixing member is heated and heated. It is pressurized and cured, and the die pad and the semiconductor element are sealed with a sealing member.

【0017】又、この発明の請求項7に係る半導体装置
の製造方法は、50μm以下の厚みを有するシート状の
固定部材をダイパットと半導体素子との間の所定の箇所
にはさみこみ、固定部材を150〜200℃に加熱およ
び30kg/mm2程度に加圧し、20μm以下の厚み
にして硬化し、ダイパットと半導体素子とを封止部材に
て封止するものである。
According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-like fixing member having a thickness of 50 μm or less is sandwiched at a predetermined position between the die pad and the semiconductor element, and the fixing member is provided at 150. It is heated to ˜200 ° C. and pressurized to about 30 kg / mm 2 , and cured to a thickness of 20 μm or less, and the die pad and the semiconductor element are sealed with a sealing member.

【0018】又、この発明の請求項8に係る半導体装置
の製造方法は、所望の厚みを有し且つ金属薄膜で表面が
覆われているシート状の固定部材をダイパットと半導体
素子との間の所定の箇所にはさみこみ、固定部材を加熱
および加圧して硬化し、ダイパットと半導体素子とを封
止部材にて封止するものである。
According to an eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a sheet-like fixing member having a desired thickness and having a surface covered with a metal thin film is provided between the die pad and the semiconductor element. It is sandwiched at a predetermined position, and the fixing member is heated and pressed to be cured, and the die pad and the semiconductor element are sealed with a sealing member.

【0019】又、この発明の請求項9に係る半導体装置
の製造方法は、50μm以下の厚みを有し且つ金属薄膜
で表面が覆われているシート状の固定部材をダイパット
と半導体素子との間の所定の箇所にはさみこみ、固定部
材を150〜200℃に加熱および30kg/mm2
度に加圧し、20μm以下の厚みにして硬化し、ダイパ
ットと半導体素子とを封止部材にて封止するものであ
る。
According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a sheet-like fixing member having a thickness of 50 μm or less and having a surface covered with a metal thin film is provided between the die pad and the semiconductor element. At a predetermined position, heat the fixing member to 150 to 200 ° C. and pressurize it to about 30 kg / mm 2 , and harden it to a thickness of 20 μm or less, and seal the die pad and the semiconductor element with a sealing member. Is.

【0020】又、この発明の請求項10に係る半導体装
置の製造方法は、所望の厚みを有するシート状の固定部
材を内部リードと半導体素子との間の所定の箇所にはさ
みこみ、固定部材を加熱および加圧して硬化し、内部リ
ードと半導体素子とを封止部材にて封止するものであ
る。
According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-like fixing member having a desired thickness is sandwiched at a predetermined position between the inner lead and the semiconductor element, and the fixing member is heated. Then, the inner lead and the semiconductor element are sealed with a sealing member by applying pressure and curing.

【0021】又、この発明の請求項11に係る半導体装
置の製造方法は、50μm以下の厚みを有するシート状
の固定部材を内部リードと半導体素子との間の所定の箇
所にはさみこみ、固定部材を150〜200℃に加熱お
よび30kg/mm2程度に加圧し、20μm以下の厚
みにして硬化し、内部リードと半導体素子とを封止部材
にて封止するものである。
According to the eleventh aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-like fixing member having a thickness of 50 μm or less is sandwiched at a predetermined position between the inner lead and the semiconductor element, and the fixing member is attached. It is heated to 150 to 200 ° C. and pressurized to about 30 kg / mm 2 , and cured to a thickness of 20 μm or less, and then the internal lead and the semiconductor element are sealed with a sealing member.

【0022】[0022]

【作用】この発明の請求項1における半導体装置の固定
部材は、封止部材との熱応力を低減する。
The fixing member for a semiconductor device according to claim 1 of the present invention reduces thermal stress with the sealing member.

【0023】又、この発明の請求項2における半導体装
置の固定部材は、封止部材との熱応力を低減する。
The fixing member of the semiconductor device according to the second aspect of the present invention reduces the thermal stress with the sealing member.

【0024】又、この発明の請求項3における半導体装
置の固定部材は吸湿を低減し、熱応力を低減することが
できる封止部材を容易に得る。
Further, the fixing member of the semiconductor device according to claim 3 of the present invention can easily obtain a sealing member which can reduce moisture absorption and thermal stress.

【0025】又、この発明の請求項4における半導体装
置の固定部材は半導体素子とダイパットとを電気的に導
通させる。
Further, the fixing member of the semiconductor device according to the fourth aspect of the present invention electrically connects the semiconductor element and the die pad.

【0026】又、この発明の請求項5における半導体装
置の固定部材は吸湿を低減し、熱応力を低減することが
できる封止部材を容易に得る。
Further, the fixing member of the semiconductor device according to the fifth aspect of the present invention can easily obtain the sealing member which can reduce moisture absorption and thermal stress.

【0027】又、この発明の請求項6における半導体装
置の製造方法は、所望の厚みを有するシート状の固定部
材をダイパットと半導体素子との間の所定の箇所にはさ
み固定部材を加熱および加圧して硬化し、ダイパットと
半導体素子とを封止部材にて封止するようにしたので、
固定部材と封止部材との熱応力を低減する。
According to a sixth aspect of the present invention, in the method for manufacturing a semiconductor device, a sheet-like fixing member having a desired thickness is sandwiched between a die pad and a semiconductor element at a predetermined position, and the fixing member is heated and pressurized. Since it is cured by sealing the die pad and the semiconductor element with a sealing member,
The thermal stress between the fixing member and the sealing member is reduced.

【0028】又、この発明の請求項7における半導体装
置の製造方法は、50μm以下の厚みを有するシート状
の固定部材をダイパットと半導体素子との間の所定の箇
所にはさみこみ、固定部材を150〜200℃に加熱お
よび30kg/mm2程度に加圧し、20μm以下の厚
みにして硬化し、ダイパットと半導体素子とを封止部材
にて封止するようにしたので、固定部材と封止部材との
熱応力を低減する。
According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor device, a sheet-like fixing member having a thickness of 50 μm or less is sandwiched at a predetermined position between the die pad and the semiconductor element, and the fixing member is 150 to 150 μm thick. Since it is heated to 200 ° C. and pressurized to about 30 kg / mm 2 and cured to a thickness of 20 μm or less and the die pad and the semiconductor element are sealed with the sealing member, the fixing member and the sealing member are separated from each other. Reduce thermal stress.

【0029】又、この発明の請求項8における半導体装
置の製造方法は、所望の厚みを有し且つ金属薄膜で表面
が覆われているシート状の固定部材をダイパットと半導
体素子との間の所定の箇所にはさみこみ、固定部材を加
熱および加圧して硬化し、ダイパットと半導体素子とを
封止部材にて封止するようにしたので、固定部材と封止
部材との熱応力を低減するとともに、半導体素子とダイ
パットとを電気的に導通する。
In the method for manufacturing a semiconductor device according to the eighth aspect of the present invention, a sheet-like fixing member having a desired thickness and having a surface covered with a metal thin film is provided between the die pad and the semiconductor element. In place of, the fixing member is heated and pressurized to be cured, so that the die pad and the semiconductor element are sealed by the sealing member, so that the thermal stress between the fixing member and the sealing member is reduced, The semiconductor element and the die pad are electrically connected.

【0030】又、この発明の請求項9における半導体装
置の製造方法は、50μm以下の厚みを有し且つ金属薄
膜で表面が覆われているシート状の固定部材をダイパッ
トと半導体素子との間の所定の箇所にはさみこみ、固定
部材を150〜200℃に加熱および30kg/mm2
程度に加圧し、20μm以下の厚みにして硬化し、ダイ
パットと半導体素子とを封止部材にて封止するようにし
たので、固定部材と封止部材との熱応力を低減するとと
もに、半導体素子とダイパットとを電気的に導通する。
According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a sheet-like fixing member having a thickness of 50 μm or less and having a surface covered with a metal thin film is provided between the die pad and the semiconductor element. Scissors at a specified location, heat the fixing member to 150 to 200 ° C, and 30 kg / mm 2
The die pad and the semiconductor element are sealed with the sealing member after being pressed to a certain degree and cured to a thickness of 20 μm or less, so that the thermal stress between the fixing member and the sealing member is reduced, and the semiconductor element is reduced. And the die pad are electrically connected.

【0031】又、この発明の請求項10における半導体
装置の製造方法は、所望の厚みを有するシート状の固定
部材を内部リードと半導体素子との間の所定の箇所には
さみこみ、固定部材を加熱および加圧して硬化し、内部
リードと半導体素子とを封止部材にて封止するようにし
たので、固定部材と封止部材との熱応力を低減する。
According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device, a sheet-shaped fixing member having a desired thickness is sandwiched between predetermined positions between the inner lead and the semiconductor element, and the fixing member is heated and heated. Since the internal lead and the semiconductor element are sealed by the sealing member by being pressed and cured, the thermal stress between the fixing member and the sealing member is reduced.

【0032】又、この発明の請求項11における半導体
装置の製造方法は、50μm以下の厚みを有するシート
状の固定部材を内部リードと半導体素子との間の所定の
箇所にはさみこみ、固定部材を150〜200℃に加熱
および30kg/mm2程度に加圧し、20μm以下の
厚みにして硬化し、内部リードと半導体素子とを封止部
材にて封止するようにしたので、固定部材と封止部材と
の熱応力を低減する。
According to the eleventh aspect of the present invention, in the method for manufacturing a semiconductor device, a sheet-like fixing member having a thickness of 50 μm or less is sandwiched at a predetermined position between the inner lead and the semiconductor element, and the fixing member is made 150 Since the internal lead and the semiconductor element are sealed with the sealing member, the fixing member and the sealing member are heated to 200 ° C. and pressurized to about 30 kg / mm 2 and cured to a thickness of 20 μm or less. And reduce thermal stress.

【0033】[0033]

【実施例】【Example】

実施例1.以下、この発明の実施例を図について説明す
る。図1はこの発明の実施例1の半導体装置の構成を示
す断面図である。図において、従来の場合と同様の部分
は同一符号を付して説明を省略する。14は半導体素子
1とダイパット2とを固定するための固定部材としての
ダイボンド材で、例えばエポキシ樹脂にシリカを70〜
80wt%高充填させ、線膨張係数を10.5〜30×
10-61/℃としたものである。
Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. In the figure, the same parts as those in the conventional case are designated by the same reference numerals, and the description thereof will be omitted. Reference numeral 14 is a die bond material as a fixing member for fixing the semiconductor element 1 and the die pad 2, for example, epoxy resin containing silica of 70 to 70.
80 wt% high filling and linear expansion coefficient of 10.5 to 30 ×
It is 10 −6 1 / ° C.

【0034】次に上記のように構成された半導体装置の
製造方法について図1ないし図3に基づいて説明する。
まず、例えばバルク状のダイボンド材14aをダイ15
に載置し(図2(a))、プランジャ16を用いてダイ
ボンド材14aを加圧、加熱することにより溶融し、こ
の際、ダイ15の底部に設けられている真空孔15aよ
りダイボンド材14a内の空気を脱泡して、例えば50
μm以下の厚みのシート状のダイボンド材14bに成形
する(図2(b))。この際、ダイボンド材14bを5
0μm以下の厚みに成形するのは、後述する仕上がり時
の厚みである20μm以下に形成しやすいようにするた
めである。次に、このダイボンド材14bを例えば機械
的または化学処理などを用いて所望の形状に加工する。
Next, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS.
First, for example, the bulk die bond material 14a is applied to the die 15
(FIG. 2A), the die bond material 14a is melted by pressurizing and heating it with the plunger 16, and at this time, the die bond material 14a is supplied through the vacuum hole 15a provided at the bottom of the die 15. Degas the air inside, for example 50
It is formed into a sheet-shaped die bond material 14b having a thickness of not more than μm (FIG. 2B). At this time, the die bond material 14b is 5
The reason why it is formed to a thickness of 0 μm or less is to facilitate the formation to a thickness of 20 μm or less, which is the thickness at the time of finishing described later. Next, the die bond material 14b is processed into a desired shape by using, for example, mechanical or chemical treatment.

【0035】このような工程を経て、シート状である所
望の形状のダイボンド材14bとして形成するようにし
ているのは、このダイボンド材14の粘度が従来の場合
のダイボンド材3の粘度と比較して非常に高く、流動性
が悪いので、従来使用していたディスペンス法やスタン
ピングやスクリーン印刷などの工程を用いることができ
ないためである。
The die-bonding material 14b having a desired sheet-like shape is formed through these steps in comparison with the viscosity of the die-bonding material 3 in the conventional case. This is because it is very high and the fluidity is poor, so that the conventionally used processes such as the dispensing method, stamping and screen printing cannot be used.

【0036】次に、ダイパット2を加熱台17に載置
し、このダイパット2上の所定の位置にダイボンド材1
4bを置く(図3(a))、そして、この上の所定の位
置に半導体素子1を置く(図3(b))。次に、ダイボ
ンド材14bに、加熱台17にてダイパット2を介して
一般的にダイボンド材14bの溶融温度である例えば1
50〜200℃の熱を加え、且つ、ツール18にて半導
体素子1を介して半導体素子1などに影響を与えない例
えば30kg/mm2程度の圧力を加えて溶融させ、一
般的に用いられている例えば20μm以下の厚みのダイ
ボンド材14にして固定させる(図3(c))。(尚、
この際ツール18に加熱機構を有するようにして、ツー
ル18にて半導体素子1を介してダイボンド材14bに
熱を加えるようにしてもよい。)
Next, the die pad 2 is placed on the heating table 17, and the die bond material 1 is placed at a predetermined position on the die pad 2.
4b is placed (FIG. 3A), and the semiconductor element 1 is placed at a predetermined position on this (FIG. 3B). Next, the die bonding material 14b is melted on the heating table 17 via the die pad 2 and is generally the melting temperature of the die bonding material 14b, for example, 1
It is generally used by applying a heat of 50 to 200 ° C. and melting by applying a pressure of about 30 kg / mm 2 which does not affect the semiconductor element 1 and the like via the tool 18 with the tool 18. The die-bonding material 14 having a thickness of, for example, 20 μm or less is formed and fixed (FIG. 3C). (still,
At this time, the tool 18 may be provided with a heating mechanism so that the tool 18 heats the die bond material 14b through the semiconductor element 1. )

【0037】以下、従来の場合と同様に、キャピラリ9
にてワイヤ4を電極10とリード端子5とにそれぞれ圧
着する(図3(d))。次に、図1に示すように半導体
素子1、ダイパット2、ワイヤ4及びリード端子5の一
部をモールド樹脂6にて封止し、所望の形状に形成し、
例えばプリント基板等へハンダ付け等により実装する。
Thereafter, as in the conventional case, the capillary 9
Then, the wire 4 is crimped to the electrode 10 and the lead terminal 5 respectively (FIG. 3 (d)). Next, as shown in FIG. 1, a part of the semiconductor element 1, the die pad 2, the wire 4 and the lead terminal 5 is sealed with a mold resin 6 to form a desired shape,
For example, it is mounted on a printed circuit board or the like by soldering or the like.

【0038】上記のように構成された実施例1の半導体
装置および他にダイボンド材14より線膨張係数の高い
ダイボンド材を使用した半導体装置およびダイボンド材
14より線膨張係数の低いダイボンド材を使用した半導
体装置のクラックの発生率を比較する実験を行った。実
験条件としては温度を85℃、温度を85%RHとし、
24時間〜72時間それぞれの半導体装置を保管し、そ
の後リフローを行い(例えば、温風や熱赤外線の230
℃の雰囲気に通すこと)クラックの発生率を比較した。
以上の実験結果から、ダイボンド材14の線膨張係数が
モールド樹脂6の線膨張係数の0.7〜1.5倍の範囲
内にあれば、クラックの発生率が特に低くなることが判
明した。
The semiconductor device of Example 1 configured as described above and the semiconductor device using a die bond material having a higher linear expansion coefficient than the die bond material 14 and the die bond material having a lower linear expansion coefficient than the die bond material 14 were used. An experiment was conducted to compare the crack generation rates of semiconductor devices. The experimental conditions are a temperature of 85 ° C. and a temperature of 85% RH.
Each semiconductor device is stored for 24 hours to 72 hours and then reflowed (for example, hot air or thermal infrared rays 230
Passing through an atmosphere of ° C) The occurrence rates of cracks were compared.
From the above experimental results, it was found that the crack generation rate was particularly low when the linear expansion coefficient of the die bond material 14 was within the range of 0.7 to 1.5 times the linear expansion coefficient of the mold resin 6.

【0039】実施例2.上記実施例1では半導体素子1
とダイパット2とを電気的に導通させない場合について
説明したが、実施例2では半導体素子1とダイパット2
とを電気的に導通させる場合について説明する。まず、
上記実施例1の図2(b)にて示したようなシート状の
ダイボンド材14bを形成した後、例えば、メッキ、蒸
着またはスパッタリング等の方法により、ダイボンド材
14bの表面を例えば銀、銅、アルミニウム等の金属薄
膜にて覆うようにし、ダイボンド材14bに導電性を持
たせる。そして以下、上記実施例1と同様の工程を経て
半導体装置を形成する。このようにすれば、半導体素子
1とダイパット2とを電気的に導通させることができ、
半導体素子1のアースをダイパット2にてとることがで
きる。
Example 2. In the first embodiment, the semiconductor device 1
The case where the electrical connection between the die pad 2 and the die pad 2 is not described, but in the second embodiment, the semiconductor element 1 and the die pad 2 are connected.
The case of electrically connecting and will be described. First,
After forming the sheet-shaped die bond material 14b as shown in FIG. 2B of Example 1, the surface of the die bond material 14b is formed of, for example, silver, copper, or the like by a method such as plating, vapor deposition or sputtering. The die bond material 14b is made conductive by covering it with a metal thin film such as aluminum. Then, the semiconductor device is formed through the same steps as those in the first embodiment. With this configuration, the semiconductor element 1 and the die pad 2 can be electrically connected to each other,
The semiconductor device 1 can be grounded by the die pad 2.

【0040】実施例3.図4はこの発明の実施例3の構
成を示す断面図である。図において、上記従来の場合と
同様の部分は同一符号を付して説明を省略する。19は
半導体素子1と内部リード5aとを固定するための固定
部材としてのダイボンド材で、例えばエポキシ樹脂にシ
リカを70〜80wt%高充填させ、線膨張係数を1
0.5〜30×10-61/℃としたものである。
Example 3. FIG. 4 is a sectional view showing the structure of the third embodiment of the present invention. In the figure, the same parts as those in the above-mentioned conventional case are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 19 denotes a die bond material as a fixing member for fixing the semiconductor element 1 and the internal lead 5a. For example, epoxy resin is highly filled with silica in an amount of 70 to 80 wt% and the linear expansion coefficient is 1.
It is 0.5 to 30 × 10 −6 1 / ° C.

【0041】次に上記のように構成された半導体装置の
製造方法について図4ないし図6に基づいて説明する。
まず、上記実施例1の場合と同様の工程を経てダイボン
ド材19aを例えば50μm以下のシート状に成形し、
このダイボンド材19aを例えば機械的または化学的処
理などを用いて所望の形状に加工する。そして、従来の
場合と同様に半導体素子1をトレイ12に載置させ、加
工されたダイボンド材19aを半導体素子1上の所定の
位置に載置する(図5及び図6(a))。
Next, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS.
First, the die-bonding material 19a is molded into a sheet having a size of, for example, 50 μm or less through the same steps as in the case of the above-described Example 1.
The die bond material 19a is processed into a desired shape by using, for example, mechanical or chemical treatment. Then, as in the conventional case, the semiconductor element 1 is placed on the tray 12, and the processed die bonding material 19a is placed at a predetermined position on the semiconductor element 1 (FIGS. 5 and 6 (a)).

【0042】次に、ダイボンド材19a上の所定の箇所
に内部リード5aを載置させ(図6(b))、加熱手段
を備えたツール20にて内部リード5aを介してダイボ
ンド材19aに、一般的にダイボンド材19aの溶融温
度である例えば150〜200℃の熱を加え、且つ、半
導体素子1などに影響を与えない例えば30kg/mm
2程度の圧力を加えて溶融させ、一般的に用いられてい
る例えば20μm以下の厚みのダイボンド材19にして
固定させる(図6(c))。
Next, the internal lead 5a is placed at a predetermined position on the die bond material 19a (FIG. 6 (b)), and the tool 20 having a heating means is used to attach the internal lead 5a to the die bond material 19a via the internal lead 5a. Generally, a heat of 150 to 200 ° C., which is the melting temperature of the die bonding material 19a, is applied, and the semiconductor element 1 or the like is not affected, for example, 30 kg / mm.
A pressure of about 2 is applied to melt it, and the die-bonding material 19 having a thickness of, for example, 20 μm or less which is generally used is fixed (FIG. 6C).

【0043】以下、従来の場合と同様に、ワイヤ4を電
極10と内部リード5aとに接続する(図6(d))。
次に、図4に示すように半導体素子1、ワイヤ4および
内部リード5aをモールド樹脂6にて封止し所望の形状
に形成し、例えばプリント基板等へハンダ付け等により
実装する。
Thereafter, the wire 4 is connected to the electrode 10 and the internal lead 5a as in the conventional case (FIG. 6 (d)).
Next, as shown in FIG. 4, the semiconductor element 1, the wires 4 and the inner leads 5a are sealed with a molding resin 6 to form a desired shape, and mounted on a printed circuit board or the like by soldering or the like.

【0044】上記のように構成された実施例4の半導体
装置は上記実施例1と同様のダイボンド材19にて形成
するようにしているので、上記実施例1と同様の効果を
奏することは言うまでもない。
Since the semiconductor device of the fourth embodiment configured as described above is formed by the same die bond material 19 as that of the first embodiment, it goes without saying that the same effects as those of the first embodiment can be obtained. Yes.

【0045】実施例4.上記各実施例ではモールド樹脂
6の線膨張係数が15〜20×10-61/℃の場合、ダ
イボンド材14および19の一例としてエポキシ樹脂に
シリカを70〜80wt%高充填させ、線膨張係数を1
0.5〜30×10-61/℃としたものを用いる例を示
したけれども、これに限られることなく、他のモールド
樹脂を用いる場合についても、このモールド樹脂の線膨
張係数の0.7〜1.5倍のダイボンド材を用いるよう
にすれば、ダイボンド材の吸湿およびダイボンド材とモ
ールド樹脂との熱応力を低減することができるため、上
記各実施例と同様の効果を奏することは言うまでもな
い。
Example 4. In each of the above examples, when the linear expansion coefficient of the mold resin 6 is 15 to 20 × 10 −6 1 / ° C., the epoxy resin is highly filled with silica at 70 to 80 wt% as an example of the die bonding materials 14 and 19, and the linear expansion coefficient is 1
Although an example of using the resin of 0.5 to 30 × 10 −6 1 / ° C. is shown, the invention is not limited to this, and when the other molding resin is used, the linear expansion coefficient of the molding resin of 0. By using a die bond material of 7 to 1.5 times, the moisture absorption of the die bond material and the thermal stress between the die bond material and the mold resin can be reduced, so that the same effect as each of the above-described examples can be obtained. Needless to say.

【0046】[0046]

【発明の効果】以上のように、この発明の請求項1によ
れば、半導体素子とダイパットとを固定する固定部材の
線膨張係数が封止部材の線膨張係数の0.7〜1.5倍
にて成るようにしたので、封止部材のクラックの発生を
防止して信頼性を向上させる半導体装置を提供すること
ができる。
As described above, according to claim 1 of the present invention, the linear expansion coefficient of the fixing member for fixing the semiconductor element and the die pad is 0.7 to 1.5 of the linear expansion coefficient of the sealing member. Since it is doubled, it is possible to provide a semiconductor device in which cracking of the sealing member is prevented and reliability is improved.

【0047】又、この発明の請求項2によれば、半導体
素子と内部リードとを固定する固定部材の線膨張係数が
封止部材の線膨張係数の0.7〜1.5倍にて成るよう
にしたので、封止部材のクラックの発生を防止して信頼
性を向上させる半導体装置を提供することができる。
According to claim 2 of the present invention, the linear expansion coefficient of the fixing member for fixing the semiconductor element and the internal lead is 0.7 to 1.5 times the linear expansion coefficient of the sealing member. As a result, it is possible to provide a semiconductor device that improves the reliability by preventing the occurrence of cracks in the sealing member.

【0048】又、この発明の請求項3によれば、請求項
1において、固定部材がエポキシ樹脂にシリカを70〜
80wt%充填し、線膨張係数が10.5〜30×10
-61/℃にて成るようにしたので、固定部材の吸湿性を
低減するとともに、固定部材との熱応力を低減すること
ができる封止部材を容易に得ることが可能な半導体装置
を提供することができる。
According to a third aspect of the present invention, in the first aspect, the fixing member comprises an epoxy resin containing 70 to 70% silica.
80 wt% filling and linear expansion coefficient of 10.5 to 30 × 10
Since the temperature is set to -6 1 / ° C, it is possible to easily obtain a sealing member that can reduce the hygroscopicity of the fixing member and the thermal stress with the fixing member. can do.

【0049】又、この発明の請求項4によれば、請求項
1または請求項3において、固定部材の表面が金属薄膜
で覆われているようにしたので、半導体素子のアースを
固定部材を介してダイパットにとる半導体装置を提供す
ることができる。
According to a fourth aspect of the present invention, in the first or third aspect, the surface of the fixing member is covered with the metal thin film, so that the semiconductor element is grounded through the fixing member. It is possible to provide a semiconductor device that can be used as a die pad.

【0050】又、この発明の請求項5によれば、請求項
2において、固定部材がエポキシ樹脂にシリカを70〜
80wt%充填し、線膨張係数が10.5〜30×10
-61/℃にて成るようにしたので、固定部材の吸湿性を
低減するとともに、固定部材との熱応力を低減すること
ができる封止部材を容易に得ることが可能な半導体装置
を提供することができる。
According to a fifth aspect of the present invention, in the second aspect, the fixing member is made of epoxy resin containing silica of 70 to 70%.
80 wt% filling and linear expansion coefficient of 10.5 to 30 × 10
Since the temperature is set to -6 1 / ° C, it is possible to easily obtain a sealing member that can reduce the hygroscopicity of the fixing member and the thermal stress with the fixing member. can do.

【0051】又、この発明の請求項6によれば、請求項
1または請求項3において、所望の厚みを有するシート
状の固定部材をダイパットと半導体素子との間の所定の
箇所にはさみこみ、固定部材を加熱および加圧して硬化
し、ダイパットと半導体素子とを封止部材にて封止する
ようにしたので、封止部材のクラックの発生を防止して
信頼性を向上させる半導体装置の製造方法を提供するこ
とができる。
According to a sixth aspect of the present invention, in the first or third aspect, a sheet-like fixing member having a desired thickness is sandwiched and fixed at a predetermined position between the die pad and the semiconductor element. Since the member is heated and pressed to be cured and the die pad and the semiconductor element are sealed with the sealing member, a method of manufacturing a semiconductor device in which cracking of the sealing member is prevented and reliability is improved. Can be provided.

【0052】又、この発明の請求項7によれば、請求項
1または請求項3において、50μm以下の厚みを有す
るシート状の固定部材をダイパットと半導体素子との間
の所定の箇所にはさみこみ、固定部材を150〜200
℃に加熱および30kg/mm2程度に加圧し、20μ
m以下の厚みにして硬化し、ダイパットと半導体素子と
を封止部材にて封止するようにしたので、封止部材のク
ラックの発生を防止して信頼性を向上させる半導体装置
の製造方法を提供することができる。
According to a seventh aspect of the present invention, in the first or third aspect, a sheet-like fixing member having a thickness of 50 μm or less is sandwiched at a predetermined position between the die pad and the semiconductor element, Fixing member 150-200
Heated to ℃ and pressurized to about 30kg / mm 2 , 20μ
Since the die pad and the semiconductor element are cured with a thickness of m or less and sealed with a sealing member, a method of manufacturing a semiconductor device that prevents cracks in the sealing member and improves reliability is provided. Can be provided.

【0053】又、この発明の請求項8によれば、請求項
4において、所望の厚みを有し且つ金属薄膜で表面が覆
われているシート状の固定部材をダイパットと半導体素
子との間の所定の箇所にはさみこみ、固定部材を加熱お
よび加圧して硬化し、ダイパットと半導体素子とを封止
部材にて封止するようにしたので、封止部材のクラック
の発生を防止して信頼性を向上させるとともに、半導体
素子のアースを固定部材を介してダイパットにとる半導
体装置の製造方法を提供することができる。
According to an eighth aspect of the present invention, in the fourth aspect, a sheet-like fixing member having a desired thickness and having a surface covered with a metal thin film is provided between the die pad and the semiconductor element. It is pinched in a predetermined place, the fixing member is heated and pressed to cure, and the die pad and the semiconductor element are sealed with the sealing member, so that cracking of the sealing member is prevented and reliability is improved. It is possible to provide a method for manufacturing a semiconductor device that improves and grounds a semiconductor element to a die pad through a fixing member.

【0054】又、この発明の請求項9によれば、請求項
4において、50μm以下の厚みを有し且つ金属薄膜で
表面が覆われているシート状の固定部材をダイパットと
半導体素子との間の所定の箇所にはさみこみ、固定部材
を150〜200℃に加熱および30kg/mm2程度
に加圧し、20μm以下の厚みにして硬化し、ダイパッ
トと半導体素子とを封止部材にて封止するようにしたの
で、封止部材のクラックの発生を防止して信頼性を向上
させるとともに、半導体素子のアースを固定部材を介し
てダイパットにとる半導体装置の製造方法を提供するこ
とができる。
According to a ninth aspect of the present invention, in the fourth aspect, a sheet-like fixing member having a thickness of 50 μm or less and having a surface covered with a metal thin film is provided between the die pad and the semiconductor element. At a predetermined position, heat the fixing member to 150 to 200 ° C. and pressurize it to about 30 kg / mm 2 , and harden it to a thickness of 20 μm or less to seal the die pad and the semiconductor element with a sealing member. Therefore, it is possible to provide a method for manufacturing a semiconductor device in which cracking of the sealing member is prevented, reliability is improved, and the ground of the semiconductor element is grounded to the die pad through the fixing member.

【0055】又、この発明の請求項10によれば、請求
項2または請求項5において、所望の厚みを有するシー
ト状の固定部材を内部リードと半導体素子との間の所定
の箇所にはさみこみ、固定部材を加熱および加圧して硬
化し、内部リードと半導体素子とを封止部材にて封止す
るようにしたので、封止部材のクラックの発生を防止し
て信頼性を向上させる半導体装置の製造方法を提供する
ことができる。
According to a tenth aspect of the present invention, in the second or fifth aspect, a sheet-like fixing member having a desired thickness is sandwiched at a predetermined position between the inner lead and the semiconductor element, Since the fixing member is heated and pressed to be cured and the inner lead and the semiconductor element are sealed by the sealing member, a crack of the sealing member is prevented from occurring and the reliability of the semiconductor device is improved. A manufacturing method can be provided.

【0056】又、この発明の請求項11によれば、50
μm以下の厚みを有するシート状の固定部材を内部リー
ドと半導体素子との間の所定の箇所にはさみこみ、固定
部材を150〜200℃に加熱および30kg/mm2
程度に加圧し、20μm以下の厚みにして硬化し、内部
リードと半導体素子とを封止部材にて封止するようにし
たので、封止部材のクラックの発生を防止して信頼性を
向上させる半導体装置の製造方法を提供することができ
る。
According to claim 11 of the present invention, 50
A sheet-shaped fixing member having a thickness of less than or equal to μm is sandwiched at a predetermined position between the internal lead and the semiconductor element, and the fixing member is heated to 150 to 200 ° C. and 30 kg / mm 2
Since the internal lead and the semiconductor element are sealed with the sealing member after being pressed to a certain degree and cured to a thickness of 20 μm or less, cracking of the sealing member is prevented and reliability is improved. A method for manufacturing a semiconductor device can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の実施例1における半導体装置の構
成を示す断面図である。
FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

【図2】 図1に示す半導体装置の製造方法の一工程を
示す断面図である。
FIG. 2 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIG.

【図3】 図1に示す半導体装置の製造方法の一工程を
示す断面図である。
3 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device shown in FIG.

【図4】 この発明の実施例3における半導体装置の構
成を示す断面図である。
FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

【図5】 図4に示す半導体装置の製造方法の一工程を
示す断面図である。
5 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device shown in FIG.

【図6】 図4に示す半導体装置の製造方法の一工程を
示す断面図である。
6 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device shown in FIG.

【図7】 従来の半導体装置の構成を示す断面図であ
る。
FIG. 7 is a sectional view showing a configuration of a conventional semiconductor device.

【図8】 図7に示す半導体装置の製造方法の工程を示
す断面図である。
FIG. 8 is a cross-sectional view showing a step in a method of manufacturing the semiconductor device shown in FIG.

【図9】 図7に示す半導体装置の材料の物性を示す図
である。
9 is a diagram showing physical properties of materials of the semiconductor device shown in FIG.

【図10】 他の従来の半導体装置の構成を示す断面図
である。
FIG. 10 is a cross-sectional view showing the configuration of another conventional semiconductor device.

【図11】 図10に示す半導体装置の製造方法の一工
程を示す断面図である。
11 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIG.

【図12】 図10に示す半導体装置の製造方法の一工
程を示す断面図である。
12 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIG.

【符号の説明】[Explanation of symbols]

1 半導体素子、2 ダイパット、5 リード端子、5
a 内部リード、5b外部リード、6 封止樹脂、1
4,14a,14b,19,19a ダイボンド材、1
5 ダイ、15a 真空孔、16 プランジャ、17
加熱台、18ツール、20 ツール。
1 semiconductor element, 2 die pad, 5 lead terminal, 5
a inner lead, 5b outer lead, 6 sealing resin, 1
4,14a, 14b, 19,19a Die bond material, 1
5 die, 15a vacuum hole, 16 plunger, 17
Heating table, 18 tools, 20 tools.

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、ダイパットと、上記半導
体素子と上記ダイパットとを固定する固定部材と、上記
半導体素子と上記ダイパットとを封止する封止部材とを
備えた半導体装置において、上記固定部材の線膨張係数
が上記封止部材の線膨張係数の0.7〜1.5倍にて成
ることを特徴とする半導体装置。
1. A semiconductor device comprising: a semiconductor element; a die pad; a fixing member for fixing the semiconductor element and the die pad; and a sealing member for sealing the semiconductor element and the die pad. A semiconductor device, wherein the linear expansion coefficient of the member is 0.7 to 1.5 times the linear expansion coefficient of the sealing member.
【請求項2】 半導体素子と、内部リードと、上記半導
体素子と上記内部リードとを固定する固定部材と、上記
半導体素子と上記内部リードとを封止する封止部材とを
備えた半導体装置において、上記固定部材の線膨張係数
が上記封止部材の線膨張係数の0.7〜1.5倍にて成
ることを特徴とする半導体装置。
2. A semiconductor device comprising a semiconductor element, an internal lead, a fixing member for fixing the semiconductor element and the internal lead, and a sealing member for sealing the semiconductor element and the internal lead. A semiconductor device, wherein the linear expansion coefficient of the fixing member is 0.7 to 1.5 times the linear expansion coefficient of the sealing member.
【請求項3】 固定部材はエポキシ樹脂にシリカが70
〜80wt%充填され、線膨張係数が10.5〜30×
10-61/℃にて成ることを特徴とする請求項1記載の
半導体装置。
3. The fixing member is made of epoxy resin and silica of 70.
˜80 wt% filled with a linear expansion coefficient of 10.5-30 ×
The semiconductor device according to claim 1, wherein the semiconductor device is formed at 10 -6 1 / ° C.
【請求項4】 固定部材の表面が金属薄膜で覆われてい
ることを特徴とする請求項1または請求項3のいずれか
に記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the surface of the fixing member is covered with a thin metal film.
【請求項5】 固定部材はエポキシ樹脂にシリカが70
〜80wt%充填され、線膨張係数が10.5〜30×
10-61/℃にて成ることを特徴とする請求項2記載の
半導体装置。
5. The fixing member is made of epoxy resin and silica of 70.
˜80 wt% filled with a linear expansion coefficient of 10.5-30 ×
The semiconductor device according to claim 2, wherein the semiconductor device is formed at 10 -6 1 / ° C.
【請求項6】 所望の厚みを有するシート状の固定部材
をダイパットと半導体素子との間の所定の箇所にはさみ
こむ工程と、上記固定部材を加熱および加圧して硬化す
る工程と、上記ダイパットと上記半導体素子とを封止部
材にて封止する工程とを備えたことを特徴とする請求項
1または請求項3のいずれかに記載の半導体装置の製造
方法。
6. A step of sandwiching a sheet-shaped fixing member having a desired thickness at a predetermined position between the die pad and the semiconductor element, a step of hardening the fixing member by heating and pressurizing, the die pad and the 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of sealing the semiconductor element with a sealing member.
【請求項7】 50μm以下の厚みを有するシート状の
固定部材をダイパットと半導体素子との間の所定の箇所
にはさみこむ工程と、上記固定部材を150〜200℃
に加熱および30kg/mm2程度に加圧し、20μm
以下の厚みにして硬化する工程と、上記ダイパットと上
記半導体素子とを封止部材にて封止する工程とを備えた
ことを特徴とする請求項1または請求項3のいずれかに
記載の半導体装置の製造方法。
7. A step of sandwiching a sheet-shaped fixing member having a thickness of 50 μm or less at a predetermined position between the die pad and the semiconductor element, and the fixing member at 150 to 200 ° C.
And pressurize to about 30 kg / mm 2 to 20 μm
4. The semiconductor according to claim 1, further comprising: a step of hardening the die pad and the semiconductor element to have the following thickness, and a step of sealing the die pad and the semiconductor element with a sealing member. Device manufacturing method.
【請求項8】 所望の厚みを有し且つ金属薄膜で表面が
覆われているシート状の固定部材をダイパットと半導体
素子との間の所定の箇所にはさみこむ工程と、上記固定
部材を加熱および加圧して硬化する工程と、上記ダイパ
ットと上記半導体素子とを封止部材にて封止する工程と
を備えたことを特徴とする請求項4に記載の半導体装置
の製造方法。
8. A step of sandwiching a sheet-shaped fixing member having a desired thickness and whose surface is covered with a metal thin film at a predetermined position between a die pad and a semiconductor element, and heating and applying the fixing member. The method of manufacturing a semiconductor device according to claim 4, further comprising: a step of pressing and curing, and a step of sealing the die pad and the semiconductor element with a sealing member.
【請求項9】 50μm以下の厚みを有し且つ金属薄膜
で表面が覆われているシート状の固定部材をダイパット
と半導体素子との間の所定の箇所にはさみこむ工程と、
上記固定部材を150〜200℃に加熱および30kg
/mm2程度に加圧し、20μm以下の厚みにして硬化
する工程と、上記ダイパットと上記半導体素子とを封止
部材にて封止する工程とを備えたことを特徴とする請求
項4に記載の半導体装置の製造方法。
9. A step of sandwiching a sheet-like fixing member having a thickness of 50 μm or less and having a surface covered with a metal thin film at a predetermined position between the die pad and the semiconductor element.
The fixing member is heated to 150 to 200 ° C. and 30 kg
5. The method according to claim 4, further comprising a step of applying a pressure of about / mm 2 to a thickness of 20 μm or less and curing, and a step of sealing the die pad and the semiconductor element with a sealing member. Of manufacturing a semiconductor device of.
【請求項10】 所望の厚みを有するシート状の固定部
材を内部リードと半導体素子との間の所定の箇所にはさ
みこむ工程と、上記固定部材を加熱および加圧して硬化
する工程と、上記内部リードと上記半導体素子とを封止
部材にて封止する工程とを備えたことを特徴とする請求
項2または請求項5のいずれかに記載の半導体装置の製
造方法。
10. A step of sandwiching a sheet-shaped fixing member having a desired thickness at a predetermined position between the internal lead and the semiconductor element, a step of heating and pressing the fixing member to cure the fixing member, and the internal lead. 6. The method of manufacturing a semiconductor device according to claim 2, further comprising: a step of sealing the semiconductor element with a sealing member.
【請求項11】 50μm以下の厚みを有するシート状
の固定部材を内部リードと半導体素子との間の所定の箇
所にはさみこむ工程と、上記固定部材を150〜200
℃に加熱および30kg/mm2程度に加圧し、20μ
m以下の厚みにして硬化する工程と、上記内部リードと
上記半導体素子とを封止部材にて封止する工程とを備え
たことを特徴とする請求項2または請求項5のいずれか
に記載の半導体装置の製造方法。
11. A step of sandwiching a sheet-like fixing member having a thickness of 50 μm or less at a predetermined position between an internal lead and a semiconductor element, and 150 to 200 of the fixing member.
Heated to ℃ and pressurized to about 30kg / mm 2 , 20μ
6. The method according to claim 2, further comprising: a step of hardening to a thickness of m or less; and a step of sealing the internal lead and the semiconductor element with a sealing member. Of manufacturing a semiconductor device of.
JP07071594A 1994-04-08 1994-04-08 Semiconductor device and method of manufacturing semiconductor device Expired - Fee Related JP3300525B2 (en)

Priority Applications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999001771A1 (en) * 1997-07-04 1999-01-14 Kabushiki Kaisha Tokai Rika Denki Seisakusho Sensor with diaphragm sensor chip
JP2002093825A (en) * 2000-09-11 2002-03-29 Nippon Steel Chem Co Ltd Semiconductor package and its manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4019254B2 (en) 2002-04-24 2007-12-12 信越化学工業株式会社 Conductive resin composition

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999001771A1 (en) * 1997-07-04 1999-01-14 Kabushiki Kaisha Tokai Rika Denki Seisakusho Sensor with diaphragm sensor chip
US6201285B1 (en) 1997-07-04 2001-03-13 Kabushiki Kaisha Tokai Rika Denki Seisakusho Sensor with diaphragm sensor chip
JP2002093825A (en) * 2000-09-11 2002-03-29 Nippon Steel Chem Co Ltd Semiconductor package and its manufacturing method
JP4537555B2 (en) * 2000-09-11 2010-09-01 新日鐵化学株式会社 Semiconductor package manufacturing method and semiconductor package

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