JP3279849B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3279849B2
JP3279849B2 JP30258394A JP30258394A JP3279849B2 JP 3279849 B2 JP3279849 B2 JP 3279849B2 JP 30258394 A JP30258394 A JP 30258394A JP 30258394 A JP30258394 A JP 30258394A JP 3279849 B2 JP3279849 B2 JP 3279849B2
Authority
JP
Japan
Prior art keywords
semiconductor element
insulating base
external lead
wiring layer
metallized wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30258394A
Other languages
Japanese (ja)
Other versions
JPH08162589A (en
Inventor
清茂 宮脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP30258394A priority Critical patent/JP3279849B2/en
Publication of JPH08162589A publication Critical patent/JPH08162589A/en
Application granted granted Critical
Publication of JP3279849B2 publication Critical patent/JP3279849B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、コンピュータ等の情報
処理装置に使用される半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for an information processing device such as a computer.

【0002】[0002]

【従来技術】従来、コンピューター等の情報処理装置に
使用される半導体装置は、半導体素子と、半導体素子を
搭載するダイパッドと、該ダイパッドを取り囲みダイパ
ッド近傍から所定間隔で延出する多数の外部リード端子
と、前記半導体素子、ダイパッド及び外部リード端子の
一部を被覆するモールド樹脂とで形成されており、かか
る半導体装置は、ダイパッドと多数の外部リード端子と
が枠状の連結帯を介して一体に連結形成されたリードフ
レームを準備するとともに該リードフレームのダイパッ
ド上面に半導体素子を搭載固定し、次に前記半導体素子
の各電極と外部リード端子とをボンディングワイヤーを
介して電気的に接続するとともに前記半導体素子、ダイ
パッド及び外部リード端子の一部をモールド樹脂により
被覆することによって製作されている。
2. Description of the Related Art Conventionally, a semiconductor device used for an information processing apparatus such as a computer includes a semiconductor element, a die pad on which the semiconductor element is mounted, and a large number of external lead terminals surrounding the die pad and extending at predetermined intervals from near the die pad. And a mold resin that covers a part of the semiconductor element, the die pad, and the external lead terminal. In such a semiconductor device, the die pad and a large number of external lead terminals are integrally formed via a frame-shaped connecting band. Prepare a connected lead frame and mount and fix a semiconductor element on the upper surface of the die pad of the lead frame, and then electrically connect each electrode of the semiconductor element and an external lead terminal via a bonding wire, and By covering the semiconductor element, die pad and part of the external lead terminals with mold resin It has been produced Te.

【0003】尚、前記リードフレームは、銅を主成分と
する金属や鉄を主成分とする金属等から成り、該銅を主
成分とする金属等から成る薄板に従来周知の打ち抜き加
工やエッチング加工等の金属加工を施すことによって製
作される。
The lead frame is made of a metal mainly composed of copper, a metal mainly composed of iron, or the like. And the like.

【0004】しかしながら、従来の打ち抜き加工やエッ
チング加工により形成されるリードフレームは、外部リ
ード端子の幅及び隣接する外部リード端子の間隔を0.
3mm以下の極めて狭いものとすることが困難であり、
そのため近時の高集積化が進み電極数が大幅に増大した
半導体素子を搭載させた場合、半導体素子に近接して多
数の外部リード端子を配置することが不可となる。従っ
て、半導体素子の各電極と外部リード端子とを電気的に
接続するボンディングワイヤーが長いものとなり、その
結果、半導体素子、ダイパッド及び外部リード端子の一
部をモールド樹脂により被覆する際等にボンディングワ
イヤーに外力が印加されると、僅かな外力によりボンデ
ィングワイヤーが容易に変形し、隣接するボンディング
ワイヤー同士が互いに接触して電気的短絡を引き起こし
てしまうという欠点を有していた。
However, in a conventional lead frame formed by punching or etching, the width of an external lead terminal and the distance between adjacent external lead terminals are set to 0.
It is difficult to make it extremely narrow, 3 mm or less,
For this reason, in recent years, when high integration is advanced and a semiconductor element having a significantly increased number of electrodes is mounted, it is impossible to arrange a large number of external lead terminals close to the semiconductor element. Accordingly, the length of the bonding wire for electrically connecting each electrode of the semiconductor element to the external lead terminal becomes long. As a result, when the semiconductor element, the die pad, and a part of the external lead terminal are covered with the mold resin, the bonding wire becomes long. When an external force is applied to the bonding wire, the bonding wire is easily deformed by a slight external force, and adjacent bonding wires come into contact with each other to cause an electric short circuit.

【0005】そこで、上記欠点を解消するために酸化ア
ルミニウム質焼結体等の電気絶縁材料から成り、上面に
半導体素子を搭載する搭載部及び該搭載部から外周部に
かけて扇状に高密度に導出する多数のメタライズ配線層
を有する絶縁基体及び内端が前記絶縁基体外周部位にお
けるメタライズ配線層の間隔と実質的に同一の間隔で配
置された多数の外部リード端子を外端部で枠状の連結帯
により一体に連結して成るリードフレームを準備すると
ともに該絶縁基体のメタライズ配線層に外部リード端子
の内端を銀ロウ、半田、金−錫ロウ等のロウ材を介して
接合させ、しかる後、前記絶縁基体の搭載部に半導体素
子を該半導体素子の各電極とメタライズ配線層とが金属
バンプを介して電気的に接続されるようにして搭載固定
するとともに前記絶縁基体、半導体素子及び外部リード
端子の一部をモールド樹脂により被覆するようになした
半導体装置が提案されている。
Therefore, in order to solve the above-mentioned drawbacks, it is made of an electrically insulating material such as an aluminum oxide sintered body, and a mounting portion for mounting a semiconductor element on an upper surface and a fan-like high density lead from the mounting portion to the outer peripheral portion. An insulating base having a large number of metallized wiring layers and a large number of external lead terminals whose inner ends are arranged at substantially the same intervals as the intervals of the metallized wiring layers at the outer peripheral portion of the insulating base are connected to a frame-like connecting band at the outer end. Prepare a lead frame integrally connected by the above, and join the inner ends of the external lead terminals to the metallized wiring layer of the insulating base via silver brazing, soldering, brazing material such as gold-tin brazing, and then A semiconductor element is mounted and fixed on a mounting portion of the insulating base so that each electrode of the semiconductor element and a metallized wiring layer are electrically connected via metal bumps. Edge base, a semiconductor device of a part without so as to cover a mold resin of the semiconductor element and the external lead terminals has been proposed.

【0006】かかる半導体装置は、絶縁基体、半導体素
子及び外部リード端子の一部をモールド樹脂により被覆
した後、外部リード端子を枠状の連結帯から切断分離さ
せ、各外部リード端子を電気的に独立させるとともに各
外部リード端子を外部電気回路に接続することにより内
部の半導体素子が外部電気回路に電気的に接続されるこ
とになる。
In such a semiconductor device, after the insulating base, the semiconductor element, and a part of the external lead terminals are covered with a mold resin, the external lead terminals are cut and separated from the frame-shaped connecting band, and each external lead terminal is electrically connected. By making them independent and connecting each external lead terminal to an external electric circuit, the internal semiconductor element is electrically connected to the external electric circuit.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前記半
導体装置は、絶縁基体と半導体素子との間に金属バンプ
の高さ分だけ隙間が形成され、該隙間が狭いために絶縁
基体、半導体素子及び外部リード端子の一部をモールド
樹脂により被覆する際に前記絶縁基体と半導体素子との
隙間に存在する空気が外部に良好に排出されず絶縁基体
と半導体素子との間に残留して熱伝導率の悪い空隙が多
数形成されてしまい、その結果、半導体素子が作動時に
発生する熱が絶縁基体及びモールド樹脂を介して外部に
良好に放散除去されず、半導体素子が該半導体素子自身
の発生する熱で高温となり、半導体素子に熱破壊や誤動
作を発生させてしまうという欠点を誘発した。
However, in the above-mentioned semiconductor device, a gap is formed between the insulating base and the semiconductor element by the height of the metal bump. When a part of the lead terminal is covered with the mold resin, air existing in the gap between the insulating base and the semiconductor element is not sufficiently discharged to the outside and remains between the insulating base and the semiconductor element to reduce the thermal conductivity. A large number of bad voids are formed, and as a result, heat generated during operation of the semiconductor element is not satisfactorily radiated and removed to the outside through the insulating base and the mold resin, and the semiconductor element is generated by the heat generated by the semiconductor element itself. The high temperature has caused a disadvantage that the semiconductor element may be damaged by heat or malfunction.

【0008】[0008]

【発明の目的】本発明は、かかる従来の欠点に鑑み案出
されたもので、その目的は内部の半導体素子を常に低温
として正常、且つ安定に作動させることが可能な半導体
装置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has as its object to provide a semiconductor device capable of operating normally and stably at a low internal semiconductor element temperature. It is in.

【0009】[0009]

【課題を解決するための手段】本発明は、上面中央部に
半導体素子が搭載される搭載部及び該搭載部周辺から外
周部にかけて導出するメタライズ配線層を有する絶縁基
体と、前記絶縁基体の搭載部に搭載され、電極が前記メ
タライズ配線層に金属バンプを介して接続されている半
導体素子と、前記絶縁基体及び半導体素子を被覆するモ
ールド樹脂とから成る半導体装置であって、前記半導体
素子はその厚み方向に貫通する貫通孔が形成されている
ことを特徴とするものである。
SUMMARY OF THE INVENTION The present invention relates to an insulating substrate having a mounting portion on which a semiconductor element is mounted in the center of the upper surface, and a metallized wiring layer extending from the periphery of the mounting portion to the outer periphery, and mounting of the insulating substrate. A semiconductor element mounted on a portion and having an electrode connected to the metallized wiring layer via a metal bump, and a mold resin covering the insulating base and the semiconductor element, wherein the semiconductor element is A through-hole penetrating in the thickness direction is formed.

【0010】[0010]

【作用】本発明の半導体装置は、絶縁基体に搭載される
半導体素子の厚み方向に貫通孔を有していることから、
絶縁基体上に半導体素子を金属バンプを介して搭載後、
前記絶縁基体及び半導体素子をモールド樹脂で被覆する
際、絶縁基体と半導体素子との間に存在する空気は前記
半導体素子に設けた孔から外部に良好に排出され、その
結果、絶縁基体と半導体素子との間に熱伝導率の悪い空
隙が多量に発生することは一切ない。
The semiconductor device of the present invention has a through-hole in the thickness direction of the semiconductor element mounted on the insulating base.
After mounting the semiconductor element on the insulating base via the metal bump,
When the insulating base and the semiconductor element are covered with the mold resin, air existing between the insulating base and the semiconductor element is satisfactorily exhausted to the outside through a hole provided in the semiconductor element. There is no generation of a large amount of voids having poor thermal conductivity between them.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1は、本発明の半導体装置の一実施例を示し、1
は絶縁基体、2は外部リード端子、3は半導体素子であ
る。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of the semiconductor device of the present invention.
Is an insulating base, 2 is an external lead terminal, and 3 is a semiconductor element.

【0012】前記絶縁基体1は、その上面中央部に半導
体素子を搭載する搭載部1aを有しており、該搭載部1
aには半導体素子3が搭載実装される。
The insulating base 1 has a mounting portion 1a for mounting a semiconductor element at the center of the upper surface thereof.
The semiconductor element 3 is mounted on a.

【0013】前記絶縁基体1は、酸化アルミニウム質焼
結体、窒化アルミニウム質焼結体、ムライト質焼結体、
炭化珪素質焼結体、ガラスセラミックス焼結体等の電気
絶縁材料から成り、例えば酸化アルミニウム質焼結体か
ら成る場合は、酸化アルミニウム、酸化珪素、酸化カル
シウム、酸化マグネシウム等の原料粉末に適当なバイン
ダー、溶剤を添加混合して泥漿状となすとともにこれを
従来周知のドクターブレード法を採用してシート状とな
すことによってセラミックグリーンシート(セラミック
生シート)を得、しかる後、前記セラミックグリーンシ
ートを打ち抜き加工法等により適当な形状に打ち抜くと
ともに必要に応じて複数枚を積層し、最後に前記セラミ
ックグリーンシートを還元雰囲気中約1600℃の温度
で焼成することによって製作される。
The insulating substrate 1 is made of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
It is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramic sintered body. For example, in the case of an aluminum oxide sintered body, it is suitable for a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide. A ceramic green sheet (green ceramic sheet) is obtained by adding and mixing a binder and a solvent to form a slurry and forming the sheet into a sheet by using a conventionally known doctor blade method. It is manufactured by punching into an appropriate shape by a punching method or the like, laminating a plurality of sheets as necessary, and finally firing the ceramic green sheet at a temperature of about 1600 ° C. in a reducing atmosphere.

【0014】また、前記絶縁基体1は、その搭載部1a
から外周部にかけて扇状に広がる多数のメタライズ配線
層4が被着形成されており、該メタライズ配線層4の搭
載部1a周辺部位には半導体素子3の各電極が半田等の
金属から成る金属バンプ5を介して電気的に接続された
状態で接合され、また絶縁基体1の外周部位には外部電
気回路と接続される外部リード端子2がロウ材6を介し
て接合される。
The insulating base 1 has a mounting portion 1a.
A large number of metallized wiring layers 4 spreading in a fan shape from the metallized wiring layer 4 are formed on the mounting portion 1a of the metallized wiring layer 4, and each electrode of the semiconductor element 3 is formed of a metal bump 5 made of a metal such as solder. An external lead terminal 2 connected to an external electric circuit is joined to an outer peripheral portion of the insulating base 1 via a brazing material 6.

【0015】前記メタライズ配線層4は、タングステ
ン、モリブデン、マンガン等の高融点金属粉末から成
り、前記タングステン等の高融点粉末に適当なバインダ
ー、溶剤を添加混合して得た金属ペーストを前記絶縁基
体1となるセラミックグリーンシートに従来周知のスク
リーン印刷法等の厚膜手法を採用して所定パターンに印
刷塗布しておくことによって絶縁基体1の搭載部1aか
ら絶縁基体1外周部上面にかけて扇状に広がるように被
着形成される。
The metallized wiring layer 4 is made of a high melting point metal powder such as tungsten, molybdenum, manganese or the like. By printing and applying a predetermined pattern on the ceramic green sheet to be used as a substrate 1 by using a conventionally known thick film method such as a screen printing method, the ceramic green sheet spreads in a fan shape from the mounting portion 1a of the insulating substrate 1 to the upper surface of the outer peripheral portion of the insulating substrate 1. Is formed as follows.

【0016】前記メタライズ配線層4にロウ材6を介し
て接合される外部リード端子2は、内部に収容する半導
体素子3を外部電気回路に接続する作用を為し、外部リ
ード端子2を外部電気回路基板の配線導体に接続するこ
とにより、半導体素子3がメタライズ配線層4及び外部
リード端子2を介して外部電気回路に電気的に接続され
ることとなる。
An external lead terminal 2 joined to the metallized wiring layer 4 via a brazing material 6 serves to connect the semiconductor element 3 housed therein to an external electric circuit, and connects the external lead terminal 2 to an external electric circuit. By connecting to the wiring conductor of the circuit board, the semiconductor element 3 is electrically connected to the external electric circuit via the metallized wiring layer 4 and the external lead terminal 2.

【0017】前記外部リード端子2は、銅を主成分とす
る銅系合金や鉄を主成分とする鉄系合金等の金属から成
り、例えば銅系合金のインゴットを従来周知の圧延加工
法を採用して所定厚みの板状となすとともにこれにエッ
チング加工やパンチング加工を施して所定の形状となす
ことによって製作される。
The external lead terminal 2 is made of a metal such as a copper alloy containing copper as a main component or an iron alloy containing iron as a main component. For example, a copper alloy ingot is formed by a conventionally known rolling method. Then, a plate having a predetermined thickness is formed, and the plate is etched and punched to form a predetermined shape.

【0018】尚、前記外部リード端子2を絶縁基体1の
メタライズ配線層4に取着するには、内端が前記絶縁基
体1外周部部位におけるメタライズ配線層4の間隔と実
質的に同一の間隔で配置された多数の外部リード端子2
を外端部で枠状の連結帯により一体に連結して成るリー
ドフレームを準備するとともに絶縁基体1のメタライズ
配線層4上に外部リード端子2の内端を両者の間に銀ロ
ウ、半田、金−錫ロウ等のロウ材6を挟んで載置し、こ
れを前記ロウ6が溶融する温度以上の温度に加熱してロ
ウ材6を溶融させ、しかる後、前記溶融したロウ材6を
冷却固化させる方法が採用される。
In order to attach the external lead terminals 2 to the metallized wiring layer 4 of the insulating substrate 1, the inner ends of the external lead terminals 2 should be substantially the same as the distance between the metallized wiring layers 4 at the outer peripheral portion of the insulating substrate 1. Many external lead terminals 2 arranged in
Of the external lead terminals 2 on the metallized wiring layer 4 of the insulating base 1 with silver brazing, soldering, and the like. The brazing material 6 such as a gold-tin brazing material is interposed and heated to a temperature equal to or higher than the temperature at which the brazing material 6 is melted to melt the brazing material 6, and then the molten brazing material 6 is cooled. A method of solidifying is employed.

【0019】また、前記絶縁体1の搭載部1aに搭載実
装される半導体素子3は、その下面に多数の電極3aを
有しており、該電極3aとメタライズ配線層4とが金属
バンプ5を介して接合されている。
The semiconductor element 3 mounted and mounted on the mounting portion 1a of the insulator 1 has a large number of electrodes 3a on its lower surface, and the electrodes 3a and the metallized wiring layer 4 have metal bumps 5 formed thereon. Are joined through.

【0020】前記金属バンプ5は、例えば錫−鉛半田等
の金属からなり、該錫−鉛半田を半導体素子3の各電極
3a、或いは絶縁基体1のメタライズ配線層4の所定位
置に予め熔着法やメッキ法等により所定高さに被着させ
ておくことによって形成され、絶縁基体1のメタライズ
配線層4に半導体素子3の各電極3a金属バンプ5を介
して接続するには、例えば絶縁基体1の搭載部1aに半
導体素子3を該半導体素子3の各電極3aとメタライズ
配線層4との間に金属バンプ5を挟んで載置し、これを
前記半田から成る金属バンプ5が溶融する温度以上の温
度に加熱して前記金属バンプ5を溶融させ、しかる後、
前記溶融した金属バンプ5を冷却固化することによって
接続する方法が採られる。
The metal bumps 5 are made of, for example, a metal such as tin-lead solder, and the tin-lead solder is previously welded to each electrode 3a of the semiconductor element 3 or a predetermined position of the metallized wiring layer 4 of the insulating base 1. In order to connect to the metallized wiring layer 4 of the insulating substrate 1 via the metal bumps 5 of the electrodes 3a of the semiconductor element 3, for example, an insulating substrate The semiconductor element 3 is mounted on the mounting portion 1a of the semiconductor device 3 with a metal bump 5 interposed between each electrode 3a of the semiconductor element 3 and the metallized wiring layer 4, and the temperature at which the metal bump 5 made of solder melts is placed. Heat to the above temperature to melt the metal bumps 5, and then
A method of connecting by cooling and solidifying the molten metal bump 5 is adopted.

【0021】更に前記半導体素子3にはその厚み方向に
貫通する貫通孔3bが形成されており、該貫通孔3bは
絶縁基体1に半導体素子3を搭載後、絶縁基体1、半導
体素子3及び外部リード端子2の一部を後述するモール
ド樹脂7で被覆する際に前記絶縁基体1と半導体素子3
との間に存在する空気を外部に排出する排出孔として作
用する。
Further, a through hole 3b penetrating the semiconductor element 3 in the thickness direction thereof is formed. After the semiconductor element 3 is mounted on the insulating base 1, the through hole 3b is formed on the insulating base 1, the semiconductor element 3, and the outside. When a part of the lead terminal 2 is covered with a mold resin 7 described later, the insulating base 1 and the semiconductor element 3
And serves as a discharge hole for discharging air existing between the outside and the outside.

【0022】前記半導体素子3にはその厚み方向に貫通
する貫通孔3bが形成されていることから、モールド樹
脂7により、絶縁基体1、半導体素子3及び外部リード
端子2の一部を被覆する際、絶縁基体1と半導体素子3
との間に存在する空気は、前記半導体素子3に形成され
た貫通孔3bから外部に良好に排出され、従って、絶縁
基体1と半導体素子3との間に熱伝導率の悪い空隙が形
成されることは一切なく、その結果、半導体素子3が作
動時に発生する熱は、絶縁基体1及びモールド樹脂7を
介して外部に良好に放散除去され、半導体素子3を常に
低温として正常、且つ安定に作動させることが可能とな
る。
Since the semiconductor element 3 is formed with a through hole 3b penetrating in the thickness direction, when the insulating resin 1, the semiconductor element 3 and a part of the external lead terminal 2 are covered with the mold resin 7, , Insulating base 1 and semiconductor element 3
Is satisfactorily discharged to the outside through the through-hole 3b formed in the semiconductor element 3, so that a gap having poor thermal conductivity is formed between the insulating base 1 and the semiconductor element 3. As a result, heat generated during operation of the semiconductor element 3 is satisfactorily dissipated and removed to the outside via the insulating base 1 and the mold resin 7, so that the semiconductor element 3 is always kept at a low temperature in a normal and stable manner. It can be activated.

【0023】また前記絶縁基体1、半導体素子3及び外
部リード端子2の一部は、エポキシ樹脂等から成るモー
ルド樹脂7により被覆されており、これにより半導体素
子3が内部に気密に封止されることとなる。
A part of the insulating base 1, the semiconductor element 3, and the external lead terminals 2 is covered with a mold resin 7 made of epoxy resin or the like, whereby the semiconductor element 3 is hermetically sealed therein. It will be.

【0024】前記絶縁基体1、半導体素子3及び外部リ
ード端子2の一部をモールド樹脂7で被覆するには、半
導体素子3及び外部リード端子2が接合された絶縁基体
1を所定のモールド金型内に配置するとともに該金型内
にエポキシ樹脂等のモールド樹脂を注入し、しかる後、
注入した樹脂を約200℃の温度、100kgf/mm
2 の圧力を加えて熱硬化させる方法が採られる。
In order to cover the insulating substrate 1, the semiconductor element 3 and a part of the external lead terminal 2 with the molding resin 7, the insulating substrate 1 to which the semiconductor element 3 and the external lead terminal 2 are joined is formed by a predetermined molding die. And inject mold resin such as epoxy resin into the mold, and then
The injected resin is heated at a temperature of about 200 ° C. and 100 kgf / mm.
The method of applying heat and hardening by applying pressure is adopted.

【0025】尚、前記絶縁基体1、半導体素子3及び外
部リード端子2の一部をモールド樹脂7で覆う場合、先
ず絶縁基体1と半導体素子3との間にモールド樹脂7a
を注入して絶縁基体1と半導体素子3との間をモールド
樹脂7aで完全に充填させた後、絶縁基体1、半導体素
子3及び外部リード端子2の一部で残りの部分をモール
ド樹脂7bで覆うようにすると絶縁基体1と半導体素子
3との間に存在する空気をより効率よく外部に排出する
ことができる。
When the insulating substrate 1, the semiconductor element 3 and a part of the external lead terminals 2 are covered with the molding resin 7, first, the molding resin 7a is interposed between the insulating substrate 1 and the semiconductor element 3.
To completely fill the space between the insulating base 1 and the semiconductor element 3 with the molding resin 7a, and then the remaining part of the insulating base 1, the semiconductor element 3 and the external lead terminals 2 is filled with the molding resin 7b. By covering, the air existing between the insulating base 1 and the semiconductor element 3 can be more efficiently discharged to the outside.

【0026】かくして本発明の半導体装置によれば、外
部リード端子2が取着された絶縁基体1の搭載部1aに
半導体素子3を、該半導体素子3の各電極3aと絶縁基
体1のメタライズ配線層4とが半田等の金属から成る金
属バンプ5で電気的に接続するようにして搭載し、しか
る後、前記絶縁基体1、半導体素子3及び外部リード端
子2の一部をモールド樹脂7で被覆し、最後に前記各外
部リード端子2を枠状の連結帯から切断分離して各々電
気的に独立させ、該電気的に各々独立した外部リード端
子2を外部電気回路に接続することによってコンピュー
ター等の情報処理装置内で使用されることとなる。
Thus, according to the semiconductor device of the present invention, the semiconductor element 3 is mounted on the mounting portion 1a of the insulating base 1 to which the external lead terminals 2 are attached, and each electrode 3a of the semiconductor element 3 is connected to the metallized wiring of the insulating base 1. The layer 4 is mounted so as to be electrically connected to a metal bump 5 made of a metal such as solder. Thereafter, a part of the insulating base 1, the semiconductor element 3, and the external lead terminals 2 is covered with a mold resin 7. Finally, each of the external lead terminals 2 is cut and separated from the frame-shaped connecting band to be electrically independent, and the electrically independent external lead terminals 2 are connected to an external electric circuit, so that a computer or the like can be obtained. Will be used in the information processing device.

【0027】[0027]

【発明の効果】本発明の半導体装置は、絶縁基体に搭載
される半導体素子の厚み方向に貫通孔を有していること
から、絶縁基体上に半導体素子を金属バンプを介して搭
載後、前記絶縁基体及び半導体素子をモールド樹脂で被
覆する際、絶縁基体と半導体素子との間に存在する空気
は前記半導体素子に設けた貫通孔から外部に良好に排出
される。従って、絶縁基体と半導体素子との間に熱伝導
率の悪い空隙が多量に形成されることは一切なく、その
結果、半導体素子が作動時に発生する熱を絶縁基体及び
モールド樹脂を介して外部に良好に放散除去させること
ができ、半導体素子を常に正常、且つ安定に作動させる
ことが可能となる。
Since the semiconductor device of the present invention has a through hole in the thickness direction of the semiconductor element mounted on the insulating base, the semiconductor element is mounted on the insulating base via a metal bump, When the insulating base and the semiconductor element are covered with the mold resin, air existing between the insulating base and the semiconductor element is satisfactorily discharged to the outside through a through hole provided in the semiconductor element. Therefore, a large amount of voids having poor thermal conductivity are never formed between the insulating base and the semiconductor element, and as a result, heat generated when the semiconductor element is operated is transferred to the outside via the insulating base and the molding resin. The semiconductor device can be satisfactorily diffused and removed, and the semiconductor element can always be operated normally and stably.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施例を示す断面図で
ある。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 1a・・・搭載部 2・・・・外部リード端子 3・・・・半導体素子 4・・・・メタライズ配線層 5・・・・金属バンプ 7・・・・モールド樹脂 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Mounting part 2 ... External lead terminal 3 ... Semiconductor element 4 ... Metallized wiring layer 5 ... Metal bump 7 ... Mold resin

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/50 H01L 21/56 H01L 21/60 311 H01L 23/28 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/50 H01L 21/56 H01L 21/60 311 H01L 23/28

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】上面中央部に半導体素子が搭載される搭載
部及び該搭載部から外周部にかけて導出するメタライズ
配線層を有する絶縁基体と、前記絶縁基体の搭載部に搭
載され、電極が前記メタライズ配線層に金属バンプを介
して接続されている半導体素子と、前記絶縁基体及び半
導体素子を被覆するモールド樹脂とから成る半導体装置
であって、前記半導体素子はその厚み方向に貫通する貫
通孔が形成されていることを特徴とする半導体装置。
An insulating substrate having a mounting portion on which a semiconductor element is mounted at a central portion of an upper surface and a metallized wiring layer extending from the mounting portion to an outer peripheral portion; A semiconductor device comprising: a semiconductor element connected to a wiring layer via a metal bump; and a mold resin covering the insulating base and the semiconductor element, wherein the semiconductor element has a through hole penetrating in a thickness direction thereof. A semiconductor device characterized by being performed.
JP30258394A 1994-12-07 1994-12-07 Semiconductor device Expired - Fee Related JP3279849B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30258394A JP3279849B2 (en) 1994-12-07 1994-12-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30258394A JP3279849B2 (en) 1994-12-07 1994-12-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08162589A JPH08162589A (en) 1996-06-21
JP3279849B2 true JP3279849B2 (en) 2002-04-30

Family

ID=17910732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30258394A Expired - Fee Related JP3279849B2 (en) 1994-12-07 1994-12-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3279849B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011301A (en) * 1998-06-09 2000-01-04 Stmicroelectronics, Inc. Stress reduction for flip chip package
JP4797817B2 (en) * 2006-06-12 2011-10-19 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2014192347A (en) * 2013-03-27 2014-10-06 Murata Mfg Co Ltd Resin-sealed electronic equipment and electronic device with the same

Also Published As

Publication number Publication date
JPH08162589A (en) 1996-06-21

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