JP3287965B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP3287965B2
JP3287965B2 JP30471894A JP30471894A JP3287965B2 JP 3287965 B2 JP3287965 B2 JP 3287965B2 JP 30471894 A JP30471894 A JP 30471894A JP 30471894 A JP30471894 A JP 30471894A JP 3287965 B2 JP3287965 B2 JP 3287965B2
Authority
JP
Japan
Prior art keywords
insulating base
external electric
integrated circuit
electric circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30471894A
Other languages
Japanese (ja)
Other versions
JPH08162551A (en
Inventor
信行 伊藤
伸 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP30471894A priority Critical patent/JP3287965B2/en
Priority to US08/567,949 priority patent/US6225700B1/en
Publication of JPH08162551A publication Critical patent/JPH08162551A/en
Application granted granted Critical
Publication of JP3287965B2 publication Critical patent/JP3287965B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はLSI等の半導体集積回
路素子を収容するための半導体素子収納用パッケージに
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor integrated circuit device such as an LSI.

【0002】[0002]

【従来の技術】従来、半導体素子、特にLSI(大規模
集積回路素子)等の半導体集積回路素子を収容するため
の半導体素子収納用パッケージは、一般にアルミナセラ
ミックス等の電気絶縁材料から成り、その上面略中央部
に半導体集積回路素子を収容するための凹所を有する絶
縁基体と、前記絶縁基体の凹所周辺から下面にかけて導
出されるタングステン、モリブデン等の高融点金属粉末
から成る複数個のメタライズ配線層と、前記絶縁基体の
下面に形成され、メタライズ配線層が電気的に接続され
る複数個の接続パッドと、前記接続パッドにロウ付け取
着される半田(共晶半田)から成るボール状端子と、蓋
体とから構成されており、絶縁基体の凹所底面に半導体
集積回路素子をガラス、樹脂等から成る接着剤を介して
接着固定させ、半導体集積回路素子の各電極とメタライ
ズ配線層とをボンディングワイヤを介して電気的に接続
させるとともに絶縁基体上面に蓋体をガラス、樹脂等の
封止材を介して接合させ、絶縁基体と蓋体とから成る容
器内部に半導体集積回路素子を気密に封止することによ
って製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, especially a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit) is generally made of an electrically insulating material such as alumina ceramics. An insulating base having a recess for accommodating a semiconductor integrated circuit element in a substantially central portion thereof, and a plurality of metallized wirings made of a high melting point metal powder such as tungsten or molybdenum led out from the periphery of the recess to the lower surface of the insulating base. Layer, a plurality of connection pads formed on the lower surface of the insulating base, and electrically connected to the metallized wiring layer, and ball-shaped terminals made of solder (eutectic solder) brazed to the connection pads And a lid, and the semiconductor integrated circuit element is adhered and fixed to the bottom surface of the concave portion of the insulating base via an adhesive made of glass, resin, or the like. The electrodes of the integrated circuit device are electrically connected to the metallized wiring layers via bonding wires, and the lid is joined to the upper surface of the insulating base via a sealing material such as glass, resin, or the like. By hermetically sealing the semiconductor integrated circuit element inside the container formed by the above, a semiconductor device as a product is obtained.

【0003】かかる半導体装置は絶縁基体下面の接続パ
ッドにロウ付けされている半田から成るボール状端子を
外部電気回路基板の配線導体上に載置当接させ、しかる
後、前記ボール状端子を約200 〜250 ℃の温度で加熱溶
融し、ボール状端子を配線導体に接合させることによっ
て外部電気回路基板上に実装され、同時に半導体素子収
納用パッケージの内部に収容されている半導体集積回路
素子はその各電極がメタライズ配線層及びボール状端子
を介して外部電気回路に電気的に接続されることとな
る。
In such a semiconductor device, a ball-shaped terminal made of solder brazed to a connection pad on the lower surface of an insulating substrate is placed and abutted on a wiring conductor of an external electric circuit board. It is heated and melted at a temperature of 200 to 250 ° C and mounted on an external electric circuit board by joining ball-shaped terminals to wiring conductors, and at the same time, the semiconductor integrated circuit element housed inside the semiconductor element housing package is Each electrode is electrically connected to an external electric circuit via the metallized wiring layer and the ball-shaped terminals.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、アルミナ
セラミックス等から成る絶縁基体の熱膨張係数が約6.5
×10-6/ ℃であるのに対し、外部電気回路基板は一般に
ガラスエポキシ樹脂から成り、その熱膨張係数が2 ×10
-5/ ℃〜4 ×10-5/ ℃で両者大きく相違することから半
導体素子収納用パッケージの内部に半導体集積回路素子
を収容し、しかる後、外部電気回路基板に実装した場
合、半導体集積回路素子の作動時に発する熱が絶縁基体
と外部電気回路基板の両方に繰り返し印加されると前記
半導体素子収納用パッケージの絶縁基板と外部電気回路
基板との間に両者の熱膨張係数の相違に起因する大きな
熱応力が発生するとともにこれが絶縁基体下面の接続パ
ッドの外周部に作用して接続パッドを絶縁基体より剥離
させてしまい、その結果、半導体素子収納用パッケージ
の内部に収容する半導体集積回路素子の各電極を長期間
にわたり所定の外部電気回路に電気的に接続させること
ができないという欠点を有していた。
However, in this conventional package for housing a semiconductor element, the insulating base made of alumina ceramics or the like has a thermal expansion coefficient of about 6.5.
Whereas the external electric circuit board is generally made of glass epoxy resin and has a coefficient of thermal expansion of 2 × 10 −6 / ° C.
-5 / ℃ ~ 4 × 10 -5 / ℃, because the two are greatly different, when the semiconductor integrated circuit element is housed inside the semiconductor element housing package, and then mounted on an external electric circuit board, the semiconductor integrated circuit When heat generated during the operation of the element is repeatedly applied to both the insulating base and the external electric circuit board, the heat expansion coefficient is caused between the insulating substrate and the external electric circuit board of the package for housing the semiconductor element due to the difference between the two. When a large thermal stress is generated, this acts on the outer peripheral portion of the connection pad on the lower surface of the insulating base to separate the connection pad from the insulating base. As a result, the semiconductor integrated circuit device accommodated inside the semiconductor device housing package is removed. There was a drawback that each electrode could not be electrically connected to a predetermined external electric circuit for a long period of time.

【0005】また同時に半導体素子収納用パッケージの
形状が大型で全体の重量が重いと、絶縁基体下面の接続
パッドにロウ付けされているボール状端子を加熱溶融さ
せ、該ボール状端子を外部電気回路基板の配線導体に接
合させることによって半導体素子収納用パッケージを外
部電気回路基板上に実装させる際、加熱溶融させたボー
ル状端子が半導体素子収納用パッケージの重量により押
し潰されて絶縁基体下面と外部電気回路基板との間に拡
がり、その結果、各ボール状端子を所定の外部電気回路
に正確に電気的接続するのが困難となるとともに隣接す
るボール状端子間に電気的短絡が発生するという欠点を
有していた。
At the same time, if the semiconductor device housing package is large and the overall weight is heavy, the ball terminals soldered to the connection pads on the lower surface of the insulating base are heated and melted, and the ball terminals are connected to an external electric circuit. When mounting the semiconductor element housing package on an external electric circuit board by bonding it to the wiring conductor of the substrate, the heated and melted ball-shaped terminals are crushed by the weight of the semiconductor element housing package, and the lower surface of the insulating base and the outside are removed. The disadvantage is that it spreads between the electric circuit board and each ball-shaped terminal, making it difficult to accurately electrically connect each ball-shaped terminal to a predetermined external electric circuit, and causing an electric short circuit between adjacent ball-shaped terminals. Had.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に収容する半導体集積回路素子の各
電極を長期間にわたり所定の外部電気回路に電気的接続
することができる半導体素子収納用パッケージを提供す
ることにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to electrically connect each electrode of a semiconductor integrated circuit element housed therein to a predetermined external electric circuit for a long period of time. An object of the present invention is to provide a package for housing a semiconductor element.

【0007】[0007]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、電気絶縁材料から成り、上面に半導体
素子が載置される載置部を、下面に多数の凹部を有する
絶縁基体と、前記絶縁基体の半導体素子が載置される載
置部周辺から凹部底面にかけて導出される複数個のメタ
ライズ配線層と、前記絶縁基体の凹部底面に形成され、
メタライズ配線層が電気的に接続される複数個の接続パ
ッドと、前記接続パッドに取着され、絶縁基体の下面に
球状の突出部を有する半田から成る端子と、前記絶縁基
体の下面に形成された金属パッドと、前記金属パッドに
取着された金属ボールとから成ることを特徴とするもの
である。
According to the present invention, there is provided a package for housing a semiconductor element, which is made of an electrically insulating material, has a mounting portion on which an upper surface of a semiconductor element is mounted, an insulating base having a plurality of concave portions on a lower surface, A plurality of metallized wiring layers led out from around the mounting portion on which the semiconductor element of the insulating base is mounted to the bottom of the recess, and formed on the bottom of the recess of the insulating base;
A plurality of connection pads to which a metallized wiring layer is electrically connected; terminals formed of solder attached to the connection pads and having a spherical projection on a lower surface of the insulating base; and formed on a lower surface of the insulating base. And a metal ball attached to the metal pad.

【0008】また本発明の半導体素子収納用パッケージ
は、前記金属ボールを銅で形成し、且つ該金属ボールが
取着される金属パッドを、絶縁基体の半導体素子が載置
される載置部と対向する領域に形成したことを特徴とす
るものである。
In the semiconductor device housing package of the present invention, the metal ball is formed of copper, and a metal pad to which the metal ball is attached is provided on a mounting portion of the insulating base on which the semiconductor element is mounted. It is characterized in that it is formed in the facing area.

【0009】[0009]

【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁基体下面の凹部底面に接続パッドを設けるとと
もに、該接続パッドに絶縁基体の下面に球状の突出部を
有する半田から成る端子を取着させたことから、半導体
素子収納用パッケージの内部に半導体集積回路素子を収
容するとともに外部電気回路基板に実装した場合、半導
体集積回路素子の作動時に発する熱が絶縁基体と外部電
気回路基板の両方に繰り返し印加され、半導体素子収納
用パッケージの絶縁基体と外部電気回路基板との間に両
者の熱膨張係数の相違に起因する大きな熱応力が発生し
たとしてもその熱応力は接続パッドの外周部と絶縁基体
の凹部開口領域に位置する端子の両方に分散され、その
結果、接続パッドが絶縁基体より剥離することはなく、
半導体素子収納用パッケージの内部に収容する半導体集
積回路素子の各電極を長期間にわたり所定の外部電気回
路に正確に電気的接続させることが可能となる。
According to the package for housing a semiconductor element of the present invention, connection pads are provided on the bottom surface of the concave portion on the lower surface of the insulating base, and terminals made of solder having spherical projections on the lower surface of the insulating base are attached to the connection pads. Therefore, when the semiconductor integrated circuit element is housed inside the semiconductor element housing package and mounted on an external electric circuit board, the heat generated when the semiconductor integrated circuit element is operated generates heat on both the insulating base and the external electric circuit board. Even if a large thermal stress is generated between the insulating base of the package for housing the semiconductor element and the external electric circuit board due to the difference in the thermal expansion coefficient between the two, the thermal stress is insulated from the outer periphery of the connection pad. Dispersed in both of the terminals located in the recess opening area of the base, so that the connection pads do not peel off from the insulating base,
The electrodes of the semiconductor integrated circuit device housed in the semiconductor device housing package can be accurately and electrically connected to a predetermined external electric circuit for a long period of time.

【0010】また本発明の半導体素子収納用パッケージ
によれば、絶縁基板の下面に金属パッドを形成し、且つ
該金属パッドに金属ボールを取着させたことから絶縁基
体下面の接続パッドにロウ付けされている端子を加熱溶
融させ、該端子を外部電気回路基板の配線導体に接合さ
せることによって半導体素子収納用パッケージを外部電
気回路基板上に実装させる際、絶縁基体と外部電気回路
基板との間には前記金属ボールによって所定の空隙が形
成されて加熱溶融した端子が半導体素子収納用パッケー
ジの重量が重いことにより押し潰されることは一切な
く、その結果、各端子を所定の外部電気回路に正確に電
気的接続することが可能になるとともに隣接する端子間
の電気的独立を維持することができる。
According to the semiconductor device housing package of the present invention, the metal pad is formed on the lower surface of the insulating substrate, and the metal ball is attached to the metal pad. When the semiconductor device housing package is mounted on the external electric circuit board by heating and melting the terminal, and joining the terminal to the wiring conductor of the external electric circuit board, the gap between the insulating base and the external electric circuit board is reduced. A predetermined gap is formed by the metal ball, and the terminal melted by heating is not crushed at all by the heavy weight of the semiconductor element housing package. As a result, each terminal can be accurately connected to a predetermined external electric circuit. , And electrical independence between adjacent terminals can be maintained.

【0011】更に本発明の半導体素子収納用パッケージ
によれば、絶縁基体の半導体集積回路素子が載置される
載置部と対向する領域に金属パッドを形成しておき、且
つ該金属パッドに銅から成る金属ボールを取着しておく
と、半導体集積回路素子が作動時に多量の熱を発生した
際、その熱を金属ボールを介して外部電気回路基板、或
いは大気中に良好に放散させることができ、これによっ
て半導体集積回路素子は熱破壊や特性に劣化を招来する
ような高温になることは一切なく、半導体集積回路素子
を常に低温として長期間にわたり正常、且つ安定に作動
させることができる。
Further, according to the semiconductor device housing package of the present invention, a metal pad is formed in a region of the insulating base opposite to the mounting portion on which the semiconductor integrated circuit device is mounted, and the copper pad is formed on the metal pad. When the semiconductor integrated circuit element generates a large amount of heat during operation, the heat can be satisfactorily dissipated to the external electric circuit board or the atmosphere via the metal ball when the metal ball is attached. As a result, the semiconductor integrated circuit device does not reach a high temperature at which thermal destruction or deterioration of characteristics occurs, and the semiconductor integrated circuit device can be normally and stably operated at a low temperature for a long period of time.

【0012】[0012]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。
BRIEF DESCRIPTION OF THE DRAWINGS FIG.

【0013】図1は本発明にかかる半導体素子収納用パ
ッケージの一実施例を示し、1は絶縁基体、2は蓋体で
ある。この絶縁基体1と蓋体2とで半導体集積回路素子
3を収容する容器4が構成される。
FIG. 1 shows an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor integrated circuit element 3.

【0014】前記絶縁基体1はその上面中央部に半導体
集積回路素子3が載置収容される凹所1aが設けてあ
り、該凹所1a底面には半導体集積回路素子3がガラ
ス、樹脂等の接着剤を介して接着固定される。
The insulating substrate 1 is provided with a recess 1a in the center of the upper surface thereof for mounting the semiconductor integrated circuit element 3 thereon. The semiconductor integrated circuit element 3 is made of glass, resin or the like on the bottom of the recess 1a. It is bonded and fixed via an adhesive.

【0015】前記絶縁基体1は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば酸化アルミニウム質焼結体から
成る場合は酸化アルミニウム、酸化珪素、酸化マグネシ
ウム、酸化カルシウム等の原料粉末に適当な有機バイン
ダー、可塑剤、溶剤を添加混合して泥漿物を作るととも
に該泥漿物をドクターブレード法やカレンダーロール法
を採用することによってグリーンシート(生シート)と
成し、しかる後、前記グリーンシートに適当な打ち抜き
加工を施すとともにこれを複数枚積層し、約1600℃の温
度で焼成することによって製作される。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body and the like. In the case of an aluminum sintered body, an appropriate organic binder, a plasticizer, and a solvent are added to raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide to form a slurry, and the slurry is doctor bladed. Green sheet (raw sheet) by adopting the method or calender roll method, and then subjecting the green sheet to appropriate punching and laminating a plurality of these sheets, and firing at a temperature of about 1600 ° C. Produced by

【0016】また前記絶縁基体1 は半導体集積回路素子
3 が載置収容される凹所1aの周辺から下面にかけて複数
個のメタライズ配線層5 が被着形成されている。
The insulating substrate 1 is a semiconductor integrated circuit device.
A plurality of metallized wiring layers 5 are formed from the periphery to the lower surface of the recess 1a in which 3 is placed and accommodated.

【0017】更に前記絶縁基体1 の下面には凹部1bが設
けられており、該凹部1bの底面には前記メタライズ配線
層5 が電気的に接続される接続パッド5aが被着形成され
ている。
Further, a concave portion 1b is provided on the lower surface of the insulating base 1, and a connection pad 5a to which the metallized wiring layer 5 is electrically connected is formed on the bottom surface of the concave portion 1b.

【0018】前記メタライズ配線層5 及び接続パッド5a
はタングステン、モリブデン、マンガン等の高融点金属
粉末から成り、タングステン等の高融点金属粉末に適当
な有機バインダー、可塑剤、溶剤を添加混合して得た金
属ペーストを絶縁基体1 となるグリーンシートに予め従
来周知のスクリーン印刷法により所定パターンに印刷塗
布しておくことによって絶縁基体1 の所定位置に所定パ
ターンに被着形成される。
The metallized wiring layer 5 and the connection pad 5a
Is made of a high melting point metal powder such as tungsten, molybdenum, manganese, etc., and a suitable organic binder, a plasticizer, and a solvent are added to the high melting point metal powder such as tungsten and mixed. By printing and applying a predetermined pattern by a conventionally well-known screen printing method in advance, a predetermined pattern is adhered and formed at a predetermined position of the insulating base 1.

【0019】前記メタライズ配線層5 は半導体集積回路
素子3 の各電極を後述する接続パッド5aに取着される端
子7 に電気的に接続させる作用を為し、絶縁基体1 の凹
所1a周辺に位置する領域には半導体集積回路素子3 の各
電極がボンディングワイヤ6を介して電気的に接続され
る。
The metallized wiring layer 5 functions to electrically connect each electrode of the semiconductor integrated circuit element 3 to a terminal 7 attached to a connection pad 5a to be described later. Each electrode of the semiconductor integrated circuit element 3 is electrically connected to the located region via a bonding wire 6.

【0020】また前記メタライズ配線層5 と電気的に接
続されている接続パッド5aは絶縁基体1 に端子7を取着
する際の下地金属層として作用し、接続パッド5aの表面
には半田(鉛ー錫合金)から成る端子7 が取着されてい
る。
The connection pad 5a electrically connected to the metallized wiring layer 5 functions as a base metal layer when the terminal 7 is attached to the insulating base 1, and the surface of the connection pad 5a has a solder (lead) Terminal 7 made of tin alloy).

【0021】前記接続パッド5aに取着されている端子7
はまた絶縁基体1 の下面に球状の突出部7aを有してお
り、該球状突出部7aは端子7 を外部電気回路基板8 の配
線導体8aに接続させる際、その接続を容易、且つ確実と
なす作用をする。
The terminal 7 attached to the connection pad 5a
Also has a spherical protrusion 7a on the lower surface of the insulating base 1, and when connecting the terminal 7 to the wiring conductor 8a of the external electric circuit board 8, the connection is easy and reliable. It works.

【0022】前記端子7 は絶縁基体1 の下面に球状の突
出部7aを有することから絶縁基体1の凹所1a内に半導体
集積回路素子3 を収容し、外部電気回路基板8 に実装し
た後、半導体集積回路素子3 の作動時に発する熱が絶縁
基体1 と外部電気回路基板8の両方に繰り返し印加さ
れ、絶縁基体1 と外部電気回路基板8 との間に両者の熱
膨張係数の相違に起因する大きな熱応力が発生したとし
てもその熱応力は接続パッド5aの外周部と絶縁基体1 の
凹部1b開口領域に位置する端子7 の両領域に分散されて
小さくなり、その結果、前記熱応力によって接続パッド
5aが絶縁基体1 より剥離することはなく、容器4 内部に
収容する半導体集積回路素子3 の各電極を長期間にわた
り所定の外部電気回路に電気的に接続させることができ
る。
Since the terminal 7 has a spherical projection 7a on the lower surface of the insulating base 1, the semiconductor integrated circuit element 3 is accommodated in the recess 1a of the insulating base 1, and after mounting on the external electric circuit board 8, The heat generated during the operation of the semiconductor integrated circuit element 3 is repeatedly applied to both the insulating base 1 and the external electric circuit board 8, and is caused by the difference in the thermal expansion coefficient between the insulating base 1 and the external electric circuit board 8. Even if a large thermal stress is generated, the thermal stress is dispersed and reduced to both the outer peripheral portion of the connection pad 5a and the region of the terminal 7 located in the opening region of the concave portion 1b of the insulating base 1, and as a result, the connection due to the thermal stress is reduced. pad
The electrodes 5a of the semiconductor integrated circuit element 3 housed in the container 4 can be electrically connected to a predetermined external electric circuit for a long period of time without the 5a being separated from the insulating base 1.

【0023】更に前記絶縁基体1の下面には金属パッド
9 が被着されており、該金属パッド9 には金属ボール10
が取着されている。
Further, a metal pad is provided on the lower surface of the insulating base 1.
The metal pad 9 has a metal ball 10 attached thereto.
Is attached.

【0024】前記金属パッド9 は絶縁基体1 の下面に金
属ボール10を取着させる際の下地金属層として作用し、
タングステンやモリブデン、マンガン等で形成されてい
る。
The metal pad 9 functions as a base metal layer when the metal ball 10 is attached to the lower surface of the insulating base 1,
It is formed of tungsten, molybdenum, manganese, or the like.

【0025】前記金属パッド9 はメタライズ配線層5 と
同様の方法、具体的にはタングステン等の高融点金属粉
末に適当な有機バインダー、可塑剤、溶剤を添加混合し
て得た金属ペーストを絶縁基体1 となるグリーンシート
に予め従来周知のスクリーン印刷法により所定パターン
に印刷塗布しておくことによって絶縁基体1 の下面所定
位置に所定パターンに被着形成される。
The metal pad 9 is formed in the same manner as the metallized wiring layer 5, specifically, a metal paste obtained by adding a suitable organic binder, a plasticizer and a solvent to a refractory metal powder such as tungsten and mixing the same with an insulating substrate. By printing and applying a predetermined pattern on a green sheet to be 1 in advance by a conventionally known screen printing method, the green sheet is adhered and formed in a predetermined pattern at a predetermined position on the lower surface of the insulating substrate 1.

【0026】また前記金属パッド9 には金属ボール10が
半田等のロウ材を介して取着されており、該金属ボール
10は絶縁基体1 下面の接続パッド5aに取着されている半
田から成る端子7 を加熱溶融させ、該端子7 を外部電気
回路基板8 の配線導体8aに接合させることによって半導
体素子収納用パッケージを外部電気回路基板8 上に実装
させる際、絶縁基体1 上面と外部電気回路基板8 上面と
の間に所定の空隙を形成する作用を為し、これによって
前記加熱溶融された端子7 は半導体素子収納用パッケー
ジの重量が重いとしても押し潰されることは一切なく、
その結果、各端子7 を所定の外部電気回路に正確に電気
的接続することが可能となるとともに隣接する端子7 間
の電気的独立を維持することが可能となる。
A metal ball 10 is attached to the metal pad 9 via a brazing material such as solder.
Reference numeral 10 denotes a semiconductor element housing package by heating and melting a terminal 7 made of solder attached to a connection pad 5a on the lower surface of the insulating base 1 and joining the terminal 7 to a wiring conductor 8a of an external electric circuit board 8. When mounted on the external electric circuit board 8, it acts to form a predetermined gap between the upper surface of the insulating base 1 and the upper surface of the external electric circuit board 8. Even if the weight of the package is heavy, it will not be crushed at all,
As a result, each terminal 7 can be accurately electrically connected to a predetermined external electric circuit, and the electrical independence between adjacent terminals 7 can be maintained.

【0027】更に前記金属パッド9 を絶縁基体1 の半導
体集積回路素子3 が載置収容される凹所1aと対向する領
域に形成するとともに該金属パッド9 に取着される金属
ボール10を熱伝導性に優れる銅で形成しておくと半導体
集積回路素子3 が作動時に多量の熱を発生したとしても
その熱を金属ボール10を介して外部電気回路基板8 や大
気中に効率良く放散させることができ、これによって半
導体集積回路素子3 は熱破壊や特性に劣化を招来するよ
うな高温となることは一切なく、半導体集積回路素子3
を常に低温として長期間にわたり正常、且つ安定に作動
させることができる。従って、前記金属パッド9 は絶縁
基体1 の半導体集積回路素子3 が載置収容される凹所1a
と対向する領域に、また前記金属パッド9 に取着される
金属ボール10は熱伝導性に優れる銅で形成しておくこと
が好ましい。
Further, the metal pad 9 is formed in a region of the insulating base 1 facing the recess 1a in which the semiconductor integrated circuit element 3 is placed and accommodated, and the metal ball 10 attached to the metal pad 9 is thermally conductive. If the semiconductor integrated circuit element 3 generates a large amount of heat during operation, the heat can be efficiently dissipated to the external electric circuit board 8 and the atmosphere via the metal balls 10 even if the semiconductor integrated circuit element 3 generates a large amount of heat during operation. As a result, the semiconductor integrated circuit device 3 is never heated to a high temperature that would cause thermal destruction or deterioration of its characteristics.
Can be operated normally and stably for a long time at a low temperature. Accordingly, the metal pad 9 is provided in the recess 1a of the insulating base 1 in which the semiconductor integrated circuit element 3 is mounted.
It is preferable that the metal ball 10 attached to the region facing the metal pad 9 and the metal pad 9 is formed of copper having excellent thermal conductivity.

【0028】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹所1a底面に半導体集積回路
素子3 を接着剤を介して接着固定するとともに半導体集
積回路素子3 の各電極をメタライズ配線層5 にボンディ
ングワイヤ6 を介して電気的に接続し、しかる後、絶縁
基体1 の上面に蓋体2 をガラス、樹脂等から成る封止材
により接合させ、絶縁基体1 と蓋体2 とから成る容器4
内部に半導体集積回路素子3 を気密に封止することによ
って製品としての半導体装置となる。
Thus, according to the package for accommodating a semiconductor element of the present invention, the semiconductor integrated circuit element 3 is bonded and fixed to the bottom of the recess 1a of the insulating base 1 with an adhesive, and each electrode of the semiconductor integrated circuit element 3 is metallized. It is electrically connected to the layer 5 via bonding wires 6, and then the lid 2 is joined to the upper surface of the insulating base 1 with a sealing material made of glass, resin, or the like. Container consisting of 4
A semiconductor device as a product is obtained by hermetically sealing the semiconductor integrated circuit element 3 inside.

【0029】また前記半導体装置は絶縁基体1 下面の端
子7 を外部電気回路基板8 の配線導体8aに接合させるこ
とによって外部電気回路基板8 上に実装され、同時に容
器4の内部に収容されている半導体集積回路素子3 はそ
の各電極がボンディングワイヤ6 、メタライズ配線層5
、接続パッド5a及び端子7 を介して外部電気回路基板8
の配線導体8aに電気的に接続される。
The semiconductor device is mounted on the external electric circuit board 8 by joining the terminals 7 on the lower surface of the insulating base 1 to the wiring conductors 8 a of the external electric circuit board 8, and is housed inside the container 4 at the same time. In the semiconductor integrated circuit device 3, each electrode has a bonding wire 6, a metallized wiring layer 5
, The external electric circuit board 8 via the connection pad 5a and the terminal 7
Is electrically connected to the wiring conductor 8a.

【0030】[0030]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁基体下面の凹部底面に接続パッドを設ける
とともに、該接続パッドに絶縁基体の下面に球状の突出
部を有する半田から成る端子を取着させたことから、半
導体素子収納用パッケージの内部に半導体集積回路素子
を収容するとともに外部電気回路基板に実装した場合、
半導体集積回路素子の作動時に発する熱が絶縁基体と外
部電気回路基板の両方に繰り返し印加され、半導体素子
収納用パッケージの絶縁基体と外部電気回路基板との間
に両者の熱膨張係数の相違に起因する大きな熱応力が発
生したとしてもその熱応力は接続パッドの外周部と絶縁
基体の凹部開口領域に位置する端子の両方に分散され、
その結果、接続パッドが絶縁基体より剥離することはな
く、半導体素子収納用パッケージの内部に収容する半導
体集積回路素子の各電極を長期間にわたり所定の外部電
気回路に正確に電気的接続させることが可能となる。
According to the semiconductor device housing package of the present invention, connection pads are provided on the bottom surface of the concave portion on the lower surface of the insulating base, and the connection pads are provided with terminals made of solder having spherical projections on the lower surface of the insulating base. When the semiconductor integrated circuit device is housed inside the semiconductor device housing package and mounted on an external electric circuit board,
The heat generated during the operation of the semiconductor integrated circuit device is repeatedly applied to both the insulating substrate and the external electric circuit board, resulting from the difference in the coefficient of thermal expansion between the insulating substrate and the external electric circuit board of the package for housing the semiconductor element. Even if a large thermal stress occurs, the thermal stress is distributed to both the outer peripheral portion of the connection pad and the terminal located in the concave opening region of the insulating base,
As a result, the connection pads do not peel off from the insulating base, and each electrode of the semiconductor integrated circuit element housed in the semiconductor element housing package can be accurately and electrically connected to a predetermined external electric circuit for a long period of time. It becomes possible.

【0031】また本発明の半導体素子収納用パッケージ
によれば、絶縁基板の下面に金属パッドを形成し、且つ
該金属パッドに金属ボールを取着させたことから絶縁基
体下面の接続パッドにロウ付けされている端子を加熱溶
融させ、該端子を外部電気回路基板の配線導体に接合さ
せることによって半導体素子収納用パッケージを外部電
気回路基板上に実装させる際、絶縁基体と外部電気回路
基板との間には前記金属ボールによって所定の空隙が形
成されて加熱溶融した端子が半導体素子収納用パッケー
ジの重量が重いことにより押し潰されることは一切な
く、その結果、各端子を所定の外部電気回路に正確に電
気的接続することが可能になるとともに隣接する端子間
の電気的独立を維持することができる。
According to the semiconductor device housing package of the present invention, the metal pad is formed on the lower surface of the insulating substrate and the metal ball is attached to the metal pad. When the semiconductor device housing package is mounted on the external electric circuit board by heating and melting the terminal, and joining the terminal to the wiring conductor of the external electric circuit board, the gap between the insulating base and the external electric circuit board is reduced. A predetermined gap is formed by the metal ball, and the terminal melted by heating is not crushed at all by the heavy weight of the semiconductor element housing package. As a result, each terminal can be accurately connected to a predetermined external electric circuit. , And electrical independence between adjacent terminals can be maintained.

【0032】更に本発明の半導体素子収納用パッケージ
によれば、絶縁基体の半導体集積回路素子が載置される
載置部と対向する領域に金属パッドを形成しておき、且
つ該金属パッドに銅から成る金属ボールを取着しておく
と、半導体集積回路素子が作動時に多量の熱を発生した
際、その熱を金属ボールを介して外部電気回路基板、或
いは大気中に良好に放散させることができ、これによっ
て半導体集積回路素子は熱破壊や特性に劣化を招来する
ような高温になることは一切なく、半導体集積回路素子
を常に低温として長期間にわたり正常、且つ安定に作動
させることができる。
Further, according to the package for accommodating a semiconductor element of the present invention, a metal pad is formed in a region of the insulating substrate facing the mounting portion on which the semiconductor integrated circuit element is mounted, and the metal pad is formed on the metal pad. When the semiconductor integrated circuit element generates a large amount of heat during operation, the heat can be satisfactorily dissipated to the external electric circuit board or the atmosphere via the metal ball when the metal ball is attached. As a result, the semiconductor integrated circuit device does not reach a high temperature at which thermal destruction or deterioration of characteristics occurs, and the semiconductor integrated circuit device can be normally and stably operated at a low temperature for a long period of time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基体 2・・・・・・蓋体 3・・・・・・半導体集積回路素子 5・・・・・・メタライズ配線層 7・・・・・・端子 7a・・・・・端子の球状突出部 8・・・・・・外部電気回路基板 8a・・・・・外部電気回路基板の配線導体 9・・・・・・金属パッド 10・・・・・金属ボール DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor integrated circuit element 5 ... Metallized wiring layer 7 ... Terminal 7a ... ... Spherical protruding portion of terminal 8 ... External electric circuit board 8a ... Wiring conductor of external electric circuit board 9 ... Metal pad 10 ... Metal ball

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/00 - 23/30 H01L 21/56 H01L 21/60 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/00-23/30 H01L 21/56 H01L 21/60

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電気絶縁材料から成り、上面に半導体素子
が載置される載置部を、下面に多数の凹部を有する絶縁
基体と、前記絶縁基体の半導体素子が載置される載置部
周辺から凹部底面にかけて導出される複数個のメタライ
ズ配線層と、前記絶縁基体の凹部底面に形成され、メタ
ライズ配線層が電気的に接続される複数個の接続パッド
と、前記接続パッドに取着され、絶縁基体の下面に球状
の突出部を有する半田から成る端子と、前記絶縁基体の
下面に形成された金属パッドと、前記金属パッドに取着
された金属ボールとから成る半導体素子収納用パッケー
ジ。
An insulating base having an upper surface on which a semiconductor element is mounted, an insulating base having a plurality of concave portions on a lower surface, and a mounting part on which the semiconductor element of the insulating base is mounted. A plurality of metallized wiring layers extending from the periphery to the bottom surface of the concave portion, a plurality of connection pads formed on the bottom surface of the concave portion of the insulating base, and electrically connected to the metallized wiring layer; A semiconductor device package comprising: a terminal made of solder having a spherical projection on the lower surface of the insulating base; a metal pad formed on the lower surface of the insulating base; and a metal ball attached to the metal pad.
【請求項2】前記金属ボールを銅で形成し、且つ該金属
ボールが取着される金属パッドを、絶縁基体の半導体素
子が載置される載置部と対向する領域に形成したことを
特徴とする請求項1に記載の半導体素子収納用パッケー
ジ。
2. The semiconductor device according to claim 1, wherein the metal ball is formed of copper, and a metal pad to which the metal ball is attached is formed in a region of the insulating base opposite to the mounting portion on which the semiconductor element is mounted. The package for accommodating a semiconductor element according to claim 1.
JP30471894A 1994-12-08 1994-12-08 Package for storing semiconductor elements Expired - Fee Related JP3287965B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP30471894A JP3287965B2 (en) 1994-12-08 1994-12-08 Package for storing semiconductor elements
US08/567,949 US6225700B1 (en) 1994-12-08 1995-12-06 Package for a semiconductor element having depressions containing solder terminals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30471894A JP3287965B2 (en) 1994-12-08 1994-12-08 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH08162551A JPH08162551A (en) 1996-06-21
JP3287965B2 true JP3287965B2 (en) 2002-06-04

Family

ID=17936384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30471894A Expired - Fee Related JP3287965B2 (en) 1994-12-08 1994-12-08 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3287965B2 (en)

Also Published As

Publication number Publication date
JPH08162551A (en) 1996-06-21

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