JP2000340715A - Wiring board for mounting semiconductor element and semiconductor device using the same - Google Patents
Wiring board for mounting semiconductor element and semiconductor device using the sameInfo
- Publication number
- JP2000340715A JP2000340715A JP11151572A JP15157299A JP2000340715A JP 2000340715 A JP2000340715 A JP 2000340715A JP 11151572 A JP11151572 A JP 11151572A JP 15157299 A JP15157299 A JP 15157299A JP 2000340715 A JP2000340715 A JP 2000340715A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- mounting
- resin filler
- wiring board
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
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- Engineering & Computer Science (AREA)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線導体を有する
絶縁基体上に半導体素子をフリップチップ接続法により
搭載するようになした半導体素子搭載用配線基板および
この半導体素子搭載用配線基板に半導体素子をフリップ
チップ接続法により搭載するとともに半導体素子と絶縁
基体との間に樹脂製充填材を充填して成る半導体装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting a semiconductor element on a dielectric substrate having a wiring conductor by a flip-chip connection method, and a semiconductor element mounted on the wiring board for mounting a semiconductor element. And a semiconductor device in which a resin filler is filled between a semiconductor element and an insulating substrate.
【０００２】[0002]
【従来の技術】近時、コンピュータ等の電子機器の小型
化や薄型化に対応した半導体装置として、例えば酸化ア
ルミニウム質焼結体や窒化アルミニウム質焼結体・ムラ
イト質焼結体・炭化珪素質焼結体・窒化珪素質焼結体・
ガラスセラミックス等のセラミックスから成る絶縁基体
の上面中央部に半導体素子が搭載される搭載部を有する
とともにその搭載部から下面にかけて配線導体が配設さ
れて成る半導体素子搭載用配線基板を準備し、この半導
体素子搭載用配線基板の搭載部に半導体素子を半田や金
等から成るバンプを介してフリップチップ接続法により
搭載して、しかる後、この半導体素子と絶縁基体との間
にアンダーフィルと呼ばれる液状の樹脂製充填材を充填
するとともにこれを熱硬化させ、この熱硬化した樹脂製
充填材により半導体素子を保護するとともに絶縁基体と
半導体素子とを固着して成る半導体装置が知られてい
る。2. Description of the Related Art Recently, as a semiconductor device corresponding to miniaturization and thinning of electronic equipment such as a computer, for example, an aluminum oxide-based sintered body, an aluminum nitride-based sintered body, a mullite-based sintered body, and a silicon carbide-based material have been developed. Sintered body ・ Silicon nitride based sintered body ・
A semiconductor element mounting wiring board having a mounting portion on which a semiconductor element is mounted at the center of the upper surface of an insulating base made of ceramics such as glass ceramic and having wiring conductors arranged from the mounting portion to the lower surface is prepared. The semiconductor element is mounted on the mounting portion of the wiring board for mounting the semiconductor element via a bump made of solder, gold, or the like by a flip-chip connection method. Thereafter, a liquid called an underfill is placed between the semiconductor element and the insulating base. 2. Description of the Related Art There is known a semiconductor device in which a resin filler is filled and thermally cured, and the semiconductor element is protected by the thermally cured resin filler and the insulating base and the semiconductor element are fixed.
【０００３】なお、この半導体装置における半導体素子
搭載用配線基板は、いわゆるセラミックグリーンシート
積層法によって製作されている。具体的には、セラミッ
クス原料粉末を有機バインダで結合して成るセラミック
グリーンシートに適当な打ち抜き加工を施すとともに配
線導体となる金属ペーストを所定のパターンに印刷塗布
し、このセラミックグリーンシートを複数枚積層すると
ともに高温で焼成することによって製作されている。The wiring board for mounting the semiconductor element in this semiconductor device is manufactured by a so-called ceramic green sheet laminating method. Specifically, a ceramic green sheet formed by combining ceramic raw material powders with an organic binder is subjected to an appropriate punching process, and a metal paste serving as a wiring conductor is printed and applied in a predetermined pattern, and a plurality of the ceramic green sheets are laminated. And fired at a high temperature.
【０００４】しかしながら、この半導体装置によると、
半導体素子搭載用配線基板の搭載部に半導体素子を半田
や金から成るバンプを介してフリップチップ接続法によ
り搭載した後、絶縁基体と半導体素子との間に液状の樹
脂製充填材を充填することから、充填した液状の樹脂が
その流動性により絶縁基体上で樹脂製充填材が不要な部
分にまで流れ広がり、これが半導体装置としての機能に
悪影響を及ぼしたり、半導体装置の外観を著しく損ねた
りするという問題点があった。However, according to this semiconductor device,
After mounting the semiconductor element on the mounting portion of the wiring board for mounting the semiconductor element via a bump made of solder or gold by a flip chip connection method, filling a liquid resin filler between the insulating base and the semiconductor element. Therefore, the filled liquid resin flows due to its fluidity and spreads to portions where the resin filler is not required on the insulating substrate, which adversely affects the function as a semiconductor device or significantly impairs the appearance of the semiconductor device. There was a problem.
【０００５】そこで、上記問題点を解決するために、図
３に断面図で示すように、絶縁基体11の上面中央部に半
導体素子12がフリップチップ接続法により搭載される搭
載部11ａおよびこの搭載部11ａから下面に導出する配線
導体13を有するとともに、この搭載部11ａを取り囲むよ
うにして形成された所定高さの枠状のダム部14を有する
半導体素子搭載用配線基板を準備し、この半導体素子搭
載用配線基板の搭載部11ａに半導体素子12を半田や金等
から成るバンプ15を介してフリップチップ接続法により
搭載し、その後、ダム部14の内側で絶縁基体11と半導体
素子12との間に液状の樹脂製充填材16を充填し、これを
熱硬化させて成る半導体装置が提案されている。In order to solve the above problem, as shown in a sectional view of FIG. 3, a mounting portion 11a on which a semiconductor element 12 is mounted at the center of the upper surface of an insulating base 11 by a flip-chip connection method and a mounting portion 11a. A wiring board for mounting a semiconductor element having a wiring conductor 13 extending to the lower surface from the section 11a and having a frame-shaped dam section 14 of a predetermined height formed so as to surround the mounting section 11a is prepared. The semiconductor element 12 is mounted on the mounting part 11a of the element mounting wiring board by a flip-chip connection method via a bump 15 made of solder, gold, or the like, and then the insulating base 11 and the semiconductor element 12 are connected inside the dam part 14. There has been proposed a semiconductor device in which a liquid resin filler 16 is filled in between, and this is thermally cured.
【０００６】このような半導体装置によると、搭載部11
ａを取り囲むダム部14の内側で絶縁基体11と半導体素子
12との間に液状の樹脂製充填材16を充填すると、液状の
樹脂製充填材16が不要な部分にまで流れ広がるのがダム
部14により有効に防止される。According to such a semiconductor device, the mounting section 11
The insulating base 11 and the semiconductor element inside the dam portion 14 surrounding a
When the liquid resin filler 16 is filled in between the gap 12 and the liquid resin 12, the dam portion 14 effectively prevents the liquid resin filler 16 from flowing to and spreading to unnecessary portions.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上述の
半導体素子搭載用配線基板においては、ダム部14は通
常、枠状に打ち抜いたセラミックグリーンシートを半導
体素子搭載用配線基板となるセラミックグリーンシート
の積層体の最上層に積層し、それを焼成することによっ
て搭載部11ａを取り囲むように形成されている。However, in the above-mentioned wiring board for mounting a semiconductor element, the dam portion 14 is usually formed by laminating a ceramic green sheet punched in a frame shape into a ceramic green sheet serving as a wiring board for mounting a semiconductor element. It is formed so as to surround the mounting portion 11a by being laminated on the uppermost layer of the body and firing it.
【０００８】このようにして形成されたダム部14は、セ
ラミックグリーンシートを打ち抜き、これを焼成するこ
とにより形成されていることから、その内側の側面が絶
縁基体11の上面に対して略垂直となっている。The dam portion 14 thus formed is formed by punching out a ceramic green sheet and firing the same, so that the inner side surface is substantially perpendicular to the upper surface of the insulating base 11. Has become.
【０００９】そして、このダム部14の内側で絶縁基体11
と半導体素子12との間に液状の樹脂製充填材16を充填し
てこの樹脂製充填材16を熱硬化させると、樹脂製充填材
16が熱硬化する際に収縮することによりダム部14と樹脂
製充填材16との間に大きな引っ張り応力が発生する。The insulating substrate 11 is provided inside the dam portion 14.
A liquid resin filler 16 is filled between the semiconductor element 12 and the resin filler 16 and the resin filler 16 is cured by heat.
A large tensile stress is generated between the dam portion 14 and the resin filler 16 due to the shrinkage of the 16 when it is thermally cured.
【００１０】さらに、絶縁基体11を形成するセラミック
スの熱膨張係数が４×10-6〜10×10-6／℃程度であるの
に対して樹脂製充填材16の熱膨張係数が30×10-6〜50×
10-6／℃程度であり、両者の熱膨張係数が大きく相違す
ることから、半導体素子12を作動させると、その作動時
に発生する熱により絶縁基体11と樹脂製充填材16との間
に両者の熱膨張係数の相違に起因して大きな熱応力が発
生する。Further, the thermal expansion coefficient of the ceramic forming the insulating base 11 is about 4 × 10 −6 to 10 × 10 −6 / ° C., while the thermal expansion coefficient of the resin filler 16 is 30 × 10 6 -6 to 50 ×
When the semiconductor element 12 is operated, the heat generated during the operation causes the insulating substrate 11 and the resin filler 16 to have a large thermal expansion coefficient of about 10 −6 / ° C. Large thermal stress is generated due to the difference in the thermal expansion coefficients of the two.
【００１１】このような応力は、互いに重畳してダム部
14と樹脂製充填材16との接合面に対して作用し、この応
力が最も集中する部位であるダム部14と樹脂製充填材16
との接合面の上端部からダム部14と樹脂製充填材16との
間に剥離を発生させる。なお、ダム部14と樹脂製充填材
16との間に作用する応力は、ダム部14と樹脂製充填材16
との接合面に対して垂直な方向に作用する成分が大きい
程、ダム部14と樹脂製充填材16とを引き剥がす力が大き
くなるのでダム部14と樹脂製充填材16とが剥離しやすく
なる。Such stresses are superimposed on each other, and
Acts on the joint surface between the resin filler 16 and the resin filler 16, where the stress is most concentrated, the dam portion 14 and the resin filler 16.
Separation occurs between the dam portion 14 and the resin filler 16 from the upper end of the joining surface with the resin. The dam 14 and the resin filler
The stress acting between the dam 16 and the resin filler 16
The larger the component acting in the direction perpendicular to the joining surface with the larger, the greater the force to peel off the dam portion 14 and the resin filler 16, so that the dam portion 14 and the resin filler 16 are easily separated. Become.
【００１２】そして、ダム部14と樹脂製充填材16との間
に剥離が発生すると、半導体素子12の作動および停止の
繰り返しに伴って、この剥離が次第に絶縁基体11の中心
部に向かって徐々に進行していき、ついには樹脂製充填
材16が絶縁基体11から完全に剥離してしまい、半導体素
子12を良好に保護することができなくなってしまうとい
う問題点があった。また、半導体素子12の電極と半導体
素子搭載用配線基板の配線導体13とを接合している半田
や金等の接続用バンプ15の剥離を誘発させることによっ
て、半導体素子12の電極と絶縁基体11の配線導体13との
電気的な接続が切断され、その結果、半導体素子12を長
期間にわたり安定に作動させることができなくなってし
まうという問題点を有していた。When peeling occurs between the dam portion 14 and the resin filler 16, the peeling gradually proceeds toward the center of the insulating base 11 as the operation and stop of the semiconductor element 12 are repeated. As a result, the resin filler 16 is completely peeled off from the insulating base 11 and the semiconductor element 12 cannot be protected well. Further, by inducing peeling of connection bumps 15 such as solder or gold joining the electrodes of the semiconductor element 12 and the wiring conductors 13 of the wiring board for mounting the semiconductor element, the electrodes of the semiconductor element 12 and the insulating base 11 are separated. The electrical connection with the wiring conductor 13 is cut off, and as a result, the semiconductor element 12 cannot be operated stably for a long period of time.
【００１３】本発明は上記問題点に鑑み案出されたもの
であり、その目的は、絶縁基体と半導体素子とを樹脂製
充填材により強固に固着させ、半導体素子を良好に保護
するとともに半導体素子の電極と配線導体との電気的な
接続を完全なものとして半導体素子を長期間にわたり安
定に作動させることができる半導体素子搭載用配線基板
およびこれを用いた半導体装置を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to firmly fix an insulating substrate and a semiconductor element with a resin filler to protect the semiconductor element well and to improve the semiconductor element. It is an object of the present invention to provide a wiring board for mounting a semiconductor element and a semiconductor device using the same, in which the electrical connection between the electrode and the wiring conductor can be completed and the semiconductor element can be operated stably for a long period of time.
【００１４】[0014]
【課題を解決するための手段】本発明の半導体素子搭載
用配線基板は、配線導体が配設されたセラミックスから
成る絶縁基体上に、半導体素子がフリップチップ接続法
により搭載される搭載部およびこの搭載部を取り囲むよ
うにして形成された枠状のダム部を有する半導体素子搭
載用配線基板であって、前記ダム部は、複数層のセラミ
ック厚膜を積層して成り、その内側の側面が階段状また
は傾斜面となっていることを特徴とするものである。According to the present invention, there is provided a wiring board for mounting a semiconductor device, comprising: a mounting portion on which a semiconductor device is mounted by a flip-chip connection method on an insulating base made of ceramic on which wiring conductors are provided; A wiring board for mounting a semiconductor element having a frame-shaped dam portion formed so as to surround a mounting portion, wherein the dam portion is formed by laminating a plurality of ceramic thick films, and an inner side surface thereof has a step. It is characterized by having a shape or an inclined surface.
【００１５】また、本発明の半導体装置は、配線導体が
配設されたセラミックスから成る絶縁基体上に、半導体
素子がフリップチップ接続法により搭載される搭載部お
よびこの搭載部を取り囲むようにして形成された枠状の
ダム部を有する半導体素子搭載用配線基板と、搭載部に
フリップチップ接続法により搭載された半導体素子と、
ダム部の内側で絶縁基体と半導体素子との間に充填され
た樹脂製充填材とから成る半導体装置であって、前記ダ
ム部は、複数層のセラミック厚膜を積層して成り、その
内側の側面が階段状または傾斜面となっていることを特
徴とするものである。Further, the semiconductor device of the present invention is formed on an insulating base made of ceramics on which wiring conductors are provided, on which a semiconductor element is mounted by a flip-chip connection method, and is formed so as to surround the mounting part. A wiring board for mounting a semiconductor element having a frame-shaped dam part, a semiconductor element mounted on the mounting part by a flip-chip connection method,
A semiconductor device comprising a resin filler filled between an insulating base and a semiconductor element inside a dam portion, wherein the dam portion is formed by laminating a plurality of ceramic thick films, It is characterized in that the side surface is stepped or inclined.
【００１６】本発明の半導体素子搭載用配線基板および
半導体装置によれば、前記ダム部は、複数層のセラミッ
ク厚膜を積層して成り、その内側の側面が階段状または
傾斜面となっていることから、絶縁基体の搭載部に半導
体素子をフリップチップ接続法により搭載した後、ダム
部の内側で絶縁基体と半導体素子との間に液状の樹脂製
充填材を充填し、これを熱硬化させた後、樹脂製充填材
の硬化時の収縮による応力や半導体素子が作動時に発生
する熱による応力がダム部と樹脂製充填材との間に印加
されたとしても、その応力は階段状または傾斜面となっ
ているダム部の内側の側面によりダム部と樹脂製充填材
との接合面に対して垂直方向に作用する成分が良好に低
減分散されるため、ダム部と樹脂製充填材との間に剥離
が発生することを有効に防止することができる。According to the wiring board for mounting a semiconductor element and the semiconductor device of the present invention, the dam portion is formed by laminating a plurality of ceramic thick films, and the inner side surface is stepped or inclined. Therefore, after the semiconductor element is mounted on the mounting portion of the insulating base by the flip-chip connection method, a liquid resin filler is filled between the insulating base and the semiconductor element inside the dam portion, and this is thermally cured. Then, even if stress due to shrinkage of the resin filler during curing or heat generated during operation of the semiconductor element is applied between the dam portion and the resin filler, the stress is stepwise or inclined. The components acting in the direction perpendicular to the joint surface between the dam portion and the resin filler are reduced and dispersed satisfactorily by the inner side surface of the dam portion that is a surface, so that the dam portion and the resin filler That separation occurs between It is possible to prevent the effect.
【００１７】[0017]
【発明の実施の形態】次に、本発明の半導体素子搭載用
配線基板および半導体装置について添付の図面を基にし
て詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a wiring board for mounting a semiconductor element and a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
【００１８】図１は、本発明の半導体素子搭載用配線基
板およびこれを用いた半導体装置の実施の形態の一例を
示す断面図である。図１において、１は絶縁基体、２は
配線導体、３はダム部、４は半導体素子、５は樹脂製充
填材である。これらのうち、絶縁基体１と配線導体２と
ダム部３とで本発明の半導体素子搭載用配線基板が構成
されており、この半導体素子搭載用配線基板と半導体素
子４および樹脂製充填材５とにより本発明の半導体装置
が構成されている。FIG. 1 is a sectional view showing an embodiment of a wiring board for mounting a semiconductor element and a semiconductor device using the same according to the present invention. In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a dam portion, 4 is a semiconductor element, and 5 is a resin filler. Of these, the insulating substrate 1, the wiring conductor 2, and the dam portion 3 constitute the wiring board for mounting a semiconductor element of the present invention, and the wiring board for mounting a semiconductor element, the semiconductor element 4, the resin filler 5, and the like. Constitutes the semiconductor device of the present invention.
【００１９】絶縁基体１は、例えば大きさが数ｍｍ〜数
ｃｍ角程度の略四角形の平板であり、酸化アルミニウム
質焼結体や窒化アルミニウム質焼結体・ムライト質焼結
体・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラ
ミックス等のセラミックスから形成されている。The insulating substrate 1 is, for example, a substantially rectangular flat plate having a size of several mm to several cm square, and is made of aluminum oxide sintered body, aluminum nitride sintered body, mullite sintered body, silicon carbide based material. It is formed of a ceramic such as a sintered body, a silicon nitride sintered body, and a glass ceramic.
【００２０】この絶縁基体１は、例えば酸化アルミニウ
ム質焼結体から成る場合であれば、酸化アルミニウム・
酸化珪素・酸化マグネシウム・酸化カルシウム等の原料
粉末に適当な有機バインダ・溶剤を添加混合して泥漿状
となすとともに、これを従来周知のドクタブレード法を
採用することによってシート状となすことによりセラミ
ックグリーンシートを得、このセラミックグリーンシー
トに適当な打ち抜き加工を施すとともに必要に応じて複
数枚を積層して生セラミック積層体となし、最後にこの
生セラミック体を還元雰囲気中、約1600℃の温度で焼成
することによって製作される。If the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, the insulating substrate 1 may be made of aluminum oxide.
A raw material powder such as silicon oxide, magnesium oxide, calcium oxide, etc. is mixed with an appropriate organic binder and solvent to form a slurry, which is formed into a sheet by adopting a conventionally known doctor blade method, thereby forming a ceramic. A green sheet is obtained, the ceramic green sheet is subjected to an appropriate punching process, and if necessary, a plurality of sheets are laminated to form a green ceramic laminate. Finally, the green ceramic body is heated at a temperature of about 1600 ° C. in a reducing atmosphere. It is manufactured by firing.
【００２１】絶縁基体１は、半導体素子４を支持するた
めの支持基板として機能し、その上面中央部に半導体素
子４を搭載するための搭載部１ａを有している。この搭
載部１ａには半導体素子４が半田や金から成るバンプ６
を介してフリップチップ接続法により搭載される。な
お、半導体素子４は、例えばシリコンやガリウム砒素等
の半導体材料から形成されている集積回路素子等の電子
回路用素子である。The insulating substrate 1 functions as a support substrate for supporting the semiconductor element 4, and has a mounting portion 1a for mounting the semiconductor element 4 at the center of the upper surface. The semiconductor element 4 has a bump 6 made of solder or gold on the mounting portion 1a.
Via a flip chip connection method. The semiconductor element 4 is an electronic circuit element such as an integrated circuit element formed of a semiconductor material such as silicon or gallium arsenide.
【００２２】そして半導体素子４の搭載部１ａへの搭載
は、半導体素子４の能動面に形成された入出力用の各電
極に半田や金から成るバンプ６を溶着や圧着により予め
取着させておくとともにこのバンプ６を後述する配線導
体２の搭載部１ａに導出した部位に当接させ、両者を溶
着や圧着により接合することによって行なわれる。The mounting of the semiconductor element 4 on the mounting portion 1a is performed by previously attaching a bump 6 made of solder or gold to each input / output electrode formed on the active surface of the semiconductor element 4 by welding or crimping. In addition, the bump 6 is brought into contact with a portion led out to the mounting portion 1a of the wiring conductor 2 to be described later, and the two are joined by welding or pressure bonding.
【００２３】半導体素子４が搭載される絶縁基体１の搭
載部１ａにはタングステンやモリブデン・銅・銀等の金
属粉末メタライズから成る配線導体２の一端部が導出し
ており、この配線導体２の他端部は絶縁基体１の内部を
介して絶縁基体１の下面に導出している。One end of a wiring conductor 2 made of metallized metal powder such as tungsten, molybdenum, copper, silver or the like is led out to a mounting portion 1a of the insulating base 1 on which the semiconductor element 4 is mounted. The other end extends to the lower surface of the insulating base 1 via the inside of the insulating base 1.
【００２４】この配線導体２は半導体素子４の各電極を
外部電気回路に電気的に接続するための導電路として機
能し、上述したように、その搭載部１ａに導出した部位
には半導体素子４の各電極が半田や金等の接続用バンプ
６を介して電気的に接続される。また、配線導体２の絶
縁基体１の下面に導出した他端部は、図示しない外部電
気回路基板の接続用導体に半田等を介して接続され、こ
れによって、半導体素子４の各電極が外部の電気回路に
接続されることとなる。The wiring conductor 2 functions as a conductive path for electrically connecting each electrode of the semiconductor element 4 to an external electric circuit. As described above, the portion led out to the mounting portion 1a has the semiconductor element 4 Are electrically connected via connection bumps 6 such as solder and gold. The other end of the wiring conductor 2 led out to the lower surface of the insulating base 1 is connected to a connection conductor of an external electric circuit board (not shown) via solder or the like, whereby each electrode of the semiconductor element 4 is connected to an external device. It will be connected to an electric circuit.
【００２５】このような配線導体２は、例えばタングス
テンメタライズから成る場合であれば、タングステン粉
末に適当な有機バインダ・溶剤を添加混合して得た金属
ペーストを絶縁基体１となるセラミックグリーンシート
に従来周知のスクリーン印刷法を採用して所定のパター
ンに印刷塗布し、これをセラミックグリーンシートとと
もに焼成することによって、絶縁基体１の搭載部１ａか
ら下面に導出するようにして所定のパターンに被着形成
される。なお、配線導体２の表面には、通常、この配線
導体２が酸化腐食するのを防止するとともに配線導体２
とバンプ６との接続および配線導体２の外部電気回路基
板の接続用導体との半田を介した接続を容易かつ強固な
ものとするために、ニッケルめっき膜および金めっき膜
が順次被着されている。If such a wiring conductor 2 is made of, for example, tungsten metallization, a metal paste obtained by adding and mixing an appropriate organic binder and solvent to tungsten powder is conventionally applied to a ceramic green sheet serving as an insulating substrate 1. A well-known screen printing method is used to print and apply a predetermined pattern, which is baked together with the ceramic green sheet, so as to be led out from the mounting portion 1a of the insulating base 1 to the lower surface and adhere to the predetermined pattern. Is done. Note that the surface of the wiring conductor 2 is usually prevented from being oxidized and corroded,
A nickel plating film and a gold plating film are sequentially applied in order to easily and firmly connect the wiring conductor 2 to the bump 6 and the connection between the wiring conductor 2 and the connection conductor of the external electric circuit board via solder. I have.
【００２６】また、絶縁基体１の搭載部１ａに半導体素
子４をバンプ６を介してフリップチップ接続法により搭
載した後は、後述するダム部３の内側で絶縁基体１と半
導体素子４との間に例えばエポキシ樹脂から成る樹脂製
充填材５が液状で充填された後、熱硬化されて半導体装
置が完成する。After the semiconductor element 4 is mounted on the mounting portion 1a of the insulating substrate 1 via the bump 6 by the flip-chip connection method, the semiconductor element 4 is placed between the insulating substrate 1 and the semiconductor element 4 inside the dam portion 3 described later. After a resin filler 5 made of, for example, an epoxy resin is filled in a liquid state, the resin is thermally cured to complete a semiconductor device.
【００２７】この樹脂製充填材５は、その厚さが例えば
数十μｍ〜数百μｍ程度であり、絶縁基体１と半導体素
子４との間に充填されることにより、半導体素子４を保
護するとともに半導体素子４を絶縁基体１に強固に固着
させる作用をなす。また、半導体装置の仕様に応じて、
熱膨張率の調整や熱伝導性向上のための各種フィラーを
含有してもよい。The resin filler 5 has a thickness of, for example, about several tens μm to several hundred μm, and protects the semiconductor element 4 by being filled between the insulating base 1 and the semiconductor element 4. At the same time, it acts to firmly fix the semiconductor element 4 to the insulating base 1. Also, according to the specifications of the semiconductor device,
Various fillers for adjusting the coefficient of thermal expansion and improving the thermal conductivity may be contained.
【００２８】なお、絶縁基体１と半導体素子４との間へ
の液状の樹脂製充填材６の充填は、例えば従来周知のデ
ィスペンサを用いて行なえばよい。また、樹脂製充填材
５の熱硬化は、例えばオーブン等により100 〜150 ℃の
温度に加熱することにより行なえばよい。The filling of the liquid resin filler 6 between the insulating base 1 and the semiconductor element 4 may be performed using, for example, a conventionally well-known dispenser. The thermosetting of the resin filler 5 may be performed by heating the resin filler 5 to a temperature of 100 to 150 ° C. in an oven or the like.
【００２９】さらに、絶縁基体１の上面外周部には、搭
載部１ａを取り囲むようにして枠状のダム部３が形成さ
れている。Further, a frame-shaped dam portion 3 is formed on the outer peripheral portion of the upper surface of the insulating base 1 so as to surround the mounting portion 1a.
【００３０】ダム部３は、例えば酸化アルミニウム質焼
結体や窒化アルミニウム質焼結体・ムライト質焼結体・
炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミッ
クス等のセラミックスから成る５層の厚膜３ａ〜３ｅを
その内側の側面が階段状となるように積層して成る。そ
して、絶縁基体１の搭載部１ａに半導体素子４をバンプ
６を介してフリップチップ接続法により搭載した後、絶
縁基体１と半導体素子４との間に液状の樹脂製充填材５
を充填する際に、液状の樹脂製充填材５がその流動性に
より絶縁基体１上で樹脂製充填材５が不要な部分にまで
流れ広がるのを防止する作用をなす。The dam portion 3 is made of, for example, an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
It is formed by laminating five layers of thick films 3a to 3e made of ceramics such as a silicon carbide sintered body, a silicon nitride sintered body, and a glass ceramic so that the inner side surfaces are stepped. After the semiconductor element 4 is mounted on the mounting portion 1a of the insulating base 1 by the flip-chip connection method via the bumps 6, a liquid resin filler 5 is provided between the insulating base 1 and the semiconductor element 4.
When the resin is filled, the liquid resin filler 5 acts to prevent the resin filler 5 from flowing to an unnecessary portion on the insulating substrate 1 due to its fluidity.
【００３１】このダム部３は、例えば５層のセラミック
厚膜３ａ〜３ｅをその内周面である内側の側面が階段状
となるように積層してなることから、絶縁基体１の搭載
部１ａに半導体素子４をバンプ６を介してフリップチッ
プ接続法により搭載し、絶縁基体１と半導体素子４との
間に液状の樹脂製充填材５を充填してこれを硬化させた
後、樹脂製充填材５の硬化時の収縮による応力や半導体
素子４が作動時に発生する熱による応力がダム部３と樹
脂製充填材５との間に印加されたとしても、その応力は
階段状となっているダム部３の内側の側面によりダム部
３と樹脂製充填材５との接合面に対して垂直方向に作用
する成分が良好に低減分散され、これによりダム部３と
樹脂製充填材５との間における剥離の発生を有効に防止
することができる。Since the dam portion 3 is formed by laminating, for example, five ceramic thick films 3a to 3e such that the inner side surface, which is the inner peripheral surface thereof, has a stepped shape, the mounting portion 1a of the insulating base 1 is formed. The semiconductor element 4 is mounted via a bump 6 by a flip-chip connection method, and a liquid resin filler 5 is filled between the insulating base 1 and the semiconductor element 4 and is cured. Even if stress due to shrinkage during curing of the material 5 or stress due to heat generated during operation of the semiconductor element 4 is applied between the dam portion 3 and the resin filler 5, the stress has a stepped shape. The component acting in the direction perpendicular to the joint surface between the dam portion 3 and the resin filler 5 is satisfactorily reduced and dispersed by the inner side surface of the dam portion 3. It is possible to effectively prevent the occurrence of peeling between spaces
【００３２】ダム部３は、例えばその幅が１〜10ｍｍ程
度であり、その高さが0.05〜0.5 ｍｍ程度である。そし
て、各セラミック厚膜３ａ〜３ｅの厚みは、それぞれ10
〜100 μｍ程度である。また、その内側の側面に形成さ
れる各段の幅は0.01〜１ｍｍ程度としておけばよい。The dam portion 3 has, for example, a width of about 1 to 10 mm and a height of about 0.05 to 0.5 mm. The thickness of each of the ceramic thick films 3a to 3e is 10
About 100 μm. Further, the width of each step formed on the inner side surface may be about 0.01 to 1 mm.
【００３３】なお、ダム部３は、その表面の中心線平均
粗さ（Ｒａ）をＲａ≧0.65μｍとしておくと、ダム部３
の表面の凹凸と樹脂製充填材５とが係止し合って両者を
さらに強固に接合させることが可能となる。したがっ
て、ダム部３は、その表面の中心線平均粗さ（Ｒａ）を
Ｒａ≧0.65μｍとしておくことが好ましい。If the center line average roughness (Ra) of the surface of the dam section 3 is set to Ra ≧ 0.65 μm, the dam section 3
The unevenness of the surface and the resin filler 5 are engaged with each other, so that the two can be more firmly joined. Therefore, it is preferable to set the center line average roughness (Ra) of the surface of the dam portion 3 to Ra ≧ 0.65 μm.
【００３４】一方、この中心線平均粗さ（Ｒａ）がＲａ
＞10μｍとなると、ダム部３をセラミック厚膜３ａ〜３
ｅで形成することが困難となる傾向にあり、またダム部
３の表面の微細な凹凸が樹脂性充填材５で十分に濡れな
い部分が生じる傾向もあるため、ダム部３の表面の中心
線平均粗さ（Ｒａ）はＲａ≦10μｍとしておくことが好
ましい。On the other hand, the center line average roughness (Ra) is Ra
> 10 μm, dam portion 3 is formed of ceramic thick film 3a-3
e tends to be difficult to form, and there is also a tendency for fine irregularities on the surface of the dam portion 3 to be insufficiently wet with the resinous filler 5, so that the center line of the surface of the dam portion 3 is formed. The average roughness (Ra) is preferably set to Ra ≦ 10 μm.
【００３５】さらに、ダム部３は、絶縁基体１と実質的
に同じ組成のセラミックスで形成しておくと、絶縁基体
１とダム部３との熱膨張係数が略同一となり、絶縁基体
１とダム部３とに例えば半導体素子４が作動時に発生す
る熱が繰り返し印加されたとしても、両者間に熱膨張係
数の相違に起因する熱応力が発生することはなく、ダム
部３に剥離やクラックが発生することを有効に防止でき
る。従って、ダム部３は絶縁基体１と実質的に同じ組成
のセラミックスで形成することが好ましい。Further, if the dam portion 3 is formed of ceramics having substantially the same composition as the insulating base 1, the thermal expansion coefficients of the insulating base 1 and the dam portion 3 become substantially the same, and the insulating base 1 and the dam 3 are formed. Even if heat generated when the semiconductor element 4 operates, for example, is repeatedly applied to the portion 3, thermal stress due to the difference in thermal expansion coefficient between the two does not occur, and peeling or cracking occurs in the dam portion 3. This can be effectively prevented. Therefore, it is preferable that the dam portion 3 is formed of ceramics having substantially the same composition as the insulating base 1.
【００３６】このようなダム部３は、例えば各セラミッ
ク厚膜３ａ〜３ｅが酸化アルミニウム質焼結体から成る
場合であれば、酸化アルミニウム・酸化珪素・酸化カル
シウム・酸化マグネシウム等の原料粉末に適当な有機バ
インダ・溶剤を添加混合して得たセラミックペースト
を、絶縁基体１となるセラミックグリーンシート上に従
来周知のスクリーン印刷法を採用して各セラミック厚膜
３ａ〜３ｂに対応した枠状のパターンとなるように順次
印刷して積層し、これをセラミックグリーンシートとと
もに焼成することによって絶縁基体１の上面の封止部１
ｂに所定の枠状に被着形成される。If the ceramic thick films 3a to 3e are made of an aluminum oxide sintered body, the dam portion 3 is suitable for a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide. A ceramic paste obtained by adding and mixing an organic binder and a solvent is formed on a ceramic green sheet serving as an insulating substrate 1 by using a conventionally known screen printing method to form a frame pattern corresponding to each of the ceramic thick films 3a to 3b. Are sequentially printed and laminated in such a manner that the sealing portion 1 on the upper surface of the insulating base 1 is fired together with the ceramic green sheets.
b is formed in a predetermined frame shape.
【００３７】なお、セラミックペーストをスクリーン印
刷法により印刷塗布するとともに、これを焼成すること
によって得られるダム部３の表面の表面粗さは、セラミ
ックグリーンシートを焼成して得られる絶縁基体１と比
較して粗いものとなりやすいため、中心線平均粗さ（Ｒ
ａ）でＲａ≧0.65μｍとなる表面粗さを容易に得ること
ができる。The surface roughness of the dam portion 3 obtained by printing and applying the ceramic paste by the screen printing method and firing it is compared with that of the insulating substrate 1 obtained by firing the ceramic green sheet. Center line average roughness (R
In a), a surface roughness satisfying Ra ≧ 0.65 μm can be easily obtained.
【００３８】また、絶縁基体１となるセラミックグリー
ンシート上に印刷された各セラミック厚膜３ａ〜３ｅと
なる各セラミックペーストは、その側面と上面との間が
セラミックペーストの表面張力に起因して丸みを呈した
ものとなり、この丸みによってもダム部３と樹脂製充填
材５との接合面に印加される応力を良好に分散すること
ができる。Each of the ceramic pastes forming the ceramic thick films 3a to 3e printed on the ceramic green sheet serving as the insulating base 1 has a rounded surface between the side surface and the upper surface due to the surface tension of the ceramic paste. The roundness can also satisfactorily disperse the stress applied to the joint surface between the dam portion 3 and the resin filler 5.
【００３９】かくして、本発明の半導体素子搭載用配線
基板および半導体装置によれば、樹脂製充填材５が絶縁
基体１上の不要な部分に流れ広がることがなく、かつ半
導体素子４を樹脂製充填材５により良好に保護すること
ができるとともに、半導体素子４の電極と絶縁基体１の
配線導体２との電気的な接続を完全なものとして半導体
素子４を長期間にわたり安定に作動させることができ
る。Thus, according to the semiconductor element mounting wiring board and the semiconductor device of the present invention, the resin filler 5 does not flow to unnecessary portions on the insulating base 1 and spreads, and the semiconductor element 4 is filled with the resin. The semiconductor element 4 can be favorably protected by the material 5, and the semiconductor element 4 can be operated stably for a long period of time by making the electrical connection between the electrode of the semiconductor element 4 and the wiring conductor 2 of the insulating base 1 perfect. .
【００４０】なお、本発明は上述の実施の形態の一例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば種々の変更は可能である。例えば、上述の実
施の形態の一例ではダム部３はその内側の側面が階段状
となっていたが、ダム部３は必ずしもその内側の側面が
階段状となっている必要はなく、例えば図２に要部拡大
断面図で示すように、ダム部３はその内側の側面が傾斜
面となっていてもよい。この場合であっても、樹脂製充
填材５の硬化時の収縮による応力や半導体素子４が作動
時に発生する熱による応力がダム部３と樹脂製充填材５
との間に印加されたとしても、その応力は傾斜面となっ
ているダム部３の内側の側面によりダム部３と樹脂製充
填材５との接合面に対して垂直方向に作用する成分が良
好に低減分散され、これによりダム部３と樹脂製充填材
５との間に剥離が発生することを有効に防止することが
できる。このような傾斜面は、ダム部３を構成する各セ
ラミック厚膜３ａ〜３ｅとなるセラミックペーストを絶
縁基体１となるセラミックグリーンシート上にスクリー
ン印刷法を採用して順次印刷塗布する際に、各セラミッ
ク厚膜３ａ〜３ｅとなるセラミックペーストの厚みと幅
ならびに粘度を適宜調整することによって形成可能であ
る。The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the example of the above-described embodiment, the inner side surface of the dam portion 3 is stepped, but the inner side surface of the dam portion 3 does not necessarily have to be stepped. As shown in the main part enlarged cross-sectional view, the inner side surface of the dam portion 3 may be an inclined surface. Even in this case, the stress caused by the shrinkage of the resin filler 5 during curing and the stress generated by the heat generated during operation of the semiconductor element 4 may cause the dam portion 3 and the resin filler 5.
Even if the stress is applied during the period, the component acting in the direction perpendicular to the joint surface between the dam portion 3 and the resin filler 5 is generated by the inner side surface of the dam portion 3 having the inclined surface. The dispersion is satisfactorily reduced and dispersed, whereby the occurrence of peeling between the dam portion 3 and the resin filler 5 can be effectively prevented. Such an inclined surface is formed when the ceramic paste forming the ceramic thick films 3a to 3e constituting the dam portion 3 is sequentially printed and applied on the ceramic green sheet serving as the insulating base 1 by using a screen printing method. It can be formed by appropriately adjusting the thickness, width, and viscosity of the ceramic paste that becomes the ceramic thick films 3a to 3e.
【００４１】さらに、上述の実施の形態の一例ではダム
部３は５層のセラミック厚膜３ａ〜３ｅを積層すること
によって形成されていたが、ダム部３は２〜４層のセラ
ミック厚膜を積層することによって形成されていてもよ
いし、さらには６層以上のセラミック厚膜を積層するこ
とによって形成されていてもよい。Further, in the above-described embodiment, the dam portion 3 is formed by laminating five ceramic thick films 3a to 3e. However, the dam portion 3 is formed of two to four ceramic thick films. It may be formed by laminating, or may be formed by laminating six or more ceramic thick films.
【００４２】[0042]
【発明の効果】本発明の半導体素子搭載用配線基板およ
び半導体装置によれば、絶縁基体に形成されたダム部が
複数層のセラミック厚膜を積層して成り、その内側の側
面が階段状または傾斜面となっていることから、絶縁基
体の搭載部に半導体素子をフリップチップ接続法により
搭載し、ダム部の内側で絶縁基体と半導体素子との間に
液状の樹脂製充填材を充填してこれを熱硬化させた後、
樹脂製充填材の硬化時の収縮による応力や半導体素子が
作動時に発生する熱による応力がダム部と樹脂製充填材
との間に印加されたとしても、その応力は階段状または
傾斜面となっているダム部の内側の側面によりダム部と
樹脂製充填材との接合面に対して垂直方向に作用する成
分が良好に低減分散されるため、ダム部と樹脂製充填材
との間における剥離の発生を有効に防止することがで
き、その結果、樹脂製充填材が絶縁基体上の不要な部分
に流れ広がることがなく、かつ半導体素子を樹脂製充填
材により良好に保護することができるとともに、半導体
素子の電極と絶縁基体の配線導体との電気的な接続を完
全なものとして半導体素子を長期間にわたり安定に作動
させることが可能となる。According to the semiconductor element mounting wiring board and the semiconductor device of the present invention, the dam portion formed on the insulating base is formed by laminating a plurality of ceramic thick films, and the inner side surface thereof has a step-like shape. Because of the inclined surface, the semiconductor element is mounted on the mounting part of the insulating base by the flip chip connection method, and a liquid resin filler is filled between the insulating base and the semiconductor element inside the dam part. After thermosetting this,
Even if stress due to shrinkage during curing of the resin filler or heat generated during operation of the semiconductor element is applied between the dam portion and the resin filler, the stress becomes stair-like or inclined. The components acting in the direction perpendicular to the joint surface between the dam portion and the resin filler are reduced and dispersed well by the inner side surface of the dam portion, so the separation between the dam portion and the resin filler is removed. Can be effectively prevented, and as a result, the resin filler does not flow to unnecessary portions on the insulating base and spreads, and the semiconductor element can be well protected by the resin filler. The electrical connection between the electrode of the semiconductor element and the wiring conductor of the insulating substrate is made complete, and the semiconductor element can be operated stably for a long period of time.
【図１】本発明の半導体素子搭載用配線基板およびこれ
を用いた半導体装置の実施の形態の一例を示す断面図で
ある。FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board for mounting a semiconductor element and a semiconductor device using the same according to the present invention.
【図２】本発明の半導体素子搭載用配線基板およびこれ
を用いた半導体装置の実施の形態の他の例を示す要部拡
大断面図である。FIG. 2 is a main part enlarged sectional view showing another example of the embodiment of the semiconductor element mounting wiring board and the semiconductor device using the same according to the present invention.
【図３】従来の半導体素子搭載用配線基板およびこれを
用いた半導体装置の断面図である。FIG. 3 is a cross-sectional view of a conventional wiring board for mounting a semiconductor element and a semiconductor device using the same.
１・・・・絶縁基体 １ａ・・・・搭載部 ２・・・・配線導体 ３・・・・ダム部 ４・・・・半導体素子 ５・・・・樹脂製充填材 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Mounting part 2 ... Wiring conductor 3 ... Dam part 4 ... Semiconductor element 5 ... Resin filler
Claims (4)
成る絶縁基体上に、半導体素子がフリップチップ接続法
により搭載される搭載部および該搭載部を取り囲むよう
にして形成された枠状のダム部を有する半導体素子搭載
用配線基板であって、前記ダム部は、複数層のセラミッ
ク厚膜を積層して成り、その内側の側面が階段状または
傾斜面となっていることを特徴とする半導体素子搭載用
配線基板。1. A mounting portion on which a semiconductor element is mounted by a flip-chip connecting method on a ceramic insulating substrate on which a wiring conductor is disposed, and a frame-shaped dam portion formed so as to surround the mounting portion. Wherein the dam portion is formed by laminating a plurality of ceramic thick films, and the inner side surface thereof has a stepped or inclined surface. Wiring board for mounting.
実質的に同じ組成のセラミックスから成り、その表面粗
さが中心線平均粗さ（Ｒａ）でＲａ≧0.65μｍであるこ
とを特徴とする請求項１記載の半導体素子搭載用配線基
板。2. The ceramic thick film is made of ceramics having substantially the same composition as the insulating base, and has a surface roughness of Ra ≧ 0.65 μm in center line average roughness (Ra). The wiring board for mounting a semiconductor element according to claim 1.
成る絶縁基体上に、半導体素子がフリップチップ接続法
により搭載される搭載部および該搭載部を取り囲むよう
にして形成された枠状のダム部を有する半導体素子搭載
用配線基板と、前記搭載部にフリップチップ接続法によ
り搭載された半導体素子と、前記ダム部の内側で前記絶
縁基体と前記半導体素子との間に充填された樹脂製充填
材とから成る半導体装置であって、前記ダム部は、複数
層のセラミック厚膜を積層して成り、その内側の側面が
階段状または傾斜面となっていることを特徴とする半導
体装置。3. A mounting portion on which a semiconductor element is mounted by a flip-chip connection method on a ceramic insulating substrate on which a wiring conductor is disposed, and a frame-shaped dam portion formed so as to surround the mounting portion. A semiconductor element mounting wiring board having: a semiconductor element mounted on the mounting part by a flip chip connection method; and a resin filler filled between the insulating base and the semiconductor element inside the dam part. Wherein the dam portion is formed by laminating a plurality of ceramic thick films, and an inner side surface thereof is stepped or inclined.
実質的に同じ組成のセラミックスから成り、その表面粗
さが中心線平均粗さ（Ｒａ）でＲａ≧0.65μｍであるこ
とを特徴とする請求項３記載の半導体装置。4. The ceramic thick film is made of a ceramic having substantially the same composition as the insulating substrate, and has a surface roughness Ra ≧ 0.65 μm in center line average roughness (Ra). The semiconductor device according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15157299A JP3618060B2 (en) | 1999-05-31 | 1999-05-31 | Wiring board for mounting semiconductor element and semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15157299A JP3618060B2 (en) | 1999-05-31 | 1999-05-31 | Wiring board for mounting semiconductor element and semiconductor device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000340715A true JP2000340715A (en) | 2000-12-08 |
| JP3618060B2 JP3618060B2 (en) | 2005-02-09 |
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ID=15521464
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15157299A Expired - Fee Related JP3618060B2 (en) | 1999-05-31 | 1999-05-31 | Wiring board for mounting semiconductor element and semiconductor device using the same |
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| Country | Link |
|---|---|
| JP (1) | JP3618060B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812068B2 (en) * | 1998-09-02 | 2004-11-02 | Micron Technology, Inc. | Semiconductor device encapsulators, methods of encapsulating semiconductor devices and methods of forming electronic packages |
| WO2006035541A1 (en) * | 2004-09-28 | 2006-04-06 | Rohm Co., Ltd. | Semiconductor device |
| JP2014220305A (en) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | Multilayer substrate and electronic device using the same, method of manufacturing electronic device |
| CN105870075A (en) * | 2015-01-22 | 2016-08-17 | 恒劲科技股份有限公司 | Substrate structure |
| US11164756B2 (en) * | 2017-06-09 | 2021-11-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having continously formed tapered protrusions |
| US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
-
1999
- 1999-05-31 JP JP15157299A patent/JP3618060B2/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812068B2 (en) * | 1998-09-02 | 2004-11-02 | Micron Technology, Inc. | Semiconductor device encapsulators, methods of encapsulating semiconductor devices and methods of forming electronic packages |
| US10818628B2 (en) | 2004-09-28 | 2020-10-27 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| US9721865B2 (en) | 2004-09-28 | 2017-08-01 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| KR101158139B1 (en) * | 2004-09-28 | 2012-06-19 | 로무 가부시키가이샤 | Semiconductor device |
| US8405227B2 (en) | 2004-09-28 | 2013-03-26 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| US8754535B2 (en) | 2004-09-28 | 2014-06-17 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| JP2006100385A (en) * | 2004-09-28 | 2006-04-13 | Rohm Co Ltd | Semiconductor device |
| US11355462B2 (en) | 2004-09-28 | 2022-06-07 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| US9117774B2 (en) | 2004-09-28 | 2015-08-25 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| US9831204B2 (en) | 2004-09-28 | 2017-11-28 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| US10522494B2 (en) | 2004-09-28 | 2019-12-31 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
| WO2006035541A1 (en) * | 2004-09-28 | 2006-04-06 | Rohm Co., Ltd. | Semiconductor device |
| JP2014220305A (en) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | Multilayer substrate and electronic device using the same, method of manufacturing electronic device |
| CN105870075A (en) * | 2015-01-22 | 2016-08-17 | 恒劲科技股份有限公司 | Substrate structure |
| US11164756B2 (en) * | 2017-06-09 | 2021-11-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having continously formed tapered protrusions |
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