JP3420362B2 - Semiconductor device mounting structure - Google Patents
Semiconductor device mounting structureInfo
- Publication number
- JP3420362B2 JP3420362B2 JP30471994A JP30471994A JP3420362B2 JP 3420362 B2 JP3420362 B2 JP 3420362B2 JP 30471994 A JP30471994 A JP 30471994A JP 30471994 A JP30471994 A JP 30471994A JP 3420362 B2 JP3420362 B2 JP 3420362B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- semiconductor device
- external electric
- electric circuit
- connection pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の外部電気回
路基板への実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor device on an external electric circuit board.
【０００２】[0002]
【従来の技術】従来、半導体素子、特にＬＳＩ（大規模
集積回路素子）等の半導体集積回路素子を収容するため
の半導体素子収納用パッケージは、一般にアルミナセラ
ミックス等の電気絶縁材料から成り、その上面略中央部
に半導体集積回路素子を収容するための凹所を有する絶
縁基体と、前記絶縁基体の凹所周辺から下面にかけて導
出されるタングステン、モリブデン等の高融点金属粉末
から成る複数個のメタライズ配線層と、前記絶縁基体の
下面に形成され、メタライズ配線層が電気的に接続され
る複数個の接続パッドと、前記接続パッドにロウ付け取
着される半田（共晶半田）から成る端子と、蓋体とから
構成されており、絶縁基体の凹所底面に半導体集積回路
素子をガラス、樹脂等から成る接着剤を介して接着固定
させ、半導体集積回路素子の各電極とメタライズ配線層
とをボンディングワイヤを介して電気的に接続させると
ともに絶縁基体上面に蓋体をガラス、樹脂等の封止材を
介して接合させ、絶縁基体と蓋体とから成る容器内部に
半導体集積回路素子を気密に封止することによって製品
としての半導体装置となる。2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, in particular, a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit Element) is generally made of an electrically insulating material such as alumina ceramics and has an upper surface. An insulating base having a recess for accommodating a semiconductor integrated circuit element in a substantially central portion, and a plurality of metallized wirings made of a refractory metal powder of tungsten, molybdenum or the like led out from the periphery of the recess of the insulating base to the lower surface. A layer, a plurality of connection pads formed on the lower surface of the insulating substrate and electrically connected to a metallized wiring layer, and terminals made of solder (eutectic solder) brazed and attached to the connection pads, It is composed of a lid and a semiconductor integrated circuit element is adhered and fixed to the bottom surface of the recess of the insulating substrate through an adhesive made of glass, resin, etc. Each electrode of the path element and the metallized wiring layer are electrically connected via a bonding wire, and a lid is joined to the upper surface of the insulating base through a sealing material such as glass or resin, and the insulating base and the lid are separated from each other. A semiconductor device as a product is obtained by hermetically sealing a semiconductor integrated circuit element inside the container.
【０００３】かかる半導体装置は絶縁基体下面の接続パ
ッドにロウ付けされている半田から成る端子を外部電気
回路基板の配線導体上に載置当接させ、しかる後、前記
端子を約200 〜250 ℃の温度で加熱溶融し、端子を配線
導体に接合させることによって外部電気回路基板上に実
装され、同時に半導体素子収納用パッケージの内部に収
容されている半導体集積回路素子はその各電極がメタラ
イズ配線層及び端子を介して外部電気回路に電気的に接
続されることとなる。In such a semiconductor device, terminals made of solder brazed to the connection pads on the lower surface of the insulating substrate are placed and abutted on the wiring conductors of the external electric circuit board, and then the terminals are heated to about 200 to 250 ° C. Each of the electrodes of the semiconductor integrated circuit element, which is mounted on the external electric circuit board by heating and melting at the temperature of the above and joining the terminals to the wiring conductor, and at the same time is accommodated inside the package for accommodating the semiconductor element, has a metallized wiring layer. And is electrically connected to the external electric circuit via the terminal.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、この従
来の半導体装置の外部電気回路基板への実装構造におい
ては、半導体集積回路素子を収容する半導体素子収納用
パッケージの絶縁基体がアルミナセラミックスから成
り、その熱膨張係数が約6.5 ×10-6/ ℃であるのに対
し、外部電気回路基板は一般にガラスエポキシ樹脂から
成り、その熱膨張係数が2 ×10-5/ ℃〜4 ×10-5/ ℃で
両者大きく相違することから半導体素子収納用パッケー
ジの内部に半導体集積回路素子を収容し、しかる後、外
部電気回路基板に実装した場合、半導体集積回路素子の
作動時に発する熱が絶縁基体と外部電気回路基板の両方
に繰り返し印加されると前記絶縁基体と外部電気回路基
板との間に両者の熱膨張係数の相違に起因する大きな熱
応力が発生するとともにこれが絶縁基体下面の接続パッ
ドの外周部、及び外部電気回路基板の配線導体と端子と
の接合界面に作用し、その結果、接続パッドが絶縁基体
より剥離したり、端子が配線導体より剥離したりし、半
導体素子収納用パッケージの内部に収容する半導体集積
回路素子の各電極を長期間にわたり所定の外部電気回路
に電気的に接続させることができないという欠点を有し
ていた。However, in the conventional mounting structure of the semiconductor device on the external electric circuit board, the insulating base of the semiconductor element housing package for housing the semiconductor integrated circuit element is made of alumina ceramics. While the coefficient of thermal expansion is about 6.5 × 10 -6 / ℃, the external electric circuit board is generally made of glass epoxy resin, the coefficient of thermal expansion is 2 × 10 -5 / ℃ ~ 4 × 10 -5 / ℃ Therefore, when the semiconductor integrated circuit device is housed inside the semiconductor device housing package and then mounted on the external electric circuit board, the heat generated during the operation of the semiconductor integrated circuit device is generated by the insulating substrate and the external electric power. When repeatedly applied to both of the circuit boards, a large thermal stress is generated between the insulating substrate and the external electric circuit board due to the difference in thermal expansion coefficient between the two, and this It acts on the outer peripheral portion of the connection pad on the lower surface of the insulating base and on the bonding interface between the wiring conductor and the terminal of the external electric circuit board, and as a result, the connection pad may peel off from the insulating base or the terminal may peel off from the wiring conductor. However, there is a drawback in that each electrode of the semiconductor integrated circuit element housed inside the semiconductor element housing package cannot be electrically connected to a predetermined external electric circuit for a long period of time.
【０００５】[0005]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半導体集積回路素子の各電極を長期間に
わたり所定の外部電気回路に強固に電気的接続すること
ができる半導体装置の実装構造を提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above drawbacks, and an object thereof is a semiconductor device capable of firmly electrically connecting each electrode of a semiconductor integrated circuit element to a predetermined external electric circuit for a long period of time. To provide the implementation structure of.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置の実
装構造は、下面に半田から成る端子が取着されている絶
縁基体と蓋体とから成る容器の内部に半導体素子を収容
した半導体装置を、配線導体を有する外部電気回路基板
上に、前記端子を前記配線導体に接合させることによっ
て実装して成る半導体装置の実装構造であって、前記端
子を、前記絶縁基体自体の下面に設けた凹部の底面に該
底面および前記凹部の開口と同じ面積で被着されている
接続パッドに、前記凹部の内部を充填するとともに前記
絶縁基体の下面と前記外部電気回路基板の上面との間に
球状の突出部が形成されるようにして取着し、且つ前記
接続パッドの面積より広い前記配線導体に対する前記端
子の接合面積を前記接続パッドの面積より広くしたこと
を特徴とするものである。SUMMARY OF THE INVENTION A semiconductor device mounting structure according to the present invention is a semiconductor device in which a semiconductor element is housed in a container composed of an insulating base body to which terminals made of solder are attached and a lid. A mounting structure of a semiconductor device, wherein the terminal is mounted on an external electric circuit board having a wiring conductor by joining the terminal to the wiring conductor, wherein the terminal is provided on a lower surface of the insulating substrate itself. A connection pad, which is attached to the bottom surface of the recess in the same area as the bottom surface and the opening of the recess, fills the inside of the recess and has a spherical shape between the lower surface of the insulating base and the upper surface of the external electric circuit board. And the bonding area of the terminal to the wiring conductor, which is larger than the area of the connection pad, is larger than the area of the connection pad. A.
【０００７】また本発明の半導体装置の実装構造は、上
記構成において、前記配線導体に対する前記端子の接合
面積が前記接続パッドの面積より２５％以上広いことを
特徴とするものである。Further, the mounting structure of the semiconductor device of the present invention is characterized in that, in the above-mentioned structure, the bonding area of the terminal to the wiring conductor is larger than the area of the connection pad by 25% or more.
【０００８】[0008]
【作用】本発明の半導体装置の実装構造によれば、半田
から成る端子を、半導体素子を収容する容器の絶縁基体
自体の下面に設けた凹部の底面にこの底面および凹部の
開口と同じ面積で被着されている接続パッドに、凹部の
内部を充填するとともに絶縁基体の下面と外部電気回路
基板の上面との間に球状の突出部が形成されるようにし
て取着させたことから、半導体装置を外部電気回路基板
上に実装させた後、半導体集積回路素子の作動時に発す
る熱が絶縁基体と外部電気回路基板の両方に繰り返し印
加され、絶縁基体と外部電気回路基板との間に両者の熱
膨張係数の相違に起因する大きな熱応力が発生したとし
ても、その熱応力は接続パッドの外周部と絶縁基体の下
面の凹部開口領域に位置する端子の両方に分散されて小
さくなり、その結果、接続パッドが絶縁基体より剥離す
ることはなく、容器内部に収容する半導体集積回路素子
の各電極を長期間にわたり所定の外部電気回路に正確、
且つ強固に電気的接続させることが可能となる。According to the mounting structure of the semiconductor device of the present invention, the terminals made of solder are formed on the bottom surface of the recess provided on the lower surface of the insulating base body of the container for housing the semiconductor element in the same area as the bottom surface and the opening of the recess. Since the connection pad which has been adhered is filled so as to fill the inside of the recess and a spherical projection is formed between the lower surface of the insulating base and the upper surface of the external electric circuit board, the semiconductor is attached. After the device is mounted on the external electric circuit board, heat generated during the operation of the semiconductor integrated circuit element is repeatedly applied to both the insulating base and the external electric circuit board, and the heat is generated between the insulating base and the external electric circuit board. Even if a large thermal stress is generated due to the difference in the thermal expansion coefficient, the thermal stress is dispersed to both the outer peripheral portion of the connection pad and the terminal located in the recess opening area of the lower surface of the insulating base, and becomes small. Not the connection pad is peeled off from the insulating base, precisely each electrode of the semiconductor integrated circuit device which accommodates the inner container over a long period of time to a predetermined external electric circuit,
In addition, it is possible to make a strong electrical connection.
【０００９】また同時に外部電気回路基板の接続パッド
の面積より広くなっている配線導体と端子との接合面積
を接続パッドの面積に比べ広くしたことから外部電気回
路基板の配線導体に対する端子の接合強度が極めて強い
ものとなり、その結果、絶縁基体と外部電気回路基板の
熱膨張係数の相違に起因する熱応力によって端子が配線
導体より剥離することはなく、これによっても容器内部
に収容する半導体集積回路素子の各電極を長期間にわた
り所定の外部電気回路に正確、且つ強固に電気的接続さ
せることが可能となる。At the same time, since the joint area between the wiring conductor and the terminal, which is wider than the area of the connection pad of the external electric circuit board, is made wider than the area of the connection pad, the joint strength of the terminal to the wiring conductor of the external electric circuit board is increased. As a result, the terminals do not separate from the wiring conductor due to the thermal stress caused by the difference in the thermal expansion coefficient between the insulating base and the external electric circuit board, and this also causes the semiconductor integrated circuit to be housed inside the container. It becomes possible to accurately and firmly electrically connect each electrode of the element to a predetermined external electric circuit for a long period of time.
【００１０】[0010]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１及び図２は本発明にかかる半導体装置の実装構
造の一実施例を示し、Ａは半導体装置、Ｂは外部電気回
路基板である。The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a mounting structure of a semiconductor device according to the present invention, in which A is a semiconductor device and B is an external electric circuit board.
【００１１】前記半導体装置Ａは半導体集積回路素子5
を、絶縁基体1 と蓋体2 とメタライズ配線層3 と端子4
とで形成される半導体素子収納用パッケージの内部に気
密に収容することによって形成され、前記半導体素子収
納用パッケージの絶縁基体1及び蓋体2 は半導体集積回
路素子5 を内部に気密に収容するための容器6 を構成す
る。The semiconductor device A is a semiconductor integrated circuit element 5
Insulating substrate 1, lid 2, metallized wiring layer 3 and terminals 4
Is formed by hermetically accommodating the inside of a semiconductor element accommodating package formed by and the insulating base 1 and the lid 2 of the semiconductor element accommodating package are for accommodating the semiconductor integrated circuit element 5 inside. Configure container 6 of.
【００１２】前記半導体素子収納用パッケージを形成す
る絶縁基体１はその上面中央部に半導体集積回路素子5
が載置収容される凹所１ａが設けてあり、該凹所１ａ底
面には半導体集積回路素子5 がガラス、樹脂等の接着剤
を介して接着固定される。The insulating substrate 1 forming the package for accommodating the semiconductor element has a semiconductor integrated circuit element 5 at the center of its upper surface.
Is provided with a recess 1a in which the semiconductor integrated circuit element 5 is mounted and accommodated, and the semiconductor integrated circuit element 5 is bonded and fixed to the bottom surface of the recess 1a via an adhesive such as glass or resin.
【００１３】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば酸化アルミニウム質焼結体から
成る場合は酸化アルミニウム、酸化珪素、酸化マグネシ
ウム、酸化カルシウム等の原料粉末に適当な有機バイン
ダー、可塑剤、溶剤を添加混合して泥漿物を作るととも
に該泥漿物をドクターブレード法やカレンダーロール法
を採用することによってグリーンシート（生シート）と
成し、しかる後、前記グリーンシートに適当な打ち抜き
加工を施すとともにこれを複数枚積層し、約1600℃の温
度で焼成することによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a glass ceramic sintered body. When it is made of an aluminum-based sintered body, it is made by adding and mixing an appropriate organic binder, plasticizer, and solvent to raw material powders of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. Green sheet (green sheet) by adopting the method or calender roll method, and then appropriately punching the green sheet and stacking multiple sheets and firing at a temperature of about 1600 ° C Produced by.
【００１４】また前記絶縁基体1は半導体集積回路素子5
が載置収容される凹所1aの周辺から下面にかけて複数個
のメタライズ配線層3が被着形成されており、更に前記
絶縁基体1の下面には図２に示すように絶縁基体1自体に
凹部1bが設けられており、該凹部1bの底面に前記メタラ
イズ配線層3が電気的に接続される接続パッド3aがこの
底面および凹部1bの開口と同じ面積で被着形成されてい
る。The insulating substrate 1 is a semiconductor integrated circuit device 5
A plurality of metallized wiring layers 3 are formed by adhering from the periphery of the recess 1a in which the parts are placed and accommodated to the lower surface. Further, the lower surface of the insulating base 1 is recessed in the insulating base 1 itself as shown in FIG. 1b is provided, and a connection pad 3a to which the metallized wiring layer 3 is electrically connected is formed on the bottom surface of the recess 1b in the same area as the bottom surface and the opening of the recess 1b.
【００１５】前記メタライズ配線層3 及び接続パッド3a
はタングステン、モリブデン、マンガン等の高融点金属
粉末から成り、タングステン等の高融点金属粉末に適当
な有機バインダー、可塑剤、溶剤を添加混合して得た金
属ペーストを絶縁基体1 となるグリーンシートに予め従
来周知のスクリーン印刷法により所定パターンに印刷塗
布しておくことによって絶縁基体1 の所定位置に所定パ
ターンに被着形成される。The metallized wiring layer 3 and the connection pad 3a
Is a refractory metal powder such as tungsten, molybdenum, manganese, etc., and a metal paste obtained by adding and mixing an appropriate organic binder, plasticizer, and solvent to refractory metal powder such as tungsten is used as a green sheet for the insulating substrate 1. By printing and applying a predetermined pattern in advance by a conventionally known screen printing method, the insulating substrate 1 is adhered and formed in a predetermined pattern at a predetermined position.
【００１６】前記メタライズ配線層3 は半導体集積回路
素子5 の各電極を後述する接続パッド3aに取着される端
子4 に電気的に接続させる作用を為し、絶縁基体1 の凹
所1a周辺に位置する領域には半導体集積回路素子5 の各
電極がボンディングワイヤ7を介して電気的に接続され
る。The metallized wiring layer 3 has a function of electrically connecting each electrode of the semiconductor integrated circuit element 5 to a terminal 4 attached to a connection pad 3a, which will be described later. Each electrode of the semiconductor integrated circuit element 5 is electrically connected to the located region via a bonding wire 7.
【００１７】また前記メタライズ配線層3と電気的に接
続されている接続パッド3aは絶縁基体1に端子4を取着す
る際の下地金属層として作用し、該接続パッド3aの表面
には半田（錫−鉛合金）から成る端子4が取着されて凹
部1bの内部を充填している。Further, the connection pad 3a electrically connected to the metallized wiring layer 3 acts as a base metal layer when the terminal 4 is attached to the insulating base 1, and the surface of the connection pad 3a is soldered ( A terminal 4 made of a tin-lead alloy) is attached to fill the inside of the recess 1b.
【００１８】更に前記接続パッド3aに取着されている端
子4 は絶縁基体1 の下面に球状の突出部4aを有してお
り、該球状の突出部4aを有する端子4 は半導体集積回路
素子5の各電極が接続されている接続パッド3aを外部電
気回路基板Ｂの配線導体8 に接続させるとともに半導体
装置Ａを外部電気回路基板Ｂ上に実装させる作用を為
す。Further, the terminal 4 attached to the connection pad 3a has a spherical protrusion 4a on the lower surface of the insulating substrate 1, and the terminal 4 having the spherical protrusion 4a is a semiconductor integrated circuit device 5 The connection pad 3a to which the respective electrodes are connected is connected to the wiring conductor 8 of the external electric circuit board B, and the semiconductor device A is mounted on the external electric circuit board B.
【００１９】前記絶縁基体1 、蓋体2 、メタライズ配線
層3 及び端子4 から成る半導体素子収納用パッケージは
絶縁基体1 の凹所1a底面に半導体集積回路素子5 をガラ
ス、樹脂、ロウ材等から成る接着剤を介して接着固定す
るとともに半導体集積回路素子5 の各電極をメタライズ
配線層3 にボンディングワイヤ7 を介して電気的に接続
し、しかる後、絶縁基体1 の上面に蓋体2 をガラス、樹
脂等から成る封止材により接合させ、絶縁基体1 と蓋体
2 とから成る容器6 内部に半導体集積回路素子5 を気密
に収容することによって半導体装置Ａとなる。The package for storing a semiconductor element, which comprises the insulating base 1, the lid 2, the metallized wiring layer 3 and the terminal 4, has a semiconductor integrated circuit element 5 on the bottom surface of the recess 1a of the insulating base 1 made of glass, resin, brazing material or the like. Then, each electrode of the semiconductor integrated circuit element 5 is electrically connected to the metallized wiring layer 3 via the bonding wire 7, and then the lid 2 is attached to the upper surface of the insulating substrate 1 by glass. Insulating base 1 and lid are joined by sealing material made of resin, resin, etc.
The semiconductor device A is obtained by hermetically housing the semiconductor integrated circuit element 5 in the container 6 composed of 2 and 5.
【００２０】また前記半導体装置Ａは絶縁基体1 下面の
接続パッド3aに取着されている半田から成る端子4 を外
部電気回路基板Ｂの配線導体8 上に載置当接させ、しか
る後、前記端子4 を約200 〜250 ℃の温度で加熱溶融
し、端子4 を配線導体8 に接合させることによって外部
電気回路基板Ｂ上に実装される。In the semiconductor device A, the terminals 4 made of solder attached to the connection pads 3a on the lower surface of the insulating substrate 1 are placed and abutted on the wiring conductors 8 of the external electric circuit board B, and thereafter, the terminals are contacted. The terminal 4 is mounted on the external electric circuit board B by heating and melting the terminal 4 at a temperature of about 200 to 250 ° C. and joining the terminal 4 to the wiring conductor 8.
【００２１】前記半導体装置Ａは端子4 が、絶縁基体1
の下面に設けた凹部1bの底面に被着されている接続パッ
ド3aに、絶縁基体1 下面に球状の突出部4aを形成するよ
うにして取着させたことから半導体装置Ａを外部電気回
路基板Ｂ上に実装させた後、半導体集積回路素子5 の作
動時に発する熱が絶縁基体1 と外部電気回路基板Ｂの両
方に繰り返し印加され、絶縁基体1 と外部電気回路基板
Ｂとの間に両者の熱膨張係数の相違に起因する大きな熱
応力が発生したとしてもその熱応力は接続パッド3aの外
周部と絶縁基体1 下面の凹部1b開口領域に位置する端子
4 の両方に分散されて小さくなり、その結果、接続パッ
ド3aが絶縁基体1 より剥離することはなく、容器6 内部
に収容する半導体集積回路素子5 の各電極をボンディン
グワイヤ7 、メタライズ配線層3 、接続パッド3a及び端
子4 を介して外部電気回路に長期間にわたり正確、且つ
強固に電気的接続させることができる。In the semiconductor device A, the terminal 4 has the insulating base 1
The semiconductor device A is attached to the connection pad 3a formed on the bottom surface of the concave portion 1b formed on the lower surface of the insulating substrate 1 so that the spherical projection 4a is formed on the lower surface of the insulating substrate 1. After being mounted on B, heat generated during the operation of the semiconductor integrated circuit element 5 is repeatedly applied to both the insulating base 1 and the external electric circuit board B, and the heat is generated between the insulating base 1 and the external electric circuit board B. Even if a large thermal stress is generated due to the difference in the thermal expansion coefficient, the thermal stress is generated in the outer peripheral portion of the connection pad 3a and the terminal located in the opening area of the concave portion 1b on the lower surface of the insulating substrate 1.
As a result, the connection pads 3a are not separated from the insulating substrate 1, and the electrodes of the semiconductor integrated circuit element 5 housed inside the container 6 are bonded to the bonding wires 7 and the metallized wiring layer 3 Therefore, it is possible to make accurate and strong electrical connection to the external electric circuit for a long period of time through the connection pad 3a and the terminal 4.
【００２２】更に前記半導体装置Ａが実装される外部電
気回路基板Ｂとしては例えば、ガラスエポキシ樹脂等の
電気絶縁材料から成り、その上面に銅等の良導電性材料
から成る配線導体8 が被着されている。Further, the external electric circuit board B on which the semiconductor device A is mounted is made of, for example, an electrically insulating material such as glass epoxy resin, and a wiring conductor 8 made of a good conductive material such as copper is attached to the upper surface thereof. Has been done.
【００２３】前記外部電気回路基板Ｂは半導体装置Ａを
支持する支持部材として作用し、また配線導体8 は半導
体装置Ａの半導体集積回路素子5 の各電極を所定の外部
電気回路に接続する作用を為す。The external electric circuit board B functions as a supporting member for supporting the semiconductor device A, and the wiring conductor 8 functions to connect each electrode of the semiconductor integrated circuit element 5 of the semiconductor device A to a predetermined external electric circuit. Do
【００２４】尚、前記上面に配線導体8 を有する外部電
気回路基板Ｂは例えば、ガラスエポキシ樹脂板の上面に
銅から成る箔を接着材を介して被着させ、しかる後、前
記銅箔をエッチング加工法により所定パターンに加工す
ることによって製作される。In the external electric circuit board B having the wiring conductors 8 on the upper surface thereof, for example, a foil made of copper is adhered to the upper surface of a glass epoxy resin plate with an adhesive, and then the copper foil is etched. It is manufactured by processing into a predetermined pattern by a processing method.
【００２５】また前記外部電気回路基板Ｂの上面に被着
されている配線導体8 は図２に示す如く、半導体装置Ａ
の絶縁基体1 下面に設けた凹部1bの底面に被着されてい
る接続パッド3aの面積より広くなっており、端子4 の配
線導体8 に対する接合面積が接続パッド3aの面積より広
くなっている。この場合、外部電気回路基板Ｂの配線導
体8 と端子4 との接合面積が接続パッド3aの面積に比べ
て広いことから外部電気回路基板Ｂの配線導体8 に対す
る端子4 の接合強度が極めて強いものとなり、その結
果、絶縁基体1 と外部電気回路基板Ｂの熱膨張係数の相
違に起因する熱応力によって端子4 が配線導体8 より剥
離することはなく、これによっても容器6内部に収容す
る半導体集積回路素子5 の各電極を長期間にわたり所定
の外部電気回路に正確、且つ強固に電気的接続させるこ
とが可能となる。The wiring conductor 8 attached to the upper surface of the external electric circuit board B is a semiconductor device A as shown in FIG.
The area of the connection pad 3a attached to the bottom surface of the concave portion 1b provided on the lower surface of the insulating base 1 is larger than that of the connection pad 3a, and the bonding area of the terminal 4 to the wiring conductor 8 is larger than the area of the connection pad 3a. In this case, since the joint area between the wiring conductor 8 of the external electric circuit board B and the terminal 4 is larger than the area of the connection pad 3a, the joint strength of the terminal 4 to the wiring conductor 8 of the external electric circuit board B is extremely strong. As a result, the terminal 4 is not separated from the wiring conductor 8 due to the thermal stress due to the difference in the thermal expansion coefficient between the insulating substrate 1 and the external electric circuit board B. The electrodes of the circuit element 5 can be accurately and firmly electrically connected to a predetermined external electric circuit for a long period of time.
【００２６】更に前記外部電気回路基板Ｂの上面に被着
されている配線導体8と端子4との接合面積を接続パッド
3aの面積に対し、２５％以上広いものになしておくと、
外部電気回路基板Ｂの配線導体8に対する端子4の接合強
度が端子4の配線導体8からの剥離を皆無とする極めて強
いものとなすことができる。従って、前記外部電気回路
基板Ｂの上面に被着されている配線導体8と端子4との接
合面積は接続パッド3aの面積に対し、２５％以上広いも
のとなしておくことが好ましい。Further, the connection area between the wiring conductor 8 and the terminal 4 attached to the upper surface of the external electric circuit board B is set to a connection pad.
If you make it 25% or more larger than the area of 3a,
The bonding strength of the terminal 4 to the wiring conductor 8 of the external electric circuit board B can be made extremely strong without any peeling of the terminal 4 from the wiring conductor 8. Therefore, it is preferable that the bonding area between the wiring conductor 8 and the terminal 4 attached to the upper surface of the external electric circuit board B is larger than the area of the connection pad 3a by 25% or more.
【００２７】また更に本発明は上述の実施例に限定され
るものではなく、本発明の要旨を逸脱しない範囲であれ
ば種々の変更は可能である。Further, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.
【００２８】[0028]
【発明の効果】本発明の半導体装置の実装構造によれ
ば、半田から成る端子を、半導体素子を収容する容器の
絶縁基体自体の下面に設けた凹部の底面にこの底面およ
び凹部の開口と同じ面積で被着されている接続パッド
に、凹部の内部を充填するとともに絶縁基体の下面と外
部電気回路基板の上面との間に球状の突出部が形成され
るようにして取着させたことから、半導体装置を外部電
気回路基板上に実装させた後、半導体集積回路素子の作
動時に発する熱が絶縁基体と外部電気回路基板の両方に
繰り返し印加され、絶縁基体と外部電気回路基板との間
に両者の熱膨張係数の相違に起因する大きな熱応力が発
生したとしても、その熱応力は接続パッドの外周部と絶
縁基体の下面の凹部開口領域に位置する端子の両方に分
散されて小さくなり、その結果、接続パッドが絶縁基体
より剥離することはなく、容器内部に収容する半導体集
積回路素子の各電極を長期間にわたり所定の外部電気回
路に正確、且つ強固に電気的接続させることが可能とな
る。According to the mounting structure of the semiconductor device of the present invention, the terminals made of solder are formed on the bottom surface of the concave portion provided on the lower surface of the insulating substrate itself of the container accommodating the semiconductor element in the same manner as the bottom surface and the opening of the concave portion. Since the connection pad, which is applied in an area, fills the inside of the recess and forms a spherical protrusion between the lower surface of the insulating substrate and the upper surface of the external electric circuit board, the connection pad is attached. After mounting the semiconductor device on the external electric circuit board, heat generated during the operation of the semiconductor integrated circuit element is repeatedly applied to both the insulating base and the external electric circuit board, so that the heat is generated between the insulating base and the external electric circuit board. Even if a large thermal stress occurs due to the difference in thermal expansion coefficient between the two, the thermal stress is dispersed to both the outer peripheral portion of the connection pad and the terminal located in the recess opening area of the lower surface of the insulating base, and becomes small. As a result, the connection pad does not peel off from the insulating substrate, and each electrode of the semiconductor integrated circuit element housed inside the container can be accurately and firmly electrically connected to a predetermined external electric circuit for a long period of time. Become.
【００２９】また同時に外部電気回路基板の接続パッド
の面積より広くなっている配線導体と端子との接合面積
を接続パッドの面積に比べ広くしたことから外部電気回
路基板の配線導体に対する端子の接合強度が極めて強い
ものとなり、その結果、絶縁基体と外部電気回路基板の
熱膨張係数の相違に起因する熱応力によって端子が配線
導体より剥離することはなく、これによっても容器内部
に収容する半導体集積回路素子の各電極を長期間にわた
り所定の外部電気回路に正確、且つ強固に電気的接続さ
せることが可能となる。At the same time, since the area of connection between the wiring conductor and the terminal, which is wider than the area of the connection pad of the external electric circuit board, is made wider than the area of the connection pad, the bonding strength of the terminal to the wiring conductor of the external electric circuit board is increased. As a result, the terminals do not separate from the wiring conductor due to the thermal stress caused by the difference in the thermal expansion coefficient between the insulating base and the external electric circuit board, and this also causes the semiconductor integrated circuit to be housed inside the container. It becomes possible to accurately and firmly electrically connect each electrode of the element to a predetermined external electric circuit for a long period of time.
【図１】本発明の半導体装置の実装構造を説明するため
の断面図である。FIG. 1 is a sectional view for explaining a mounting structure of a semiconductor device of the present invention.
【図２】図１の要部拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a main part of FIG.
１・・・・・・絶縁基体 １ｂ・・・・・凹部 ２・・・・・・蓋体 ３・・・・・・メタライズ配線層 ３ａ・・・・・接続パッド ４・・・・・・端子 ４ａ・・・・・端子の球状の突出部 ５・・・・・・半導体集積回路素子 ６・・・・・・容器 ８・・・・・・配線導体 Ａ・・・・・・半導体装置 Ｂ・・・・・・外部電気回路基板 1 ... Insulating substrate 1b ... Recess 2 ... Lid 3 ... Metallized wiring layer 3a ... Connection pad 4 ・ ・ Terminal 4a ... Spherical protrusion of terminal 5 ・ ・ Semiconductor integrated circuit device 6- ・ Container 8 ... Wiring conductor A: Semiconductor device B ... External electric circuit board
フロントページの続き (56)参考文献 特開 平８−111578（ＪＰ，Ａ) 特開 平３−250647（ＪＰ，Ａ) 特開 平２−248066（ＪＰ，Ａ) 特開 平６−85103（ＪＰ，Ａ) 特開 平６−112354（ＪＰ，Ａ) 特開 平８−97325（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 Continuation of the front page (56) Reference JP-A-8-111578 (JP, A) JP-A-3-250647 (JP, A) JP-A-2-248066 (JP, A) JP-A-6-85103 (JP , A) JP-A-6-112354 (JP, A) JP-A-8-97325 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12
Claims (2)
絶縁基体と蓋体とから成る容器内部に半導体素子を収容
した半導体装置を、配線導体を有する外部電気回路基板
上に、前記端子を前記配線導体に接合させることによっ
て実装して成る半導体装置の実装構造であって、前記端
子を、前記絶縁基体自体の下面に設けた凹部の底面に該
底面および前記凹部の開口と同じ面積で被着されている
接続パッドに、前記凹部の内部を充填するとともに前記
絶縁基体の下面と前記外部電気回路基板の上面との間に
球状の突出部が形成されるようにして取着し、且つ前記
接続パッドの面積より広い前記配線導体に対する前記端
子の接合面積を前記接続パッドの面積より広くしたこと
を特徴とする半導体装置の実装構造。1. A semiconductor device in which a semiconductor element is housed in a container composed of an insulating substrate having a terminal made of solder attached to a lower surface and a lid, and the terminal is mounted on an external electric circuit board having a wiring conductor. A mounting structure for a semiconductor device, wherein the terminals are mounted on the bottom surface of a recess provided on the lower surface of the insulating base itself in the same area as the bottom surface and the opening of the recess. The connection pad that has been adhered is attached so that the inside of the recess is filled and a spherical protrusion is formed between the lower surface of the insulating base and the upper surface of the external electric circuit board, and The above
A mounting structure for a semiconductor device, wherein a bonding area of the terminal to the wiring conductor, which is larger than an area of a connection pad, is larger than an area of the connection pad .
が前記接続パッドの面積より２５％以上広いことを特徴
とする請求項１に記載の半導体装置の実装構造。2. The mounting structure for a semiconductor device according to claim 1, wherein a bonding area of the terminal to the wiring conductor is larger than an area of the connection pad by 25% or more.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30471994A JP3420362B2 (en) | 1994-12-08 | 1994-12-08 | Semiconductor device mounting structure |
| US08/567,949 US6225700B1 (en) | 1994-12-08 | 1995-12-06 | Package for a semiconductor element having depressions containing solder terminals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30471994A JP3420362B2 (en) | 1994-12-08 | 1994-12-08 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08162565A JPH08162565A (en) | 1996-06-21 |
| JP3420362B2 true JP3420362B2 (en) | 2003-06-23 |
Family
ID=17936397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30471994A Expired - Fee Related JP3420362B2 (en) | 1994-12-08 | 1994-12-08 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3420362B2 (en) |
-
1994
- 1994-12-08 JP JP30471994A patent/JP3420362B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08162565A (en) | 1996-06-21 |
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