JP3210835B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP3210835B2 JP3210835B2 JP14050395A JP14050395A JP3210835B2 JP 3210835 B2 JP3210835 B2 JP 3210835B2 JP 14050395 A JP14050395 A JP 14050395A JP 14050395 A JP14050395 A JP 14050395A JP 3210835 B2 JP3210835 B2 JP 3210835B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- gold
- tungsten
- metallized
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.
【０００２】[0002]
【従来の技術】従来、半導体素子、特にＬＳＩ（大規模
集積回路素子）等の半導体素子を収容するための半導体
素子収納用パッケージは、一般に図２に示すように、酸
化アルミニウム質焼結体等の電気絶縁材料から成り、そ
の上面の略中央部に半導体素子を収容するための凹部21
ａを有する絶縁基体21と、前記絶縁基体21の凹部21ａ周
辺から下面にかけて導出されるタングステン、モリブデ
ン、マンガン等の高融点金属粉末から成る複数個のメタ
ライズ配線層22と、前記絶縁基体21の下面に形成され、
メタライズ配線層22が電気的に接続される複数個の接続
パッド23と、前記接続パッド23に取着される半田から成
るボール状端子24と、蓋体25とから構成されており、絶
縁基体21の凹部21ａ底面に配線層26をガラス、樹脂等か
ら成る接着剤を介して接着固定させ、半導体素子26の各
電極とメタライズ配線層22とをボンディングワイヤ27を
介して電気的に接続させるとともに、絶縁基体21上面に
蓋体25をガラス、樹脂等の封止材を介して接合させ、絶
縁基体21と蓋体25とから成る容器内部に半導体素子26を
気密に収容することによって製品としての半導体装置と
なる。2. Description of the Related Art Conventionally, as shown in FIG. 2, a package for accommodating a semiconductor element, particularly a semiconductor element such as an LSI (Large Scale Integrated Circuit) is generally made of an aluminum oxide sintered body as shown in FIG. A concave portion 21 for accommodating a semiconductor element in a substantially central portion of the upper surface thereof.
a, a plurality of metallized wiring layers 22 made of a refractory metal powder of tungsten, molybdenum, manganese, etc., drawn from the periphery to the lower surface of the concave portion 21a of the insulating substrate 21, and the lower surface of the insulating substrate 21 Formed in
The insulating substrate 21 includes a plurality of connection pads 23 to which the metallized wiring layer 22 is electrically connected, ball-shaped terminals 24 made of solder attached to the connection pads 23, and a lid 25. The wiring layer 26 is adhered and fixed to the bottom surface of the concave portion 21a via an adhesive made of glass, resin, or the like, and each electrode of the semiconductor element 26 and the metallized wiring layer 22 are electrically connected via the bonding wire 27. The lid 25 is joined to the upper surface of the insulating base 21 via a sealing material such as glass or resin, and the semiconductor element 26 is hermetically housed in a container formed of the insulating base 21 and the lid 25, thereby forming a semiconductor product. Device.
【０００３】かかる半導体装置は絶縁基体21下面の接続
パッド23に取着されている半田から成るボール状端子24
を外部電気回路基板28の配線導体29上に載置させ、しか
る後、前記ボール状端子24を約２００〜２５０℃の温度
で加熱溶融し、ボール状端子24を配線導体29に接合させ
ることによって外部電気回路基板28上に実装され、同時
に半導体素子収納用パッケージの内部に収容されている
半導体素子26はその各電極がメタライズ配線層22及びボ
ール状端子24を介して外部電気回路に接続されることと
なる。Such a semiconductor device has a ball-shaped terminal 24 made of solder attached to a connection pad 23 on the lower surface of an insulating base 21.
Is placed on the wiring conductor 29 of the external electric circuit board 28, and thereafter, the ball-shaped terminal 24 is heated and melted at a temperature of about 200 to 250 ° C., and the ball-shaped terminal 24 is joined to the wiring conductor 29. Each electrode of the semiconductor element 26 mounted on the external electric circuit board 28 and simultaneously accommodated inside the semiconductor element accommodation package is connected to the external electric circuit via the metallized wiring layer 22 and the ball-shaped terminals 24. It will be.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、半導体素
子が接着固定される絶縁基体が一般に酸化アルミニウム
質焼結体より成り、該酸化アルミニウム質焼結体はその
熱伝導率が約１６〜１８Ｗ／ｍ・Ｋ程度であることから
半導体素子が作動時に極めて多量の熱を発生すると該半
導体素子の発した熱が絶縁基体を介して外部に良好に放
出されず、半導体素子の内部に蓄積されてしまい、その
結果、半導体素子が高温となり、半導体素子に熱破壊や
特性に熱変化を招来させるという欠点を有していた。However, in this conventional package for housing a semiconductor element, the insulating substrate to which the semiconductor element is adhered and fixed is generally made of an aluminum oxide sintered body, and the aluminum oxide sintered body is Since the thermal conductivity is about 16 to 18 W / m · K, when the semiconductor device generates an extremely large amount of heat during operation, the heat generated by the semiconductor device is not satisfactorily released to the outside via the insulating base. However, they are accumulated inside the semiconductor element, and as a result, the temperature of the semiconductor element becomes high, so that the semiconductor element has a drawback of causing thermal destruction and a thermal change in characteristics.
【０００５】またこの従来の半導体素子収納用パッケー
ジにおいては、内部に収容する半導体素子の各電極がボ
ンディングワイヤを介してメタライズ配線層に電気的に
接続されるようになっており、近時の高密度化が急激に
進み電極の数が急増してきた半導体素子を収容した場
合、半導体素子の電極とメタライズ配線層とをボンディ
ングワイヤを介して電気的接続するのに長時間を必要と
し、その結果、半導体素子を収容する作業性が極めて悪
く、最終製品としての半導体装置を高価とする欠点も有
していた。Further, in this conventional semiconductor device housing package, each electrode of the semiconductor device housed therein is electrically connected to a metallized wiring layer via a bonding wire. When a semiconductor element in which the density has rapidly increased and the number of electrodes has rapidly increased is accommodated, it takes a long time to electrically connect the electrode of the semiconductor element and the metallized wiring layer via a bonding wire, and as a result, Workability for accommodating a semiconductor element is extremely poor, and there is a disadvantage that a semiconductor device as a final product is expensive.
【０００６】[0006]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に収容する半導体素子の各電極を所
定のメタライズ配線層に短時間に電気的接続することを
可能とし、且つ半導体素子の作動時に発する熱を外部に
良好に放出して半導体素子を長期間にわたり正常、且つ
安定に作動させることができる半導体素子収納用パッケ
ージを提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to make it possible to electrically connect each electrode of a semiconductor element housed therein to a predetermined metallized wiring layer in a short time. Another object of the present invention is to provide a package for housing a semiconductor element which can satisfactorily emit heat generated during operation of the semiconductor element to the outside and operate the semiconductor element normally and stably for a long period of time.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、上面に半導体素子を収容するための凹
部を有し、該凹部底面から下面にかけて半導体素子の各
電極がフリップチップ接続により接続されるタングステ
ンまたはモリブデンから成り１μｍ乃至２０μｍの厚み
のニッケルまたは金が被着された複数個のメタライズ配
線層、および下面に前記メタライズ配線層に電気的に接
続されたタングステンまたはモリブデンから成り１μｍ
乃至２０μｍの厚みのニッケルまたは金が被着された接
続パッド、ならびに前記凹部周辺の上面にタングステン
またはモリブデンから成り１μｍ乃至２０μｍの厚みの
ニッケルまたは金が被着された枠状のメタライズ金属層
を有する電気絶縁材料の焼結体から成る絶縁基体と、前
記絶縁基体の上面の前記メタライズ金属層に金−錫合金
から成る封止材を介して取着され、且つその下面に内部
に収容する半導体素子の一主面が当接する銅または銅−
タングステン合金から成る金属製蓋体とから成ることを
特徴とするものである。SUMMARY OF THE INVENTION A package for accommodating a semiconductor device according to the present invention has a concave portion for accommodating a semiconductor device on an upper surface, and each electrode of the semiconductor device is connected by flip-chip connection from the bottom surface to the lower surface of the concave portion. A plurality of metallized wiring layers made of tungsten or molybdenum and having a thickness of 1 μm to 20 μm and coated with nickel or gold;
A connection pad on which nickel or gold having a thickness of about 20 to 20 μm is provided, and a frame-shaped metallized metal layer made of tungsten or molybdenum and having nickel or gold having a thickness of 1 to 20 μm on the periphery of the recess. An insulating base made of a sintered body of an electrically insulating material, and a semiconductor element attached to the metallized metal layer on the upper surface of the insulating base via a sealing material made of a gold-tin alloy and housed inside the lower surface thereof Copper or copper that one main surface contacts
And a metal lid made of a tungsten alloy.
【０００８】[0008]
【作用】本発明の半導体素子収納用パッケージによれ
ば、電気絶縁材料の焼結体から成る絶縁基体の半導体素
子を収容する凹部底面にタングステンまたはモリブデン
から成り１μｍ乃至２０μｍの厚みのニッケルまたは金
が被着されたメタライズ配線層の一端を導出させたこと
から、該メタライズ配線層に半導体素子の各電極をフリ
ップチップ接続により接続することができ、その結果、
半導体素子の電極数が多いとしてもその全てを所定のメ
タライズ配線層に一度に接続することが可能となって半
導体素子の収容の作業性が極めて優れたものとなるとと
もに、半導体素子の電極との接続を強固となすことがで
きる。また、凹部周辺の上面にタングステンまたはモリ
ブデンから成り１μｍ乃至２０μｍの厚みのニッケルま
たは金が被着された枠状のメタライズ金属層を有するこ
とから、絶縁基体の上面に金−錫合金から成る封止材を
介して金属製蓋体を取着して内部に収容する半導体素子
を気密に封止することができる。さらに、下面にメタラ
イズ配線層に電気的に接続されたタングステンまたはモ
リブデンから成り１μｍ乃至２０μｍの厚みのニッケル
または金が被着された接続パッドを有することから、ボ
ール状端子を介して外部電気回路基板の配線導体に容
易、且つ確実に接続することができる。According to the semiconductor device housing package of the present invention, nickel or gold made of tungsten or molybdenum and having a thickness of 1 μm to 20 μm is formed on the bottom of the concave portion for housing the semiconductor element of the insulating base made of a sintered body of an electrically insulating material. Since one end of the applied metallized wiring layer is led out, each electrode of the semiconductor element can be connected to the metallized wiring layer by flip-chip connection.
Even if the number of electrodes of the semiconductor element is large, all of them can be connected to a predetermined metallized wiring layer at a time, and the workability of housing the semiconductor element is extremely excellent, and the connection with the electrode of the semiconductor element can be improved. The connection can be made strong. In addition, since a frame-shaped metallized metal layer made of tungsten or molybdenum and having a thickness of 1 μm to 20 μm and coated with nickel or gold is provided on the upper surface around the concave portion, the upper surface of the insulating base is sealed with a gold-tin alloy. It is possible to hermetically seal a semiconductor element housed inside by attaching a metal lid through a material. Furthermore, since the lower surface has connection pads made of tungsten or molybdenum electrically connected to the metallized wiring layer and coated with nickel or gold having a thickness of 1 μm to 20 μm, the external electric circuit board is connected via ball-shaped terminals. Can be easily and reliably connected to the wiring conductor.
【０００９】また本発明の半導体素子収納用パッケージ
によれば、銅または銅−タングステン合金から成る金属
製蓋体の下面が内部に収容する半導体素子の一主面に当
接することから、半導体素子が作動時に発する熱は金属
製蓋体を介して外部に良好に放出され、その結果、半導
体素子を常に適温として半導体素子を長期間にわたり正
常、且つ安定に作動させることができる。Further, according to the semiconductor device housing package of the present invention, the lower surface of the metal lid made of copper or copper-tungsten alloy is in contact with one main surface of the semiconductor device housed therein. The heat generated during operation is satisfactorily released to the outside through the metal lid, and as a result, the semiconductor element can always be kept at an appropriate temperature to operate normally and stably for a long period of time.
【００１０】[0010]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１は本発明の半導体素子収納用パッケージの一実
施例を示し、１は絶縁基体、２は金属製蓋体である。こ
の絶縁基体１と蓋体２とで半導体素子３を収容するため
の容器４が構成される。BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a metal lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.
【００１１】前記絶縁基体１はその上面中央部に半導体
素子３が収容される凹部１ａが設けてあり、該凹部１ａ
内には半導体素子３が固定収容されるようになってい
る。The insulating base 1 is provided with a recess 1a for accommodating the semiconductor element 3 in the center of the upper surface thereof.
The semiconductor element 3 is fixedly accommodated therein.
【００１２】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば酸化アルミニウム質焼結体から
成る場合、酸化アルミニウム、酸化珪素、酸化マグネシ
ウム、酸化カルシウム等の原料粉末に適当な有機バイン
ダー、溶剤等を添加混合して泥漿状となすとともにこれ
を従来周知のドクターブレード法やカレンダーロール法
等によりシート状に成形してセラミックグリーンシート
（セラミック生シート）を得、しかる後、前記セラミッ
クグリーンシートに適当な打ち抜き加工を施すとともに
これを複数枚積層し、高温（約１６００℃）で焼成する
ことによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. In the case of an aluminum sintered body, a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide is mixed with an appropriate organic binder, a solvent, and the like to form a slurry, which is then mixed with a conventionally known doctor blade method. A ceramic green sheet (ceramic green sheet) is obtained by forming the sheet into a sheet shape by, for example, a calender roll method or the like. Thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of the sheets are laminated, and a high temperature (about 1600 ° C.) ).
【００１３】また前記絶縁基体１は半導体素子３が収容
される凹部１ａの底面から下面にかけて複数個のメタラ
イズ配線層５が、更に絶縁基体１の下面に前記メタライ
ズ配線層５が電気的に接続される複数個の接続パッド６
が各々被着形成されている。The insulating substrate 1 has a plurality of metallized wiring layers 5 electrically connected from the bottom surface to the lower surface of the concave portion 1a in which the semiconductor element 3 is accommodated, and the metallized wiring layers 5 are further electrically connected to the lower surface of the insulating substrate 1. Connecting pads 6
Are respectively formed by adhesion.
【００１４】前記メタライズ配線層５及び接続パッド６
はタングステン、モリブデン等の高融点金属粉末から成
り、タングステン等の高融点金属粉末に適当な有機バイ
ンダー、可塑剤、溶剤を添加混合して得た金属ペースト
を絶縁基体１となるセラミックグリーンシートに予め従
来周知のスクリーン印刷法により所定パターンに印刷塗
布しておくことによって絶縁基体１の所定位置に所定パ
ターンに被着形成される。The metallized wiring layer 5 and the connection pad 6
Is made of a high melting point metal powder such as tungsten or molybdenum, and a metal paste obtained by adding a suitable organic binder, a plasticizer, and a solvent to the high melting point metal powder such as tungsten is mixed in advance on a ceramic green sheet serving as the insulating substrate 1. By printing and applying a predetermined pattern by a conventionally well-known screen printing method, a predetermined pattern is adhered and formed at a predetermined position of the insulating substrate 1.
【００１５】前記メタライズ配線層５は半導体素子３の
各電極を後述する接続パッド６に取着されるボール状端
子７に電気的に接続させる作用を為し、絶縁基体１の凹
部１ａ底面に露出するメタライズ配線層５の一端には半
導体素子３の各電極がフリップチップ接続、具体的には
凹部１ａ底面に露出するメタライズ配線層５に半導体素
子３の各電極を間に半田ボールを挟んで載置対向させ、
しかる後、これを２５０〜３００℃に加熱して半田ボー
ルを溶融させ、メタライズ配線層５と半導体素子３の電
極とを半田ボールを介し接合させることによって接続さ
れる。この場合、半導体素子３はその電極数が多いとし
ても各電極は絶縁基体１の凹部１ａ底面に露出するメタ
ライズ配線層５に一度に確実に接続され、これによって
半導体素子３の収容の作業性を極めて優れたものとし、
最終製品としての半導体装置を安価となすことができ
る。The metallized wiring layer 5 functions to electrically connect each electrode of the semiconductor element 3 to a ball-shaped terminal 7 attached to a connection pad 6 described later, and is exposed on the bottom surface of the concave portion 1a of the insulating base 1. Each electrode of the semiconductor element 3 is flip-chip connected to one end of the metallized wiring layer 5 to be formed. More specifically, each electrode of the semiconductor element 3 is mounted on the metallized wiring layer 5 exposed on the bottom surface of the recess 1a with a solder ball interposed therebetween. To face each other,
Thereafter, the solder ball is heated to 250 to 300 ° C. to melt the solder ball, and the metallized wiring layer 5 and the electrode of the semiconductor element 3 are connected to each other via the solder ball. In this case, even if the semiconductor element 3 has a large number of electrodes, each electrode is reliably connected to the metallized wiring layer 5 exposed at the bottom of the concave portion 1a of the insulating base 1 at a time, thereby improving the workability of housing the semiconductor element 3. Very good,
The semiconductor device as the final product can be made inexpensive.
【００１６】また前記メタライズ配線層５と電気的に接
続されている接続パッド６は絶縁基体１にボール状端子
７を取着する際の下地金属層として作用し、接続パッド
６の表面には半田から成るボール状端子７が取着されて
いる。The connection pad 6 electrically connected to the metallized wiring layer 5 functions as a base metal layer when the ball-shaped terminal 7 is attached to the insulating base 1. Is mounted.
【００１７】前記接続パッド６に取着されている半田か
ら成るボール状端子７は接続パッド６を外部電気回路基
板１０の配線導体１１に容易、且つ確実に接続させる作
用を為し、接続パッド６の表面にボール状の半田を載置
させ、しかる後、その一部を加熱溶融させることによっ
て接続パッド６の表面に取着される。The ball-shaped terminals 7 made of solder attached to the connection pads 6 serve to easily and surely connect the connection pads 6 to the wiring conductors 11 of the external electric circuit board 10. Is mounted on the surface of the connection pad 6 by heating and melting a portion thereof.
【００１８】尚、前記メタライズ配線層５及び接続パッ
ド６の露出表面にニッケル、金等の耐蝕性に優れ、且つ
半田等のロウ材と濡れ性が良い金属をメッキ法により１
μｍ乃至２０μｍの厚みに被着させておくとメタライズ
配線層５及び接続パッド６の酸化腐食を有効に防止する
ことができるとともにメタライズ配線層５と半導体素子
３の電極との接続及び接続パッド６へのボール状端子７
の取着を強固となすこができる。従って、前記メタライ
ズ配線層５及び接続パッド６の露出表面にはニッケル、
金等の耐蝕性に優れ、且つ半田等のロウ材と濡れ性が良
い金属をメッキ法により１μｍ乃至２０μｍの厚みに被
着させておくことが好ましい。On the exposed surfaces of the metallized wiring layer 5 and the connection pads 6, a metal such as nickel or gold having excellent corrosion resistance and a good wettability with a brazing material such as solder is plated by a plating method.
When the metallized wiring layer 5 and the connection pad 6 are adhered to a thickness of 20 μm to 20 μm, oxidation corrosion of the metallized wiring layer 5 and the connection pad 6 can be effectively prevented, and the connection between the metallized wiring layer 5 and the electrode of the semiconductor element 3 and the connection pad 6 Ball-shaped terminal 7
Can be attached firmly. Therefore, the exposed surfaces of the metallized wiring layer 5 and the connection pad 6 are made of nickel,
It is preferable that a metal such as gold having excellent corrosion resistance and a good wettability with a brazing material such as solder is applied to a thickness of 1 μm to 20 μm by plating.
【００１９】また一方、前記絶縁基体１はその上面で凹
部１ａ周辺に枠状のメタライズ金属層８が被着されてお
り、該メタライズ金属層８に金−錫合金等のロウ材から
成る封止材を介して金属製蓋体２が取着され、これによ
って絶縁基体１と金属製蓋体２とから成る容器４の内部
が気密に封止される。On the other hand, a frame-shaped metallized metal layer 8 is attached on the upper surface of the insulating substrate 1 around the concave portion 1a, and the metallized metal layer 8 is sealed with a brazing material such as a gold-tin alloy. The metal lid 2 is attached via the material, whereby the inside of the container 4 including the insulating base 1 and the metal lid 2 is hermetically sealed.
【００２０】前記金属製蓋体２は容器４の内部に半導体
素子３を気密に収容する作用を為し、銅や銅−タングス
テン合金等の金属材料で形成されており、銅等のインゴ
ット（塊）を圧延加工法や打ち抜き加工法等、従来周知
の金属加工法により所定の板状となすことによって形成
されている。The metal lid 2 serves to hermetically accommodate the semiconductor element 3 inside the container 4 and is made of a metal material such as copper or a copper-tungsten alloy. ) Is formed into a predetermined plate shape by a conventionally known metal working method such as a rolling method or a punching method.
【００２１】また前記金属製蓋体２は絶縁基体１の上部
に封止材を介して取着する際、下面が絶縁基体１の凹部
１ａ内に収容する半導体素子３の一主面と当接するよう
になっており、これによって半導体素子３の作動時に発
する熱は金属製蓋体２を介して外部に良好に放出され、
半導体素子３を常に適温として長期間にわたり正常、且
つ安定に作動させることが可能となる。When the metal lid 2 is attached to the upper portion of the insulating base 1 via a sealing material, the lower surface contacts one main surface of the semiconductor element 3 housed in the recess 1a of the insulating base 1. As a result, heat generated when the semiconductor element 3 is operated is satisfactorily released to the outside through the metal lid 2,
The semiconductor element 3 can be normally and stably operated over a long period of time at an appropriate temperature.
【００２２】尚、前記金属製蓋体２及び該金属製蓋体２
が取着される枠状のメタライズ金属層８はその表面にニ
ッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性の良
い金属をメッキ法により１μｍ乃至２０μｍの厚みに被
着させておくと、金属製蓋体２及びメタライズ金属層８
の酸化腐食が有効に防止されるとともにメタライズ金属
層８への金属製蓋体２のロウ材から成る封止材を介して
の取着を強固となすことができる。従って、前記金属製
蓋体２及び該金属製蓋体２が取着される枠状のメタライ
ズ金属層８の表面にはニッケル、金等の耐蝕性に優れ、
且つロウ材と濡れ性の良い金属をメッキ法により１μｍ
乃至２０μｍの厚みに被着させておくことが好ましい。The metal cover 2 and the metal cover 2
The metallized metal layer 8 in the form of a frame is coated with a metal having excellent corrosion resistance such as nickel and gold and a good wettability with a brazing material to a thickness of 1 μm to 20 μm by plating. And metal cover 2 and metallized metal layer 8
Is effectively prevented, and the metal cover 2 can be firmly attached to the metallized metal layer 8 via a sealing material made of a brazing material. Therefore, the surfaces of the metal lid 2 and the frame-shaped metallized metal layer 8 to which the metal lid 2 is attached are excellent in corrosion resistance of nickel, gold or the like,
1μm of metal with good wettability with brazing material by plating
Preferably, it is applied to a thickness of from 20 to 20 μm.
【００２３】また前記金属製蓋体２の外表面に更に放熱
フィン９を取着させておくと該放熱フィン９によって金
属製蓋体２に伝わった半導体素子３の熱をより効率よく
外部に放出することができる。従って、半導体素子３が
作動時に極めて多量の熱を発生する場合には金属製蓋体
２の外表面に放熱フィンを取着させておき、該放熱フィ
ン９で半導体素子３の熱を効率よく放出するようにする
ことが好ましい。Further, if heat radiating fins 9 are further attached to the outer surface of the metal lid 2, the heat of the semiconductor element 3 transmitted to the metal lid 2 by the heat radiating fins 9 is more efficiently radiated to the outside. can do. Therefore, when the semiconductor element 3 generates an extremely large amount of heat during operation, heat radiation fins are attached to the outer surface of the metal lid 2 and the heat radiation fins 9 efficiently release the heat of the semiconductor element 3. It is preferable to do so.
【００２４】かくして本発明の半導体素子収納用パッケ
ージによれば、絶縁基体１の凹部１ａ内に半導体素子３
を、該半導体素子３の各電極を凹部１ａ底面に露出して
いるメタライズ配線層５にフリップチップ接続により接
続した状態で収容し、しかる後、金属製蓋体２を絶縁基
体１の上面に被着させた枠状のメタライズ金属層８に金
−錫合金等のロウ材から成る封止材により接合させ、絶
縁基体１と金属製蓋体２とから成る容器４内部に半導体
素子３を気密に収容することによって製品としての半導
体装置となる。Thus, according to the package for housing a semiconductor element of the present invention, the semiconductor element 3
Are housed in a state where each electrode of the semiconductor element 3 is connected to the metallized wiring layer 5 exposed on the bottom surface of the concave portion 1a by flip-chip connection, and then the metal lid 2 is covered on the upper surface of the insulating base 1. The semiconductor element 3 is hermetically sealed in a container 4 composed of an insulating substrate 1 and a metal lid 2 by joining the frame-shaped metallized metal layer 8 attached thereto with a sealing material made of a brazing material such as a gold-tin alloy. By being accommodated, a semiconductor device as a product is obtained.
【００２５】また前記半導体素子収納用パッケージに半
導体素子３を収容して形成される半導体装置は絶縁基体
１下面のボール状端子７を外部電気回路基板１０の配線
導体１１に接合させることによって外部電気回路基板１
０上に実装され、同時に容器４の内部に収容されている
半導体素子３はその電極がメタライズ配線層５、接続パ
ッド６及びボール状端子７を介して外部電気回路基板１
０の配線導体１１に電気的に接続される。In the semiconductor device formed by housing the semiconductor element 3 in the semiconductor element housing package, the ball-shaped terminals 7 on the lower surface of the insulating base 1 are joined to the wiring conductors 11 of the external electric circuit board 10 to provide an external electric device. Circuit board 1
The semiconductor element 3 mounted on the semiconductor chip 3 and accommodated in the container 4 at the same time has its electrodes connected to the external electric circuit board 1 via the metallized wiring layer 5, the connection pads 6 and the ball-shaped terminals 7.
0 is electrically connected to the wiring conductor 11.
【００２６】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention.
【００２７】[0027]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、電気絶縁材料の焼結体から成る絶縁基体の半導
体素子を収容する凹部底面にタングステンまたはモリブ
デンから成り１μｍ乃至２０μｍの厚みのニッケルまた
は金が被着されたメタライズ配線層の一端を導出させた
ことから、該メタライズ配線層に半導体素子の各電極を
フリップチップ接続により接続することができ、その結
果、半導体素子の電極数が多いとしてもその全てを所定
のメタライズ配線層に一度に接続することが可能となっ
て半導体素子の収容の作業性が極めて優れたものとなる
とともに、半導体素子の電極との接続を強固となすこと
ができる。また、凹部周辺の上面にタングステンまたは
モリブデンから成り１μｍ乃至２０μｍの厚みのニッケ
ルまたは金が被着された枠状のメタライズ金属層を有す
ることから、絶縁基体の上面に金−錫合金から成る封止
材を介して金属製蓋体を取着して内部に収容する半導体
素子を気密に封止することができる。さらに、下面にメ
タライズ配線層に電気的に接続されたタングステンまた
はモリブデンから成り１μｍ乃至２０μｍの厚みのニッ
ケルまたは金が被着された接続パッドを有することか
ら、ボール状端子を介して外部電気回路基板の配線導体
に容易、且つ確実に接続することができる。According to the package for housing a semiconductor element of the present invention, nickel or tungsten having a thickness of 1 μm to 20 μm made of tungsten or molybdenum is formed on the bottom surface of a concave portion for housing a semiconductor element of an insulating base made of a sintered body of an electrically insulating material. Since one end of the metallized wiring layer to which gold is applied is led out, each electrode of the semiconductor element can be connected to the metallized wiring layer by flip-chip connection. As a result, the number of electrodes of the semiconductor element is large. All of them can be connected to a predetermined metallized wiring layer at a time, so that the workability of accommodating the semiconductor element is extremely excellent, and the connection with the electrode of the semiconductor element can be made firm. . In addition, since a frame-shaped metallized metal layer made of tungsten or molybdenum and having a thickness of 1 μm to 20 μm and coated with nickel or gold is provided on the upper surface around the concave portion, the upper surface of the insulating base is sealed with a gold-tin alloy. It is possible to hermetically seal a semiconductor element housed inside by attaching a metal lid through a material. Furthermore, since the lower surface has connection pads made of tungsten or molybdenum electrically connected to the metallized wiring layer and coated with nickel or gold having a thickness of 1 μm to 20 μm, the external electric circuit board is connected via the ball-shaped terminals. Can be easily and reliably connected to the wiring conductor.
【００２８】また本発明の半導体素子収納用パッケージ
によれば、銅または銅−タングステン合金から成る金属
製蓋体の下面が内部に収容する半導体素子の一主面に当
接することから、半導体素子が作動時に発する熱は金属
製蓋体を介して外部に良好に放出され、その結果、半導
体素子を常に適温として半導体素子を長期間にわたり正
常、且つ安定に作動させることができる。According to the package for accommodating a semiconductor element of the present invention, the lower surface of the metal lid made of copper or copper-tungsten alloy is in contact with one main surface of the semiconductor element accommodated therein. The heat generated during operation is satisfactorily released to the outside through the metal lid, and as a result, the semiconductor element can always be kept at an appropriate temperature to operate normally and stably for a long period of time.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
【図２】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 2 is a cross-sectional view of a conventional semiconductor element storage package.
１・・・・・・絶縁基体 １ａ・・・・・凹部 ２・・・・・・金属製蓋体 ３・・・・・・半導体素子 ４・・・・・・絶縁容器 ５・・・・・・メタライズ配線層 ６・・・・・・接続パッド ７・・・・・・ボール状端子 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 2 ... Metal lid 3 ... Semiconductor element 4 ... Insulating container 5 ... ..Metalized wiring layers 6 Connection pads 7 Ball terminals
Claims (2)
有し、該凹部底面から下面にかけて半導体素子の各電極
がフリップチップ接続により接続されるタングステンま
たはモリブデンから成り１μｍ乃至２０μｍの厚みのニ
ッケルまたは金が被着された複数個のメタライズ配線
層、および下面に前記メタライズ配線層に電気的に接続
されたタングステンまたはモリブデンから成り１μｍ乃
至２０μｍの厚みのニッケルまたは金が被着された接続
パッド、ならびに前記凹部周辺の上面にタングステンま
たはモリブデンから成り１μｍ乃至２０μｍの厚みのニ
ッケルまたは金が被着された枠状のメタライズ金属層を
有する電気絶縁材料の焼結体から成る絶縁基体と、前記
絶縁基体の上面の前記メタライズ金属層に金−錫合金か
ら成る封止材を介して取着され、且つその下面に内部に
収容する半導体素子の一主面が当接する銅または銅−タ
ングステン合金から成る金属製蓋体とから成ることを特
徴とする半導体素子収納用パッケージ。An upper surface has a concave portion for accommodating a semiconductor element, and from the bottom surface of the concave portion to the lower surface, each electrode of the semiconductor element is connected to tungsten or the like by flip-chip connection.
Or d. Made of molybdenum and having a thickness of 1 μm to 20 μm.
A plurality of metallized wiring layers coated with nickel or gold , and electrically connected to the metallized wiring layers on the lower surface
Made of tungsten or molybdenum
Connections with nickel or gold deposited to a thickness of 20 μm
Pad and tungsten on the top surface around the recess
Or d. Made of molybdenum and having a thickness of 1 μm to 20 μm.
An insulating base made of a sintered body of an electrical insulating material having a frame-shaped metallized metal layer to which nickel or gold is adhered ; and a gold-tin alloy formed on the metallized metal layer on the upper surface of the insulating base .
Copper or copper tape which is attached via a sealing material made of the above , and whose one lower surface of the semiconductor element housed inside abuts on the lower surface thereof
Patent in that it consists of a metallic lid made of tungsten alloy
Semiconductor device package for housing and butterflies.
着されていることを特徴とする請求項１に記載の半導体
素子収納用パッケージ。2. The package for accommodating a semiconductor element according to claim 1, wherein heat radiating fins are attached to an outer surface of said metal lid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14050395A JP3210835B2 (en) | 1995-06-07 | 1995-06-07 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14050395A JP3210835B2 (en) | 1995-06-07 | 1995-06-07 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08335650A JPH08335650A (en) | 1996-12-17 |
| JP3210835B2 true JP3210835B2 (en) | 2001-09-25 |
Family
ID=15270163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14050395A Expired - Fee Related JP3210835B2 (en) | 1995-06-07 | 1995-06-07 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3210835B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7061102B2 (en) | 2001-06-11 | 2006-06-13 | Xilinx, Inc. | High performance flipchip package that incorporates heat removal with minimal thermal mismatch |
| JP3907461B2 (en) * | 2001-12-03 | 2007-04-18 | シャープ株式会社 | Manufacturing method of semiconductor module |
| US6724079B2 (en) * | 2002-01-04 | 2004-04-20 | Motorola, Inc. | Wire bond-less electronic component for use with an external circuit and method of manufacture |
| US9425116B2 (en) | 2011-05-09 | 2016-08-23 | Infineon Technologies Ag | Integrated circuit package and a method for manufacturing an integrated circuit package |
| US9105562B2 (en) | 2011-05-09 | 2015-08-11 | Infineon Technologies Ag | Integrated circuit package and packaging methods |
| US9269685B2 (en) | 2011-05-09 | 2016-02-23 | Infineon Technologies Ag | Integrated circuit package and packaging methods |
| DE102012112328A1 (en) * | 2011-12-15 | 2013-06-20 | Infineon Technologies Ag | Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module |
-
1995
- 1995-06-07 JP JP14050395A patent/JP3210835B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08335650A (en) | 1996-12-17 |
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